1 //===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 def HasMSA : Predicate<"Subtarget.hasMSA()">,
11 AssemblerPredicate<"FeatureMSA">;
13 class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
14 let Predicates = [HasMSA];
15 let Inst{31-26} = 0b011110;
18 class PseudoMSA<dag outs, dag ins, list<dag> pattern,
19 InstrItinClass itin = IIPseudo>:
20 MipsPseudo<outs, ins, pattern, itin> {
21 let Predicates = [HasMSA];
24 class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
25 let Inst{25-23} = major;
26 let Inst{22-19} = 0b1110;
27 let Inst{5-0} = minor;
30 class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
31 let Inst{25-23} = major;
32 let Inst{22-20} = 0b110;
33 let Inst{5-0} = minor;
36 class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
37 let Inst{25-23} = major;
38 let Inst{22-21} = 0b10;
39 let Inst{5-0} = minor;
42 class MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst {
43 let Inst{25-23} = major;
45 let Inst{5-0} = minor;
48 class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
52 let Inst{25-18} = major;
56 let Inst{5-0} = minor;
59 class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
63 let Inst{25-18} = major;
67 let Inst{5-0} = minor;
70 class MSA_2RF_FMT<bits<9> major, bits<1> df, bits<6> minor>: MSAInst {
74 let Inst{25-17} = major;
78 let Inst{5-0} = minor;
81 class MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
86 let Inst{25-23} = major;
91 let Inst{5-0} = minor;
94 class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst {
99 let Inst{25-22} = major;
101 let Inst{20-16} = wt;
102 let Inst{15-11} = ws;
104 let Inst{5-0} = minor;
107 class MSA_ELM_FMT<bits<10> major, bits<6> minor>: MSAInst {
108 let Inst{25-16} = major;
109 let Inst{5-0} = minor;
112 class MSA_ELM_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
113 let Inst{25-22} = major;
114 let Inst{21-20} = 0b00;
115 let Inst{5-0} = minor;
118 class MSA_ELM_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
119 let Inst{25-22} = major;
120 let Inst{21-19} = 0b100;
121 let Inst{5-0} = minor;
124 class MSA_ELM_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
125 let Inst{25-22} = major;
126 let Inst{21-18} = 0b1100;
127 let Inst{5-0} = minor;
130 class MSA_ELM_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
131 let Inst{25-22} = major;
132 let Inst{21-17} = 0b11100;
133 let Inst{5-0} = minor;
136 class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
141 let Inst{25-23} = major;
142 let Inst{22-21} = df;
143 let Inst{20-16} = imm;
144 let Inst{15-11} = ws;
146 let Inst{5-0} = minor;
149 class MSA_I8_FMT<bits<2> major, bits<6> minor>: MSAInst {
154 let Inst{25-24} = major;
155 let Inst{23-16} = u8;
156 let Inst{15-11} = ws;
158 let Inst{5-0} = minor;
161 class MSA_I10_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
162 let Inst{25-23} = major;
163 let Inst{22-21} = df;
164 let Inst{5-0} = minor;
167 class MSA_VEC_FMT<bits<5> major, bits<6> minor>: MSAInst {
168 let Inst{25-21} = major;
169 let Inst{5-0} = minor;
172 class MSA_VECS10_FMT<bits<5> major, bits<6> minor>: MSAInst {
173 let Inst{25-21} = major;
174 let Inst{5-0} = minor;