1 //===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 def HasMSA : Predicate<"Subtarget.hasMSA()">,
11 AssemblerPredicate<"FeatureMSA">;
13 class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
14 let Predicates = [HasMSA];
15 let Inst{31-26} = 0b011110;
18 class PseudoMSA<dag outs, dag ins, list<dag> pattern,
19 InstrItinClass itin = IIPseudo>:
20 MipsPseudo<outs, ins, pattern, itin> {
21 let Predicates = [HasMSA];
24 class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
29 let Inst{25-23} = major;
30 let Inst{22-19} = 0b1110;
34 let Inst{5-0} = minor;
37 class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
42 let Inst{25-23} = major;
43 let Inst{22-20} = 0b110;
47 let Inst{5-0} = minor;
50 class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
55 let Inst{25-23} = major;
56 let Inst{22-21} = 0b10;
60 let Inst{5-0} = minor;
63 class MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst {
68 let Inst{25-23} = major;
73 let Inst{5-0} = minor;
76 class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
80 let Inst{25-18} = major;
84 let Inst{5-0} = minor;
87 class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
91 let Inst{25-18} = major;
95 let Inst{5-0} = minor;
98 class MSA_2RF_FMT<bits<9> major, bits<1> df, bits<6> minor>: MSAInst {
102 let Inst{25-17} = major;
104 let Inst{15-11} = ws;
106 let Inst{5-0} = minor;
109 class MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
114 let Inst{25-23} = major;
115 let Inst{22-21} = df;
116 let Inst{20-16} = wt;
117 let Inst{15-11} = ws;
119 let Inst{5-0} = minor;
122 class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst {
127 let Inst{25-22} = major;
129 let Inst{20-16} = wt;
130 let Inst{15-11} = ws;
132 let Inst{5-0} = minor;
135 class MSA_3R_INDEX_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
140 let Inst{25-23} = major;
141 let Inst{22-21} = df;
142 let Inst{20-16} = rt;
143 let Inst{15-11} = ws;
145 let Inst{5-0} = minor;
148 class MSA_ELM_FMT<bits<10> major, bits<6> minor>: MSAInst {
152 let Inst{25-16} = major;
153 let Inst{15-11} = ws;
155 let Inst{5-0} = minor;
158 class MSA_ELM_CFCMSA_FMT<bits<10> major, bits<6> minor>: MSAInst {
162 let Inst{25-16} = major;
163 let Inst{15-11} = cs;
165 let Inst{5-0} = minor;
168 class MSA_ELM_CTCMSA_FMT<bits<10> major, bits<6> minor>: MSAInst {
172 let Inst{25-16} = major;
173 let Inst{15-11} = rs;
175 let Inst{5-0} = minor;
178 class MSA_ELM_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
183 let Inst{25-22} = major;
184 let Inst{21-20} = 0b00;
185 let Inst{19-16} = n{3-0};
186 let Inst{15-11} = ws;
188 let Inst{5-0} = minor;
191 class MSA_ELM_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
196 let Inst{25-22} = major;
197 let Inst{21-19} = 0b100;
198 let Inst{18-16} = n{2-0};
199 let Inst{15-11} = ws;
201 let Inst{5-0} = minor;
204 class MSA_ELM_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
209 let Inst{25-22} = major;
210 let Inst{21-18} = 0b1100;
211 let Inst{17-16} = n{1-0};
212 let Inst{15-11} = ws;
214 let Inst{5-0} = minor;
217 class MSA_ELM_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
222 let Inst{25-22} = major;
223 let Inst{21-17} = 0b11100;
225 let Inst{15-11} = ws;
227 let Inst{5-0} = minor;
230 class MSA_ELM_COPY_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
235 let Inst{25-22} = major;
236 let Inst{21-20} = 0b00;
237 let Inst{19-16} = n{3-0};
238 let Inst{15-11} = ws;
240 let Inst{5-0} = minor;
243 class MSA_ELM_COPY_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
248 let Inst{25-22} = major;
249 let Inst{21-19} = 0b100;
250 let Inst{18-16} = n{2-0};
251 let Inst{15-11} = ws;
253 let Inst{5-0} = minor;
256 class MSA_ELM_COPY_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
261 let Inst{25-22} = major;
262 let Inst{21-18} = 0b1100;
263 let Inst{17-16} = n{1-0};
264 let Inst{15-11} = ws;
266 let Inst{5-0} = minor;
269 class MSA_ELM_INSERT_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
274 let Inst{25-22} = major;
275 let Inst{21-20} = 0b00;
276 let Inst{19-16} = n{3-0};
277 let Inst{15-11} = rs;
279 let Inst{5-0} = minor;
282 class MSA_ELM_INSERT_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
287 let Inst{25-22} = major;
288 let Inst{21-19} = 0b100;
289 let Inst{18-16} = n{2-0};
290 let Inst{15-11} = rs;
292 let Inst{5-0} = minor;
295 class MSA_ELM_INSERT_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
300 let Inst{25-22} = major;
301 let Inst{21-18} = 0b1100;
302 let Inst{17-16} = n{1-0};
303 let Inst{15-11} = rs;
305 let Inst{5-0} = minor;
308 class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
313 let Inst{25-23} = major;
314 let Inst{22-21} = df;
315 let Inst{20-16} = imm;
316 let Inst{15-11} = ws;
318 let Inst{5-0} = minor;
321 class MSA_I8_FMT<bits<2> major, bits<6> minor>: MSAInst {
326 let Inst{25-24} = major;
327 let Inst{23-16} = u8;
328 let Inst{15-11} = ws;
330 let Inst{5-0} = minor;
333 class MSA_I10_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
334 let Inst{25-23} = major;
335 let Inst{22-21} = df;
336 let Inst{5-0} = minor;
339 class MSA_VEC_FMT<bits<5> major, bits<6> minor>: MSAInst {
344 let Inst{25-21} = major;
345 let Inst{20-16} = wt;
346 let Inst{15-11} = ws;
348 let Inst{5-0} = minor;
351 class MSA_VECS10_FMT<bits<5> major, bits<6> minor>: MSAInst {
352 let Inst{25-21} = major;
353 let Inst{5-0} = minor;
356 class SPECIAL_LSA_FMT: MSAInst {
357 let Inst{25-21} = 0b000000;
358 let Inst{10-8} = 0b000;
359 let Inst{5-0} = 0b000101;