1 //===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips MSA ASE instructions.
12 //===----------------------------------------------------------------------===//
14 def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;
15 def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
18 SDTCisVT<3, OtherVT>]>;
19 def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
22 SDTCisVT<3, OtherVT>]>;
23 def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>,
24 SDTCisInt<1>, SDTCisVec<1>,
25 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>;
26 def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
27 SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>;
28 def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
29 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
31 def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>;
32 def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>;
33 def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>;
34 def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>;
35 def MipsVSMax : SDNode<"MipsISD::VSMAX", SDTIntBinOp,
36 [SDNPCommutative, SDNPAssociative]>;
37 def MipsVSMin : SDNode<"MipsISD::VSMIN", SDTIntBinOp,
38 [SDNPCommutative, SDNPAssociative]>;
39 def MipsVUMax : SDNode<"MipsISD::VUMAX", SDTIntBinOp,
40 [SDNPCommutative, SDNPAssociative]>;
41 def MipsVUMin : SDNode<"MipsISD::VUMIN", SDTIntBinOp,
42 [SDNPCommutative, SDNPAssociative]>;
43 def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp,
44 [SDNPCommutative, SDNPAssociative]>;
45 def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>;
46 def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>;
47 def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>;
48 def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>;
49 def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>;
50 def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>;
51 def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>;
52 def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>;
54 def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>;
55 def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>;
57 def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT",
58 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
59 def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT",
60 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
64 def uimm2 : Operand<i32> {
65 let PrintMethod = "printUnsignedImm";
68 def uimm3 : Operand<i32> {
69 let PrintMethod = "printUnsignedImm8";
72 def uimm4 : Operand<i32> {
73 let PrintMethod = "printUnsignedImm8";
76 def uimm8 : Operand<i32> {
77 let PrintMethod = "printUnsignedImm8";
80 def simm5 : Operand<i32>;
82 def simm10 : Operand<i32>;
84 def vsplat_uimm1 : Operand<vAny> {
85 let PrintMethod = "printUnsignedImm8";
88 def vsplat_uimm2 : Operand<vAny> {
89 let PrintMethod = "printUnsignedImm8";
92 def vsplat_uimm3 : Operand<vAny> {
93 let PrintMethod = "printUnsignedImm8";
96 def vsplat_uimm4 : Operand<vAny> {
97 let PrintMethod = "printUnsignedImm8";
100 def vsplat_uimm5 : Operand<vAny> {
101 let PrintMethod = "printUnsignedImm8";
104 def vsplat_uimm6 : Operand<vAny> {
105 let PrintMethod = "printUnsignedImm8";
108 def vsplat_uimm8 : Operand<vAny> {
109 let PrintMethod = "printUnsignedImm8";
112 def vsplat_simm5 : Operand<vAny>;
114 def vsplat_simm10 : Operand<vAny>;
116 def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>;
119 def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx),
120 (MipsVExtractSExt node:$vec, node:$idx, i8)>;
121 def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx),
122 (MipsVExtractSExt node:$vec, node:$idx, i16)>;
123 def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx),
124 (MipsVExtractSExt node:$vec, node:$idx, i32)>;
126 def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx),
127 (MipsVExtractZExt node:$vec, node:$idx, i8)>;
128 def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx),
129 (MipsVExtractZExt node:$vec, node:$idx, i16)>;
130 def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx),
131 (MipsVExtractZExt node:$vec, node:$idx, i32)>;
133 def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx),
134 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>;
135 def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx),
136 (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>;
137 def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx),
138 (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>;
140 class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> :
141 PatFrag<(ops node:$lhs, node:$rhs),
142 (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>;
144 // ISD::SETFALSE cannot occur
145 def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
146 def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
147 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
148 def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
149 def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>;
150 def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>;
151 def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>;
152 def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>;
153 def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>;
154 def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>;
155 def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>;
156 def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>;
157 def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>;
158 def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>;
159 def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>;
160 def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>;
161 def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>;
162 def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>;
163 def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>;
164 def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>;
165 def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>;
166 def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>;
167 def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>;
168 def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>;
169 def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
170 def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
171 def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>;
172 def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>;
173 // ISD::SETTRUE cannot occur
174 // ISD::SETFALSE2 cannot occur
175 // ISD::SETTRUE2 cannot occur
177 class vsetcc_type<ValueType ResTy, CondCode CC> :
178 PatFrag<(ops node:$lhs, node:$rhs),
179 (ResTy (vsetcc node:$lhs, node:$rhs, CC))>;
181 def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>;
182 def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>;
183 def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>;
184 def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>;
185 def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>;
186 def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>;
187 def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>;
188 def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>;
189 def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>;
190 def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>;
191 def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>;
192 def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>;
193 def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>;
194 def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>;
195 def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>;
196 def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>;
197 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
198 def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
199 def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
200 def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
202 def vsplati8 : PatFrag<(ops node:$e0),
203 (v16i8 (build_vector node:$e0, node:$e0,
210 node:$e0, node:$e0))>;
211 def vsplati16 : PatFrag<(ops node:$e0),
212 (v8i16 (build_vector node:$e0, node:$e0,
215 node:$e0, node:$e0))>;
216 def vsplati32 : PatFrag<(ops node:$e0),
217 (v4i32 (build_vector node:$e0, node:$e0,
218 node:$e0, node:$e0))>;
219 def vsplati64 : PatFrag<(ops node:$e0),
220 (v2i64 (build_vector:$v0 node:$e0, node:$e0))>;
221 def vsplatf32 : PatFrag<(ops node:$e0),
222 (v4f32 (build_vector node:$e0, node:$e0,
223 node:$e0, node:$e0))>;
224 def vsplatf64 : PatFrag<(ops node:$e0),
225 (v2f64 (build_vector node:$e0, node:$e0))>;
227 def vsplati8_elt : PatFrag<(ops node:$v, node:$i),
228 (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>;
229 def vsplati16_elt : PatFrag<(ops node:$v, node:$i),
230 (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>;
231 def vsplati32_elt : PatFrag<(ops node:$v, node:$i),
232 (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>;
233 def vsplati64_elt : PatFrag<(ops node:$v, node:$i),
234 (MipsVSHF (vsplati64 node:$i), node:$v, node:$v)>;
236 class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}],
237 SDNodeXForm xform = NOOP_SDNodeXForm>
238 : PatLeaf<frag, pred, xform> {
239 Operand OpClass = opclass;
242 class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn,
243 list<SDNode> roots = [],
244 list<SDNodeProperty> props = []> :
245 ComplexPattern<ty, numops, fn, roots, props> {
246 Operand OpClass = opclass;
249 def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1,
251 [build_vector, bitconvert]>;
253 def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1,
255 [build_vector, bitconvert]>;
257 def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1,
259 [build_vector, bitconvert]>;
261 def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1,
263 [build_vector, bitconvert]>;
265 def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1,
267 [build_vector, bitconvert]>;
269 def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1,
271 [build_vector, bitconvert]>;
273 def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1,
275 [build_vector, bitconvert]>;
277 def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1,
279 [build_vector, bitconvert]>;
281 def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1,
283 [build_vector, bitconvert]>;
285 def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1,
287 [build_vector, bitconvert]>;
289 def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1,
291 [build_vector, bitconvert]>;
293 def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1,
295 [build_vector, bitconvert]>;
297 def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1,
299 [build_vector, bitconvert]>;
301 def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1,
303 [build_vector, bitconvert]>;
305 def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1,
307 [build_vector, bitconvert]>;
309 def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1,
311 [build_vector, bitconvert]>;
313 // Any build_vector that is a constant splat with a value that is an exact
315 def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2",
316 [build_vector, bitconvert]>;
318 // Any build_vector that is a constant splat with a value that is the bitwise
319 // inverse of an exact power of 2
320 def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2",
321 [build_vector, bitconvert]>;
323 // Any build_vector that is a constant splat with only a consecutive sequence
324 // of left-most bits set.
325 def vsplat_maskl_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1,
327 [build_vector, bitconvert]>;
329 // Any build_vector that is a constant splat with only a consecutive sequence
330 // of right-most bits set.
331 def vsplat_maskr_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1,
333 [build_vector, bitconvert]>;
335 // Any build_vector that is a constant splat with a value that equals 1
336 // FIXME: These should be a ComplexPattern but we can't use them because the
337 // ISel generator requires the uses to have a name, but providing a name
338 // causes other errors ("used in pattern but not operand list")
339 def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{
341 EVT EltTy = N->getValueType(0).getVectorElementType();
343 return selectVSplat (N, Imm) &&
344 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
347 def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{
349 SDNode *BV = N->getOperand(0).getNode();
350 EVT EltTy = N->getValueType(0).getVectorElementType();
352 return selectVSplat (BV, Imm) &&
353 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
356 def vbclr_b : PatFrag<(ops node:$ws, node:$wt),
357 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
359 def vbclr_h : PatFrag<(ops node:$ws, node:$wt),
360 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
362 def vbclr_w : PatFrag<(ops node:$ws, node:$wt),
363 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
365 def vbclr_d : PatFrag<(ops node:$ws, node:$wt),
366 (and node:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1),
368 (bitconvert (v4i32 immAllOnesV))))>;
370 def vbneg_b : PatFrag<(ops node:$ws, node:$wt),
371 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
372 def vbneg_h : PatFrag<(ops node:$ws, node:$wt),
373 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
374 def vbneg_w : PatFrag<(ops node:$ws, node:$wt),
375 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
376 def vbneg_d : PatFrag<(ops node:$ws, node:$wt),
377 (xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
380 def vbset_b : PatFrag<(ops node:$ws, node:$wt),
381 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
382 def vbset_h : PatFrag<(ops node:$ws, node:$wt),
383 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
384 def vbset_w : PatFrag<(ops node:$ws, node:$wt),
385 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
386 def vbset_d : PatFrag<(ops node:$ws, node:$wt),
387 (or node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
390 def fms : PatFrag<(ops node:$wd, node:$ws, node:$wt),
391 (fsub node:$wd, (fmul node:$ws, node:$wt))>;
393 def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt),
394 (add node:$wd, (mul node:$ws, node:$wt))>;
396 def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt),
397 (sub node:$wd, (mul node:$ws, node:$wt))>;
399 def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt),
400 (fmul node:$ws, (fexp2 node:$wt))>;
403 def immSExt5 : ImmLeaf<i32, [{return isInt<5>(Imm);}]>;
404 def immSExt10: ImmLeaf<i32, [{return isInt<10>(Imm);}]>;
406 // Instruction encoding.
407 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
408 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
409 class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
410 class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>;
412 class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>;
413 class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>;
414 class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>;
415 class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>;
417 class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
418 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
419 class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>;
420 class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>;
422 class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>;
423 class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>;
424 class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>;
425 class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>;
427 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
428 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
429 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
430 class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
432 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
433 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
434 class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>;
435 class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>;
437 class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>;
439 class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>;
441 class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>;
442 class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>;
443 class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>;
444 class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>;
446 class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>;
447 class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>;
448 class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>;
449 class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>;
451 class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>;
452 class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>;
453 class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>;
454 class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>;
456 class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>;
457 class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>;
458 class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>;
459 class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>;
461 class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>;
462 class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>;
463 class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>;
464 class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>;
466 class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>;
467 class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>;
468 class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>;
469 class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>;
471 class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>;
472 class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>;
473 class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>;
474 class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>;
476 class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>;
477 class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>;
478 class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>;
479 class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>;
481 class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>;
482 class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>;
483 class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>;
484 class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>;
486 class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>;
487 class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>;
488 class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>;
489 class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>;
491 class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>;
492 class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>;
493 class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>;
494 class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>;
496 class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>;
497 class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>;
498 class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>;
499 class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>;
501 class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>;
503 class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>;
505 class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>;
507 class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>;
509 class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>;
510 class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>;
511 class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>;
512 class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>;
514 class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>;
515 class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>;
516 class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>;
517 class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>;
519 class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>;
520 class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>;
521 class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>;
522 class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>;
524 class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01000>;
526 class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>;
528 class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>;
530 class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>;
531 class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>;
532 class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>;
533 class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>;
535 class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>;
536 class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>;
537 class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>;
538 class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>;
540 class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>;
541 class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>;
542 class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>;
543 class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>;
545 class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>;
547 class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>;
548 class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>;
549 class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>;
550 class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>;
552 class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>;
553 class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>;
554 class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>;
555 class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>;
557 class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>;
559 class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>;
560 class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>;
561 class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>;
562 class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>;
564 class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>;
565 class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>;
566 class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>;
567 class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>;
569 class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>;
570 class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>;
571 class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>;
572 class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>;
574 class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>;
575 class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>;
576 class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>;
577 class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>;
579 class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>;
580 class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>;
581 class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>;
582 class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>;
584 class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>;
585 class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>;
586 class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>;
587 class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>;
589 class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>;
590 class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>;
591 class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>;
592 class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>;
594 class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>;
595 class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>;
596 class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>;
597 class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>;
599 class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>;
600 class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>;
601 class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>;
603 class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
604 class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
605 class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
607 class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>;
609 class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>;
610 class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>;
611 class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>;
612 class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>;
614 class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>;
615 class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>;
616 class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>;
617 class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>;
619 class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>;
620 class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>;
621 class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>;
623 class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>;
624 class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>;
625 class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>;
627 class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>;
628 class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>;
629 class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>;
631 class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>;
632 class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>;
633 class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>;
635 class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>;
636 class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>;
637 class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>;
639 class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>;
640 class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>;
641 class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>;
643 class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>;
644 class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>;
646 class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>;
647 class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>;
649 class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>;
650 class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>;
652 class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>;
653 class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>;
655 class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>;
656 class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>;
658 class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>;
659 class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>;
661 class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
662 class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
664 class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
665 class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
667 class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
668 class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
670 class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>;
671 class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>;
673 class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>;
674 class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>;
676 class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>;
677 class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>;
679 class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>;
680 class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>;
682 class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>;
683 class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>;
685 class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>;
686 class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>;
688 class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>;
689 class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>;
691 class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>;
692 class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>;
694 class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>;
695 class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>;
697 class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>;
698 class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>;
700 class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>;
701 class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>;
703 class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>;
704 class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>;
706 class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>;
707 class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>;
709 class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>;
710 class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>;
711 class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>;
713 class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>;
714 class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>;
716 class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>;
717 class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>;
719 class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>;
720 class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>;
722 class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>;
723 class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>;
725 class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>;
726 class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>;
728 class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>;
729 class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>;
731 class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>;
732 class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>;
734 class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>;
735 class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>;
737 class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>;
738 class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>;
740 class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>;
741 class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>;
743 class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>;
744 class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>;
746 class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>;
747 class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>;
749 class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>;
750 class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>;
752 class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>;
753 class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>;
755 class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>;
756 class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>;
758 class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>;
759 class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>;
761 class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>;
762 class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>;
764 class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>;
765 class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>;
767 class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>;
768 class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>;
770 class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>;
771 class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>;
773 class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>;
774 class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>;
776 class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>;
777 class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>;
779 class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>;
780 class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>;
782 class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>;
783 class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>;
785 class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>;
786 class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>;
788 class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>;
789 class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>;
791 class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>;
792 class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>;
794 class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>;
795 class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>;
797 class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>;
798 class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>;
800 class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>;
801 class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>;
802 class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>;
804 class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>;
805 class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>;
806 class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>;
808 class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>;
809 class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>;
810 class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>;
812 class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>;
813 class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>;
814 class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>;
816 class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>;
817 class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>;
818 class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>;
819 class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>;
821 class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>;
822 class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>;
823 class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>;
824 class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>;
826 class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>;
827 class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>;
828 class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>;
829 class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>;
831 class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>;
832 class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>;
833 class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>;
834 class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>;
836 class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>;
837 class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>;
838 class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>;
840 class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>;
841 class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>;
842 class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>;
843 class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>;
845 class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>;
846 class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>;
847 class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>;
848 class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>;
850 class LDI_B_ENC : MSA_I10_FMT<0b110, 0b00, 0b000111>;
851 class LDI_H_ENC : MSA_I10_FMT<0b110, 0b01, 0b000111>;
852 class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>;
853 class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>;
855 class LSA_ENC : SPECIAL_LSA_FMT<0b000101>;
857 class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;
858 class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
860 class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>;
861 class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>;
863 class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>;
864 class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>;
865 class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>;
866 class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>;
868 class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>;
869 class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>;
870 class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>;
871 class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>;
873 class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>;
874 class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>;
875 class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>;
876 class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>;
878 class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>;
879 class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>;
880 class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>;
881 class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>;
883 class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>;
884 class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>;
885 class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>;
886 class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>;
888 class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>;
889 class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>;
890 class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>;
891 class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>;
893 class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>;
894 class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>;
895 class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>;
896 class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>;
898 class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>;
899 class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>;
900 class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>;
901 class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>;
903 class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>;
904 class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>;
905 class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>;
906 class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>;
908 class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>;
909 class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>;
910 class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>;
911 class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>;
913 class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>;
914 class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>;
915 class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>;
916 class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>;
918 class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>;
919 class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>;
920 class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>;
921 class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>;
923 class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>;
924 class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>;
925 class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>;
926 class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>;
928 class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>;
930 class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>;
931 class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>;
933 class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>;
934 class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>;
936 class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>;
937 class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>;
938 class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>;
939 class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>;
941 class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>;
942 class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>;
944 class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>;
945 class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>;
947 class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>;
948 class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>;
949 class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>;
950 class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>;
952 class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>;
953 class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>;
954 class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>;
955 class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>;
957 class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>;
958 class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>;
959 class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>;
960 class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>;
962 class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>;
964 class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>;
966 class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>;
968 class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>;
970 class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>;
971 class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>;
972 class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>;
973 class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>;
975 class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>;
976 class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>;
977 class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>;
978 class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>;
980 class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>;
981 class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>;
982 class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>;
983 class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>;
985 class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>;
986 class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>;
987 class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>;
988 class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>;
990 class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>;
991 class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>;
992 class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>;
993 class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>;
995 class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>;
996 class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>;
997 class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>;
999 class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>;
1000 class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>;
1001 class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>;
1002 class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>;
1004 class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>;
1005 class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>;
1006 class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>;
1007 class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>;
1009 class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>;
1010 class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>;
1011 class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>;
1012 class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>;
1014 class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>;
1015 class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>;
1016 class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>;
1017 class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>;
1019 class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>;
1020 class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>;
1021 class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>;
1022 class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>;
1024 class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>;
1025 class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>;
1026 class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>;
1027 class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>;
1029 class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>;
1030 class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>;
1031 class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>;
1032 class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>;
1034 class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>;
1035 class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>;
1036 class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>;
1037 class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>;
1039 class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>;
1040 class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>;
1041 class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>;
1042 class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>;
1044 class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>;
1045 class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>;
1046 class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>;
1047 class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>;
1049 class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>;
1050 class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>;
1051 class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>;
1052 class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>;
1054 class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>;
1055 class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>;
1056 class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>;
1057 class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>;
1059 class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>;
1060 class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>;
1061 class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>;
1062 class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>;
1064 class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>;
1065 class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>;
1066 class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>;
1067 class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>;
1069 class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>;
1070 class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>;
1071 class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>;
1072 class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>;
1074 class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>;
1075 class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>;
1076 class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>;
1077 class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>;
1079 class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>;
1080 class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>;
1081 class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>;
1082 class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>;
1084 class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>;
1085 class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>;
1086 class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>;
1087 class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>;
1089 class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>;
1090 class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>;
1091 class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>;
1092 class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>;
1094 class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>;
1095 class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>;
1096 class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>;
1097 class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>;
1099 class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>;
1100 class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>;
1101 class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>;
1102 class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>;
1104 class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>;
1105 class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>;
1106 class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>;
1107 class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>;
1109 class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>;
1111 class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>;
1113 // Instruction desc.
1114 class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1115 ComplexPattern Imm, RegisterOperand ROWD,
1116 RegisterOperand ROWS = ROWD,
1117 InstrItinClass itin = NoItinerary> {
1118 dag OutOperandList = (outs ROWD:$wd);
1119 dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m);
1120 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1121 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1122 InstrItinClass Itinerary = itin;
1125 class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1126 ComplexPattern Imm, RegisterOperand ROWD,
1127 RegisterOperand ROWS = ROWD,
1128 InstrItinClass itin = NoItinerary> {
1129 dag OutOperandList = (outs ROWD:$wd);
1130 dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m);
1131 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1132 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1133 InstrItinClass Itinerary = itin;
1136 class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1137 ComplexPattern Imm, RegisterOperand ROWD,
1138 RegisterOperand ROWS = ROWD,
1139 InstrItinClass itin = NoItinerary> {
1140 dag OutOperandList = (outs ROWD:$wd);
1141 dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m);
1142 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1143 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1144 InstrItinClass Itinerary = itin;
1147 class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1148 ComplexPattern Imm, RegisterOperand ROWD,
1149 RegisterOperand ROWS = ROWD,
1150 InstrItinClass itin = NoItinerary> {
1151 dag OutOperandList = (outs ROWD:$wd);
1152 dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m);
1153 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1154 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1155 InstrItinClass Itinerary = itin;
1158 // This class is deprecated and will be removed soon.
1159 class MSA_BIT_B_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1160 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1161 InstrItinClass itin = NoItinerary> {
1162 dag OutOperandList = (outs ROWD:$wd);
1163 dag InOperandList = (ins ROWS:$ws, uimm3:$m);
1164 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1165 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt3:$m))];
1166 InstrItinClass Itinerary = itin;
1169 // This class is deprecated and will be removed soon.
1170 class MSA_BIT_H_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1171 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1172 InstrItinClass itin = NoItinerary> {
1173 dag OutOperandList = (outs ROWD:$wd);
1174 dag InOperandList = (ins ROWS:$ws, uimm4:$m);
1175 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1176 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt4:$m))];
1177 InstrItinClass Itinerary = itin;
1180 // This class is deprecated and will be removed soon.
1181 class MSA_BIT_W_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1182 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1183 InstrItinClass itin = NoItinerary> {
1184 dag OutOperandList = (outs ROWD:$wd);
1185 dag InOperandList = (ins ROWS:$ws, uimm5:$m);
1186 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1187 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt5:$m))];
1188 InstrItinClass Itinerary = itin;
1191 // This class is deprecated and will be removed soon.
1192 class MSA_BIT_D_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1193 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1194 InstrItinClass itin = NoItinerary> {
1195 dag OutOperandList = (outs ROWD:$wd);
1196 dag InOperandList = (ins ROWS:$ws, uimm6:$m);
1197 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1198 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt6:$m))];
1199 InstrItinClass Itinerary = itin;
1202 class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty,
1203 ComplexPattern Mask, RegisterOperand ROWD,
1204 RegisterOperand ROWS = ROWD,
1205 InstrItinClass itin = NoItinerary> {
1206 dag OutOperandList = (outs ROWD:$wd);
1207 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, vsplat_uimm8:$m);
1208 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1209 list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$wd_in),
1211 InstrItinClass Itinerary = itin;
1212 string Constraints = "$wd = $wd_in";
1215 class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty,
1216 RegisterOperand ROWD,
1217 RegisterOperand ROWS = ROWD,
1218 InstrItinClass itin = NoItinerary> :
1219 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskl_bits, ROWD, ROWS, itin>;
1221 class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty,
1222 RegisterOperand ROWD,
1223 RegisterOperand ROWS = ROWD,
1224 InstrItinClass itin = NoItinerary> :
1225 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskr_bits, ROWD, ROWS, itin>;
1227 class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1228 SplatComplexPattern SplatImm,
1229 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1230 InstrItinClass itin = NoItinerary> {
1231 dag OutOperandList = (outs ROWD:$wd);
1232 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m);
1233 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1234 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))];
1235 InstrItinClass Itinerary = itin;
1238 class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1239 ValueType VecTy, RegisterOperand ROD,
1240 RegisterOperand ROWS,
1241 InstrItinClass itin = NoItinerary> {
1242 dag OutOperandList = (outs ROD:$rd);
1243 dag InOperandList = (ins ROWS:$ws, uimm4:$n);
1244 string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]");
1245 list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), immZExt4:$n))];
1246 InstrItinClass Itinerary = itin;
1249 class MSA_ELM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1250 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1251 InstrItinClass itin = NoItinerary> {
1252 dag OutOperandList = (outs ROWD:$wd);
1253 dag InOperandList = (ins ROWS:$ws, uimm4:$n);
1254 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1255 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt4:$n))];
1256 InstrItinClass Itinerary = itin;
1259 class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy,
1260 RegisterClass RCD, RegisterClass RCWS> :
1261 MipsPseudo<(outs RCD:$wd), (ins RCWS:$ws, uimm4:$n),
1262 [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), immZExt4:$n))]> {
1263 bit usesCustomInserter = 1;
1266 class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1267 SplatComplexPattern SplatImm, RegisterOperand ROWD,
1268 RegisterOperand ROWS = ROWD,
1269 InstrItinClass itin = NoItinerary> {
1270 dag OutOperandList = (outs ROWD:$wd);
1271 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm);
1272 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm");
1273 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))];
1274 InstrItinClass Itinerary = itin;
1277 class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1278 SplatComplexPattern SplatImm, RegisterOperand ROWD,
1279 RegisterOperand ROWS = ROWD,
1280 InstrItinClass itin = NoItinerary> {
1281 dag OutOperandList = (outs ROWD:$wd);
1282 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8);
1283 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1284 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))];
1285 InstrItinClass Itinerary = itin;
1288 // This class is deprecated and will be removed in the next few patches
1289 class MSA_I8_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1290 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1291 InstrItinClass itin = NoItinerary> {
1292 dag OutOperandList = (outs ROWD:$wd);
1293 dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
1294 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1295 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt8:$u8))];
1296 InstrItinClass Itinerary = itin;
1299 class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1300 RegisterOperand ROWS = ROWD,
1301 InstrItinClass itin = NoItinerary> {
1302 dag OutOperandList = (outs ROWD:$wd);
1303 dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
1304 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1305 list<dag> Pattern = [(set ROWD:$wd, (MipsSHF immZExt8:$u8, ROWS:$ws))];
1306 InstrItinClass Itinerary = itin;
1309 class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1310 InstrItinClass itin = NoItinerary> {
1311 dag OutOperandList = (outs ROWD:$wd);
1312 dag InOperandList = (ins vsplat_simm10:$s10);
1313 string AsmString = !strconcat(instr_asm, "\t$wd, $s10");
1314 // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp
1315 list<dag> Pattern = [];
1316 bit hasSideEffects = 0;
1317 InstrItinClass Itinerary = itin;
1320 class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1321 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1322 InstrItinClass itin = NoItinerary> {
1323 dag OutOperandList = (outs ROWD:$wd);
1324 dag InOperandList = (ins ROWS:$ws);
1325 string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1326 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1327 InstrItinClass Itinerary = itin;
1330 class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT,
1331 SDPatternOperator OpNode, RegisterOperand ROWD,
1332 RegisterOperand ROS = ROWD,
1333 InstrItinClass itin = NoItinerary> {
1334 dag OutOperandList = (outs ROWD:$wd);
1335 dag InOperandList = (ins ROS:$rs);
1336 string AsmString = !strconcat(instr_asm, "\t$wd, $rs");
1337 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))];
1338 InstrItinClass Itinerary = itin;
1341 class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode,
1342 RegisterClass RCWD, RegisterClass RCWS = RCWD> :
1343 MipsPseudo<(outs RCWD:$wd), (ins RCWS:$fs),
1344 [(set RCWD:$wd, (OpNode RCWS:$fs))]> {
1345 let usesCustomInserter = 1;
1348 class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1349 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1350 InstrItinClass itin = NoItinerary> {
1351 dag OutOperandList = (outs ROWD:$wd);
1352 dag InOperandList = (ins ROWS:$ws);
1353 string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1354 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1355 InstrItinClass Itinerary = itin;
1358 class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1359 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1360 RegisterOperand ROWT = ROWD,
1361 InstrItinClass itin = NoItinerary> {
1362 dag OutOperandList = (outs ROWD:$wd);
1363 dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1364 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1365 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1366 InstrItinClass Itinerary = itin;
1369 class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1370 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1371 RegisterOperand ROWT = ROWD,
1372 InstrItinClass itin = NoItinerary> {
1373 dag OutOperandList = (outs ROWD:$wd);
1374 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1375 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1376 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1378 string Constraints = "$wd = $wd_in";
1379 InstrItinClass Itinerary = itin;
1382 class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1383 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1384 InstrItinClass itin = NoItinerary> {
1385 dag OutOperandList = (outs ROWD:$wd);
1386 dag InOperandList = (ins ROWS:$ws, GPR32:$rt);
1387 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1388 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32:$rt))];
1389 InstrItinClass Itinerary = itin;
1392 class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1393 RegisterOperand ROWS = ROWD,
1394 RegisterOperand ROWT = ROWD,
1395 InstrItinClass itin = NoItinerary> {
1396 dag OutOperandList = (outs ROWD:$wd);
1397 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1398 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1399 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws,
1401 string Constraints = "$wd = $wd_in";
1402 InstrItinClass Itinerary = itin;
1405 class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1406 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1407 InstrItinClass itin = NoItinerary> {
1408 dag OutOperandList = (outs ROWD:$wd);
1409 dag InOperandList = (ins ROWS:$ws, GPR32:$rt);
1410 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1411 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32:$rt))];
1412 InstrItinClass Itinerary = itin;
1415 class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1416 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1417 RegisterOperand ROWT = ROWD,
1418 InstrItinClass itin = NoItinerary> {
1419 dag OutOperandList = (outs ROWD:$wd);
1420 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1421 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1422 list<dag> Pattern = [(set ROWD:$wd,
1423 (OpNode ROWD:$wd_in, ROWS:$ws, ROWT:$wt))];
1424 InstrItinClass Itinerary = itin;
1425 string Constraints = "$wd = $wd_in";
1428 class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1429 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1430 RegisterOperand ROWT = ROWD,
1431 InstrItinClass itin = NoItinerary> :
1432 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1434 class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1435 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1436 RegisterOperand ROWT = ROWD,
1437 InstrItinClass itin = NoItinerary> :
1438 MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1440 class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> {
1441 dag OutOperandList = (outs);
1442 dag InOperandList = (ins ROWD:$wt, brtarget:$offset);
1443 string AsmString = !strconcat(instr_asm, "\t$wt, $offset");
1444 list<dag> Pattern = [];
1445 InstrItinClass Itinerary = IIBranch;
1447 bit isTerminator = 1;
1448 bit hasDelaySlot = 1;
1449 list<Register> Defs = [AT];
1452 class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1453 RegisterOperand ROWD, RegisterOperand ROS,
1454 InstrItinClass itin = NoItinerary> {
1455 dag OutOperandList = (outs ROWD:$wd);
1456 dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, uimm6:$n);
1457 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs");
1458 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1461 InstrItinClass Itinerary = itin;
1462 string Constraints = "$wd = $wd_in";
1465 class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
1466 RegisterOperand ROWD, RegisterOperand ROFS> :
1467 MipsPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, uimm6:$n, ROFS:$fs),
1468 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
1470 bit usesCustomInserter = 1;
1471 string Constraints = "$wd = $wd_in";
1474 class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1475 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1476 InstrItinClass itin = NoItinerary> {
1477 dag OutOperandList = (outs ROWD:$wd);
1478 dag InOperandList = (ins ROWD:$wd_in, uimm6:$n, ROWS:$ws);
1479 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[0]");
1480 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1483 InstrItinClass Itinerary = itin;
1484 string Constraints = "$wd = $wd_in";
1487 class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1488 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1489 RegisterOperand ROWT = ROWD,
1490 InstrItinClass itin = NoItinerary> {
1491 dag OutOperandList = (outs ROWD:$wd);
1492 dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1493 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1494 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1495 InstrItinClass Itinerary = itin;
1498 class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm,
1499 RegisterOperand ROWD,
1500 RegisterOperand ROWS = ROWD,
1501 InstrItinClass itin = NoItinerary> {
1502 dag OutOperandList = (outs ROWD:$wd);
1503 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n);
1504 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1505 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws,
1507 InstrItinClass Itinerary = itin;
1510 class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD,
1511 RegisterOperand ROWS = ROWD,
1512 RegisterOperand ROWT = ROWD> :
1513 MipsPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt),
1514 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>;
1516 class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>,
1518 class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>,
1520 class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>,
1522 class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>,
1525 class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b,
1526 MSA128BOpnd>, IsCommutable;
1527 class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h,
1528 MSA128HOpnd>, IsCommutable;
1529 class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w,
1530 MSA128WOpnd>, IsCommutable;
1531 class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d,
1532 MSA128DOpnd>, IsCommutable;
1534 class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b,
1535 MSA128BOpnd>, IsCommutable;
1536 class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h,
1537 MSA128HOpnd>, IsCommutable;
1538 class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w,
1539 MSA128WOpnd>, IsCommutable;
1540 class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d,
1541 MSA128DOpnd>, IsCommutable;
1543 class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b,
1544 MSA128BOpnd>, IsCommutable;
1545 class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h,
1546 MSA128HOpnd>, IsCommutable;
1547 class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w,
1548 MSA128WOpnd>, IsCommutable;
1549 class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d,
1550 MSA128DOpnd>, IsCommutable;
1552 class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable;
1553 class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable;
1554 class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable;
1555 class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable;
1557 class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5,
1559 class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5,
1561 class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5,
1563 class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5,
1566 class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>;
1567 class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>;
1568 class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>;
1569 class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>;
1571 class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8,
1574 class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b,
1576 class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h,
1578 class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w,
1580 class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d,
1583 class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b,
1585 class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h,
1587 class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w,
1589 class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d,
1592 class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>,
1594 class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>,
1596 class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>,
1598 class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>,
1601 class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>,
1603 class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>,
1605 class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>,
1607 class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>,
1610 class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b,
1611 MSA128BOpnd>, IsCommutable;
1612 class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h,
1613 MSA128HOpnd>, IsCommutable;
1614 class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w,
1615 MSA128WOpnd>, IsCommutable;
1616 class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d,
1617 MSA128DOpnd>, IsCommutable;
1619 class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b,
1620 MSA128BOpnd>, IsCommutable;
1621 class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h,
1622 MSA128HOpnd>, IsCommutable;
1623 class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w,
1624 MSA128WOpnd>, IsCommutable;
1625 class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d,
1626 MSA128DOpnd>, IsCommutable;
1628 class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>;
1629 class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>;
1630 class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>;
1631 class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>;
1633 class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2,
1635 class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2,
1637 class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2,
1639 class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2,
1642 class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b,
1644 class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h,
1646 class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w,
1648 class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d,
1651 class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, MSA128BOpnd>;
1652 class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, MSA128HOpnd>;
1653 class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, MSA128WOpnd>;
1654 class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, MSA128DOpnd>;
1656 class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b,
1658 class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h,
1660 class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w,
1662 class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d,
1665 class BINSRI_B_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, MSA128BOpnd>;
1666 class BINSRI_H_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, MSA128HOpnd>;
1667 class BINSRI_W_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, MSA128WOpnd>;
1668 class BINSRI_D_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, MSA128DOpnd>;
1671 dag OutOperandList = (outs MSA128BOpnd:$wd);
1672 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1674 string AsmString = "bmnz.v\t$wd, $ws, $wt";
1675 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1677 MSA128BOpnd:$wd_in))];
1678 InstrItinClass Itinerary = NoItinerary;
1679 string Constraints = "$wd = $wd_in";
1682 class BMNZI_B_DESC {
1683 dag OutOperandList = (outs MSA128BOpnd:$wd);
1684 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1686 string AsmString = "bmnzi.b\t$wd, $ws, $u8";
1687 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1689 MSA128BOpnd:$wd_in))];
1690 InstrItinClass Itinerary = NoItinerary;
1691 string Constraints = "$wd = $wd_in";
1695 dag OutOperandList = (outs MSA128BOpnd:$wd);
1696 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1698 string AsmString = "bmz.v\t$wd, $ws, $wt";
1699 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1702 InstrItinClass Itinerary = NoItinerary;
1703 string Constraints = "$wd = $wd_in";
1707 dag OutOperandList = (outs MSA128BOpnd:$wd);
1708 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1710 string AsmString = "bmzi.b\t$wd, $ws, $u8";
1711 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1714 InstrItinClass Itinerary = NoItinerary;
1715 string Constraints = "$wd = $wd_in";
1718 class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>;
1719 class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>;
1720 class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>;
1721 class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>;
1723 class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2, MSA128BOpnd>;
1724 class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2, MSA128HOpnd>;
1725 class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2, MSA128WOpnd>;
1726 class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2, MSA128DOpnd>;
1728 class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>;
1729 class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>;
1730 class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>;
1731 class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>;
1733 class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>;
1736 dag OutOperandList = (outs MSA128BOpnd:$wd);
1737 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1739 string AsmString = "bsel.v\t$wd, $ws, $wt";
1740 list<dag> Pattern = [(set MSA128BOpnd:$wd,
1741 (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1743 InstrItinClass Itinerary = NoItinerary;
1744 string Constraints = "$wd = $wd_in";
1747 class BSELI_B_DESC {
1748 dag OutOperandList = (outs MSA128BOpnd:$wd);
1749 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1751 string AsmString = "bseli.b\t$wd, $ws, $u8";
1752 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in,
1754 vsplati8_uimm8:$u8))];
1755 InstrItinClass Itinerary = NoItinerary;
1756 string Constraints = "$wd = $wd_in";
1759 class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>;
1760 class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>;
1761 class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>;
1762 class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>;
1764 class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2,
1766 class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2,
1768 class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2,
1770 class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2,
1773 class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>;
1774 class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>;
1775 class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>;
1776 class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>;
1778 class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>;
1780 class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>,
1782 class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>,
1784 class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>,
1786 class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>,
1789 class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5,
1791 class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5,
1793 class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5,
1795 class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5,
1799 dag OutOperandList = (outs GPR32Opnd:$rd);
1800 dag InOperandList = (ins MSA128CROpnd:$cs);
1801 string AsmString = "cfcmsa\t$rd, $cs";
1802 InstrItinClass Itinerary = NoItinerary;
1803 bit hasSideEffects = 1;
1806 class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>;
1807 class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>;
1808 class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>;
1809 class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>;
1811 class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>;
1812 class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>;
1813 class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>;
1814 class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>;
1816 class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8,
1817 vsplati8_simm5, MSA128BOpnd>;
1818 class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16,
1819 vsplati16_simm5, MSA128HOpnd>;
1820 class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32,
1821 vsplati32_simm5, MSA128WOpnd>;
1822 class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64,
1823 vsplati64_simm5, MSA128DOpnd>;
1825 class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8,
1826 vsplati8_uimm5, MSA128BOpnd>;
1827 class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16,
1828 vsplati16_uimm5, MSA128HOpnd>;
1829 class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32,
1830 vsplati32_uimm5, MSA128WOpnd>;
1831 class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64,
1832 vsplati64_uimm5, MSA128DOpnd>;
1834 class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>;
1835 class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>;
1836 class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>;
1837 class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>;
1839 class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>;
1840 class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>;
1841 class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>;
1842 class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>;
1844 class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8,
1845 vsplati8_simm5, MSA128BOpnd>;
1846 class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16,
1847 vsplati16_simm5, MSA128HOpnd>;
1848 class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32,
1849 vsplati32_simm5, MSA128WOpnd>;
1850 class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64,
1851 vsplati64_simm5, MSA128DOpnd>;
1853 class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8,
1854 vsplati8_uimm5, MSA128BOpnd>;
1855 class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16,
1856 vsplati16_uimm5, MSA128HOpnd>;
1857 class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32,
1858 vsplati32_uimm5, MSA128WOpnd>;
1859 class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64,
1860 vsplati64_uimm5, MSA128DOpnd>;
1862 class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8,
1863 GPR32Opnd, MSA128BOpnd>;
1864 class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16,
1865 GPR32Opnd, MSA128HOpnd>;
1866 class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32,
1867 GPR32Opnd, MSA128WOpnd>;
1869 class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8,
1870 GPR32Opnd, MSA128BOpnd>;
1871 class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16,
1872 GPR32Opnd, MSA128HOpnd>;
1873 class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32,
1874 GPR32Opnd, MSA128WOpnd>;
1876 class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, FGR32,
1878 class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, FGR64,
1882 dag OutOperandList = (outs);
1883 dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs);
1884 string AsmString = "ctcmsa\t$cd, $rs";
1885 InstrItinClass Itinerary = NoItinerary;
1886 bit hasSideEffects = 1;
1889 class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>;
1890 class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>;
1891 class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>;
1892 class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>;
1894 class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>;
1895 class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>;
1896 class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>;
1897 class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>;
1899 class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h,
1900 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1902 class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w,
1903 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1905 class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d,
1906 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1909 class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h,
1910 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1912 class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w,
1913 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1915 class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d,
1916 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1919 class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h,
1920 MSA128HOpnd, MSA128BOpnd,
1921 MSA128BOpnd>, IsCommutable;
1922 class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w,
1923 MSA128WOpnd, MSA128HOpnd,
1924 MSA128HOpnd>, IsCommutable;
1925 class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d,
1926 MSA128DOpnd, MSA128WOpnd,
1927 MSA128WOpnd>, IsCommutable;
1929 class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h,
1930 MSA128HOpnd, MSA128BOpnd,
1931 MSA128BOpnd>, IsCommutable;
1932 class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w,
1933 MSA128WOpnd, MSA128HOpnd,
1934 MSA128HOpnd>, IsCommutable;
1935 class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d,
1936 MSA128DOpnd, MSA128WOpnd,
1937 MSA128WOpnd>, IsCommutable;
1939 class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h,
1940 MSA128HOpnd, MSA128BOpnd,
1942 class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w,
1943 MSA128WOpnd, MSA128HOpnd,
1945 class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d,
1946 MSA128DOpnd, MSA128WOpnd,
1949 class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h,
1950 MSA128HOpnd, MSA128BOpnd,
1952 class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w,
1953 MSA128WOpnd, MSA128HOpnd,
1955 class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d,
1956 MSA128DOpnd, MSA128WOpnd,
1959 class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>,
1961 class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>,
1964 class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>,
1966 class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>,
1969 class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>,
1971 class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>,
1974 class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w,
1976 class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d,
1979 class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>;
1980 class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>;
1982 class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>;
1983 class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>;
1985 class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>,
1987 class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>,
1990 class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>,
1992 class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>,
1995 class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>,
1997 class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>,
2000 class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>,
2002 class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>,
2005 class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>,
2007 class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>,
2010 class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>,
2012 class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>,
2015 class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>,
2017 class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>,
2020 class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>;
2021 class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>;
2023 class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h,
2024 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2025 class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w,
2026 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2028 // The fexp2.df instruction multiplies the first operand by 2 to the power of
2029 // the second operand. We therefore need a pseudo-insn in order to invent the
2030 // 1.0 when we only need to match ISD::FEXP2.
2031 class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>;
2032 class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>;
2033 let usesCustomInserter = 1 in {
2034 class FEXP2_W_1_PSEUDO_DESC :
2035 MipsPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws),
2036 [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>;
2037 class FEXP2_D_1_PSEUDO_DESC :
2038 MipsPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws),
2039 [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>;
2042 class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w,
2043 MSA128WOpnd, MSA128HOpnd>;
2044 class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d,
2045 MSA128DOpnd, MSA128WOpnd>;
2047 class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w,
2048 MSA128WOpnd, MSA128HOpnd>;
2049 class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d,
2050 MSA128DOpnd, MSA128WOpnd>;
2052 class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>;
2053 class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>;
2055 class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>;
2056 class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>;
2058 class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w,
2059 MSA128WOpnd, MSA128HOpnd>;
2060 class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d,
2061 MSA128DOpnd, MSA128WOpnd>;
2063 class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w,
2064 MSA128WOpnd, MSA128HOpnd>;
2065 class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d,
2066 MSA128DOpnd, MSA128WOpnd>;
2068 class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8,
2069 MSA128BOpnd, GPR32Opnd>;
2070 class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16,
2071 MSA128HOpnd, GPR32Opnd>;
2072 class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32,
2073 MSA128WOpnd, GPR32Opnd>;
2075 class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W,
2077 class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D,
2080 class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>;
2081 class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>;
2083 class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>;
2084 class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>;
2086 class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>;
2087 class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>;
2089 class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w,
2091 class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d,
2094 class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>;
2095 class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>;
2097 class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w,
2099 class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d,
2102 class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", fms, MSA128WOpnd>;
2103 class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", fms, MSA128DOpnd>;
2105 class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>;
2106 class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>;
2108 class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>;
2109 class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>;
2111 class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>;
2112 class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>;
2114 class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w,
2116 class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d,
2119 class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>;
2120 class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>;
2122 class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>;
2123 class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>;
2125 class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>;
2126 class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>;
2128 class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>;
2129 class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>;
2131 class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>;
2132 class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>;
2134 class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>;
2135 class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>;
2137 class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>;
2138 class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>;
2140 class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>;
2141 class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>;
2143 class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w,
2145 class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d,
2148 class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w,
2150 class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d,
2153 class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w,
2155 class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d,
2158 class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w,
2160 class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d,
2163 class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w,
2165 class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d,
2168 class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w,
2170 class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d,
2173 class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w,
2175 class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d,
2178 class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h,
2179 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2180 class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w,
2181 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2183 class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint,
2185 class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint,
2188 class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint,
2190 class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint,
2193 class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h,
2194 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2195 class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w,
2196 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2197 class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d,
2198 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2200 class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h,
2201 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2202 class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w,
2203 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2204 class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d,
2205 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2207 class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h,
2208 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2209 class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w,
2210 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2211 class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d,
2212 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2214 class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h,
2215 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2216 class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w,
2217 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2218 class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d,
2219 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2221 class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>;
2222 class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>;
2223 class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>;
2224 class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>;
2226 class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>;
2227 class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>;
2228 class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>;
2229 class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>;
2231 class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>;
2232 class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>;
2233 class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>;
2234 class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>;
2236 class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>;
2237 class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>;
2238 class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>;
2239 class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>;
2241 class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8,
2242 MSA128BOpnd, GPR32Opnd>;
2243 class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16,
2244 MSA128HOpnd, GPR32Opnd>;
2245 class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32,
2246 MSA128WOpnd, GPR32Opnd>;
2248 class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32,
2249 MSA128WOpnd, FGR32Opnd>;
2250 class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64,
2251 MSA128DOpnd, FGR64Opnd>;
2253 class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", int_mips_insve_b,
2255 class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", int_mips_insve_h,
2257 class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", int_mips_insve_w,
2259 class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", int_mips_insve_d,
2262 class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2263 ValueType TyNode, RegisterOperand ROWD,
2264 Operand MemOpnd = mem, ComplexPattern Addr = addrRegImm,
2265 InstrItinClass itin = NoItinerary> {
2266 dag OutOperandList = (outs ROWD:$wd);
2267 dag InOperandList = (ins MemOpnd:$addr);
2268 string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2269 list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))];
2270 InstrItinClass Itinerary = itin;
2271 string DecoderMethod = "DecodeMSA128Mem";
2274 class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd>;
2275 class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd>;
2276 class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd>;
2277 class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd>;
2279 class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>;
2280 class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>;
2281 class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>;
2282 class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>;
2285 dag OutOperandList = (outs GPR32Opnd:$rd);
2286 dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, uimm2:$sa);
2287 string AsmString = "lsa\t$rd, $rs, $rt, $sa";
2288 list<dag> Pattern = [(set GPR32Opnd:$rd, (add GPR32Opnd:$rs,
2290 immZExt2Lsa:$sa)))];
2291 InstrItinClass Itinerary = NoItinerary;
2294 class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h,
2296 class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w,
2299 class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h,
2301 class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w,
2304 class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>;
2305 class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>;
2306 class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>;
2307 class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>;
2309 class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>;
2310 class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>;
2311 class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>;
2312 class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>;
2314 class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", MipsVSMax, MSA128BOpnd>;
2315 class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", MipsVSMax, MSA128HOpnd>;
2316 class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", MipsVSMax, MSA128WOpnd>;
2317 class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", MipsVSMax, MSA128DOpnd>;
2319 class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", MipsVUMax, MSA128BOpnd>;
2320 class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", MipsVUMax, MSA128HOpnd>;
2321 class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", MipsVUMax, MSA128WOpnd>;
2322 class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", MipsVUMax, MSA128DOpnd>;
2324 class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", MipsVSMax, vsplati8_simm5,
2326 class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", MipsVSMax, vsplati16_simm5,
2328 class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", MipsVSMax, vsplati32_simm5,
2330 class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", MipsVSMax, vsplati64_simm5,
2333 class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", MipsVUMax, vsplati8_uimm5,
2335 class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", MipsVUMax, vsplati16_uimm5,
2337 class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", MipsVUMax, vsplati32_uimm5,
2339 class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", MipsVUMax, vsplati64_uimm5,
2342 class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>;
2343 class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>;
2344 class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>;
2345 class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>;
2347 class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", MipsVSMin, MSA128BOpnd>;
2348 class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", MipsVSMin, MSA128HOpnd>;
2349 class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", MipsVSMin, MSA128WOpnd>;
2350 class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", MipsVSMin, MSA128DOpnd>;
2352 class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", MipsVUMin, MSA128BOpnd>;
2353 class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", MipsVUMin, MSA128HOpnd>;
2354 class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", MipsVUMin, MSA128WOpnd>;
2355 class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", MipsVUMin, MSA128DOpnd>;
2357 class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", MipsVSMin, vsplati8_simm5,
2359 class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", MipsVSMin, vsplati16_simm5,
2361 class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", MipsVSMin, vsplati32_simm5,
2363 class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", MipsVSMin, vsplati64_simm5,
2366 class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", MipsVUMin, vsplati8_uimm5,
2368 class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", MipsVUMin, vsplati16_uimm5,
2370 class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", MipsVUMin, vsplati32_uimm5,
2372 class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", MipsVUMin, vsplati64_uimm5,
2375 class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>;
2376 class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>;
2377 class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>;
2378 class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>;
2380 class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>;
2381 class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>;
2382 class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>;
2383 class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>;
2386 dag OutOperandList = (outs MSA128BOpnd:$wd);
2387 dag InOperandList = (ins MSA128BOpnd:$ws);
2388 string AsmString = "move.v\t$wd, $ws";
2389 list<dag> Pattern = [];
2390 InstrItinClass Itinerary = NoItinerary;
2393 class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h,
2395 class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w,
2398 class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h,
2400 class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w,
2403 class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>;
2404 class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>;
2405 class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>;
2406 class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>;
2408 class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h,
2410 class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w,
2413 class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h,
2415 class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w,
2418 class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>;
2419 class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>;
2420 class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>;
2421 class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>;
2423 class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>;
2424 class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>;
2425 class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>;
2426 class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>;
2428 class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>;
2429 class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>;
2430 class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>;
2431 class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>;
2433 class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>;
2434 class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>;
2435 class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>;
2436 class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>;
2438 class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8,
2441 class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>;
2442 class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>;
2443 class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>;
2444 class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>;
2446 class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>;
2448 class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>;
2449 class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>;
2450 class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>;
2451 class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>;
2453 class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>;
2454 class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>;
2455 class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>;
2456 class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>;
2458 class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>;
2459 class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>;
2460 class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>;
2461 class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>;
2463 class SAT_S_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b,
2465 class SAT_S_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h,
2467 class SAT_S_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w,
2469 class SAT_S_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d,
2472 class SAT_U_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b,
2474 class SAT_U_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h,
2476 class SAT_U_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w,
2478 class SAT_U_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d,
2481 class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>;
2482 class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>;
2483 class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>;
2485 class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>;
2486 class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>;
2487 class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>;
2488 class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>;
2490 class SLDI_B_DESC : MSA_ELM_DESC_BASE<"sldi.b", int_mips_sldi_b, MSA128BOpnd>;
2491 class SLDI_H_DESC : MSA_ELM_DESC_BASE<"sldi.h", int_mips_sldi_h, MSA128HOpnd>;
2492 class SLDI_W_DESC : MSA_ELM_DESC_BASE<"sldi.w", int_mips_sldi_w, MSA128WOpnd>;
2493 class SLDI_D_DESC : MSA_ELM_DESC_BASE<"sldi.d", int_mips_sldi_d, MSA128DOpnd>;
2495 class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>;
2496 class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>;
2497 class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>;
2498 class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>;
2500 class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3,
2502 class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4,
2504 class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5,
2506 class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6,
2509 class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt,
2511 class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt,
2513 class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt,
2515 class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt,
2518 class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4,
2520 class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3,
2522 class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2,
2524 class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1,
2527 class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>;
2528 class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>;
2529 class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>;
2530 class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>;
2532 class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3,
2534 class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4,
2536 class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5,
2538 class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6,
2541 class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>;
2542 class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>;
2543 class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>;
2544 class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>;
2546 class SRARI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srari.b", int_mips_srari_b,
2548 class SRARI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srari.h", int_mips_srari_h,
2550 class SRARI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srari.w", int_mips_srari_w,
2552 class SRARI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srari.d", int_mips_srari_d,
2555 class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>;
2556 class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>;
2557 class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>;
2558 class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>;
2560 class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3,
2562 class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4,
2564 class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5,
2566 class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6,
2569 class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>;
2570 class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>;
2571 class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>;
2572 class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>;
2574 class SRLRI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srlri.b", int_mips_srlri_b,
2576 class SRLRI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srlri.h", int_mips_srlri_h,
2578 class SRLRI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srlri.w", int_mips_srlri_w,
2580 class SRLRI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srlri.d", int_mips_srlri_d,
2583 class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2584 ValueType TyNode, RegisterOperand ROWD,
2585 Operand MemOpnd = mem, ComplexPattern Addr = addrRegImm,
2586 InstrItinClass itin = NoItinerary> {
2587 dag OutOperandList = (outs);
2588 dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr);
2589 string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2590 list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)];
2591 InstrItinClass Itinerary = itin;
2592 string DecoderMethod = "DecodeMSA128Mem";
2595 class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd>;
2596 class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd>;
2597 class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd>;
2598 class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd>;
2600 class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b,
2602 class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h,
2604 class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w,
2606 class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d,
2609 class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b,
2611 class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h,
2613 class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w,
2615 class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d,
2618 class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b,
2620 class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h,
2622 class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w,
2624 class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d,
2627 class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b,
2629 class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h,
2631 class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w,
2633 class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d,
2636 class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>;
2637 class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>;
2638 class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>;
2639 class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>;
2641 class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5,
2643 class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5,
2645 class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5,
2647 class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5,
2650 class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>;
2651 class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>;
2652 class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>;
2653 class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>;
2655 class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>;
2656 class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>;
2657 class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>;
2658 class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>;
2660 class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8,
2663 // Instruction defs.
2664 def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC;
2665 def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC;
2666 def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC;
2667 def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC;
2669 def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC;
2670 def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC;
2671 def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC;
2672 def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC;
2674 def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC;
2675 def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC;
2676 def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC;
2677 def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC;
2679 def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC;
2680 def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC;
2681 def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC;
2682 def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC;
2684 def ADDV_B : ADDV_B_ENC, ADDV_B_DESC;
2685 def ADDV_H : ADDV_H_ENC, ADDV_H_DESC;
2686 def ADDV_W : ADDV_W_ENC, ADDV_W_DESC;
2687 def ADDV_D : ADDV_D_ENC, ADDV_D_DESC;
2689 def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC;
2690 def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC;
2691 def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC;
2692 def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC;
2694 def AND_V : AND_V_ENC, AND_V_DESC;
2695 def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC,
2696 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2699 def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC,
2700 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2703 def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC,
2704 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2708 def ANDI_B : ANDI_B_ENC, ANDI_B_DESC;
2710 def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC;
2711 def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC;
2712 def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC;
2713 def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC;
2715 def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC;
2716 def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC;
2717 def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC;
2718 def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC;
2720 def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC;
2721 def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC;
2722 def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC;
2723 def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC;
2725 def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC;
2726 def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC;
2727 def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC;
2728 def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC;
2730 def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC;
2731 def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC;
2732 def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC;
2733 def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC;
2735 def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC;
2736 def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC;
2737 def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC;
2738 def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC;
2740 def BCLR_B : BCLR_B_ENC, BCLR_B_DESC;
2741 def BCLR_H : BCLR_H_ENC, BCLR_H_DESC;
2742 def BCLR_W : BCLR_W_ENC, BCLR_W_DESC;
2743 def BCLR_D : BCLR_D_ENC, BCLR_D_DESC;
2745 def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC;
2746 def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC;
2747 def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC;
2748 def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC;
2750 def BINSL_B : BINSL_B_ENC, BINSL_B_DESC;
2751 def BINSL_H : BINSL_H_ENC, BINSL_H_DESC;
2752 def BINSL_W : BINSL_W_ENC, BINSL_W_DESC;
2753 def BINSL_D : BINSL_D_ENC, BINSL_D_DESC;
2755 def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC;
2756 def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC;
2757 def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC;
2758 def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC;
2760 def BINSR_B : BINSR_B_ENC, BINSR_B_DESC;
2761 def BINSR_H : BINSR_H_ENC, BINSR_H_DESC;
2762 def BINSR_W : BINSR_W_ENC, BINSR_W_DESC;
2763 def BINSR_D : BINSR_D_ENC, BINSR_D_DESC;
2765 def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC;
2766 def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC;
2767 def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC;
2768 def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC;
2770 def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC;
2772 def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC;
2774 def BMZ_V : BMZ_V_ENC, BMZ_V_DESC;
2776 def BMZI_B : BMZI_B_ENC, BMZI_B_DESC;
2778 def BNEG_B : BNEG_B_ENC, BNEG_B_DESC;
2779 def BNEG_H : BNEG_H_ENC, BNEG_H_DESC;
2780 def BNEG_W : BNEG_W_ENC, BNEG_W_DESC;
2781 def BNEG_D : BNEG_D_ENC, BNEG_D_DESC;
2783 def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC;
2784 def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC;
2785 def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC;
2786 def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC;
2788 def BNZ_B : BNZ_B_ENC, BNZ_B_DESC;
2789 def BNZ_H : BNZ_H_ENC, BNZ_H_DESC;
2790 def BNZ_W : BNZ_W_ENC, BNZ_W_DESC;
2791 def BNZ_D : BNZ_D_ENC, BNZ_D_DESC;
2793 def BNZ_V : BNZ_V_ENC, BNZ_V_DESC;
2795 def BSEL_V : BSEL_V_ENC, BSEL_V_DESC;
2797 class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> :
2798 MipsPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt),
2799 [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$ws, RO:$wt)))]>,
2800 PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in,
2801 MSA128BOpnd:$ws, MSA128BOpnd:$wt)> {
2802 let Constraints = "$wd_in = $wd";
2805 def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>;
2806 def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>;
2807 def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>;
2808 def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>;
2809 def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>;
2811 def BSELI_B : BSELI_B_ENC, BSELI_B_DESC;
2813 def BSET_B : BSET_B_ENC, BSET_B_DESC;
2814 def BSET_H : BSET_H_ENC, BSET_H_DESC;
2815 def BSET_W : BSET_W_ENC, BSET_W_DESC;
2816 def BSET_D : BSET_D_ENC, BSET_D_DESC;
2818 def BSETI_B : BSETI_B_ENC, BSETI_B_DESC;
2819 def BSETI_H : BSETI_H_ENC, BSETI_H_DESC;
2820 def BSETI_W : BSETI_W_ENC, BSETI_W_DESC;
2821 def BSETI_D : BSETI_D_ENC, BSETI_D_DESC;
2823 def BZ_B : BZ_B_ENC, BZ_B_DESC;
2824 def BZ_H : BZ_H_ENC, BZ_H_DESC;
2825 def BZ_W : BZ_W_ENC, BZ_W_DESC;
2826 def BZ_D : BZ_D_ENC, BZ_D_DESC;
2828 def BZ_V : BZ_V_ENC, BZ_V_DESC;
2830 def CEQ_B : CEQ_B_ENC, CEQ_B_DESC;
2831 def CEQ_H : CEQ_H_ENC, CEQ_H_DESC;
2832 def CEQ_W : CEQ_W_ENC, CEQ_W_DESC;
2833 def CEQ_D : CEQ_D_ENC, CEQ_D_DESC;
2835 def CEQI_B : CEQI_B_ENC, CEQI_B_DESC;
2836 def CEQI_H : CEQI_H_ENC, CEQI_H_DESC;
2837 def CEQI_W : CEQI_W_ENC, CEQI_W_DESC;
2838 def CEQI_D : CEQI_D_ENC, CEQI_D_DESC;
2840 def CFCMSA : CFCMSA_ENC, CFCMSA_DESC;
2842 def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC;
2843 def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC;
2844 def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC;
2845 def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC;
2847 def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC;
2848 def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC;
2849 def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC;
2850 def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC;
2852 def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC;
2853 def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC;
2854 def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC;
2855 def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC;
2857 def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC;
2858 def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC;
2859 def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC;
2860 def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC;
2862 def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC;
2863 def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC;
2864 def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC;
2865 def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC;
2867 def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC;
2868 def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC;
2869 def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC;
2870 def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC;
2872 def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC;
2873 def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC;
2874 def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC;
2875 def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC;
2877 def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC;
2878 def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC;
2879 def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC;
2880 def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC;
2882 def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC;
2883 def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC;
2884 def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC;
2886 def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC;
2887 def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC;
2888 def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC;
2890 def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC;
2891 def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC;
2893 def CTCMSA : CTCMSA_ENC, CTCMSA_DESC;
2895 def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC;
2896 def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC;
2897 def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC;
2898 def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC;
2900 def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC;
2901 def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC;
2902 def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC;
2903 def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC;
2905 def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC;
2906 def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC;
2907 def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC;
2909 def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC;
2910 def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC;
2911 def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC;
2913 def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC;
2914 def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC;
2915 def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC;
2917 def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC;
2918 def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC;
2919 def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC;
2921 def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC;
2922 def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC;
2923 def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC;
2925 def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC;
2926 def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC;
2927 def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC;
2929 def FADD_W : FADD_W_ENC, FADD_W_DESC;
2930 def FADD_D : FADD_D_ENC, FADD_D_DESC;
2932 def FCAF_W : FCAF_W_ENC, FCAF_W_DESC;
2933 def FCAF_D : FCAF_D_ENC, FCAF_D_DESC;
2935 def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC;
2936 def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC;
2938 def FCLE_W : FCLE_W_ENC, FCLE_W_DESC;
2939 def FCLE_D : FCLE_D_ENC, FCLE_D_DESC;
2941 def FCLT_W : FCLT_W_ENC, FCLT_W_DESC;
2942 def FCLT_D : FCLT_D_ENC, FCLT_D_DESC;
2944 def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC;
2945 def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC;
2947 def FCNE_W : FCNE_W_ENC, FCNE_W_DESC;
2948 def FCNE_D : FCNE_D_ENC, FCNE_D_DESC;
2950 def FCOR_W : FCOR_W_ENC, FCOR_W_DESC;
2951 def FCOR_D : FCOR_D_ENC, FCOR_D_DESC;
2953 def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC;
2954 def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC;
2956 def FCULE_W : FCULE_W_ENC, FCULE_W_DESC;
2957 def FCULE_D : FCULE_D_ENC, FCULE_D_DESC;
2959 def FCULT_W : FCULT_W_ENC, FCULT_W_DESC;
2960 def FCULT_D : FCULT_D_ENC, FCULT_D_DESC;
2962 def FCUN_W : FCUN_W_ENC, FCUN_W_DESC;
2963 def FCUN_D : FCUN_D_ENC, FCUN_D_DESC;
2965 def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC;
2966 def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC;
2968 def FDIV_W : FDIV_W_ENC, FDIV_W_DESC;
2969 def FDIV_D : FDIV_D_ENC, FDIV_D_DESC;
2971 def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC;
2972 def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC;
2974 def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC;
2975 def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC;
2976 def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC;
2977 def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC;
2979 def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC;
2980 def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC;
2982 def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC;
2983 def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC;
2985 def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC;
2986 def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC;
2988 def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC;
2989 def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC;
2991 def FFQL_W : FFQL_W_ENC, FFQL_W_DESC;
2992 def FFQL_D : FFQL_D_ENC, FFQL_D_DESC;
2994 def FFQR_W : FFQR_W_ENC, FFQR_W_DESC;
2995 def FFQR_D : FFQR_D_ENC, FFQR_D_DESC;
2997 def FILL_B : FILL_B_ENC, FILL_B_DESC;
2998 def FILL_H : FILL_H_ENC, FILL_H_DESC;
2999 def FILL_W : FILL_W_ENC, FILL_W_DESC;
3000 def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC;
3001 def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC;
3003 def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC;
3004 def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC;
3006 def FMADD_W : FMADD_W_ENC, FMADD_W_DESC;
3007 def FMADD_D : FMADD_D_ENC, FMADD_D_DESC;
3009 def FMAX_W : FMAX_W_ENC, FMAX_W_DESC;
3010 def FMAX_D : FMAX_D_ENC, FMAX_D_DESC;
3012 def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC;
3013 def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC;
3015 def FMIN_W : FMIN_W_ENC, FMIN_W_DESC;
3016 def FMIN_D : FMIN_D_ENC, FMIN_D_DESC;
3018 def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC;
3019 def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC;
3021 def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC;
3022 def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC;
3024 def FMUL_W : FMUL_W_ENC, FMUL_W_DESC;
3025 def FMUL_D : FMUL_D_ENC, FMUL_D_DESC;
3027 def FRINT_W : FRINT_W_ENC, FRINT_W_DESC;
3028 def FRINT_D : FRINT_D_ENC, FRINT_D_DESC;
3030 def FRCP_W : FRCP_W_ENC, FRCP_W_DESC;
3031 def FRCP_D : FRCP_D_ENC, FRCP_D_DESC;
3033 def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC;
3034 def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC;
3036 def FSAF_W : FSAF_W_ENC, FSAF_W_DESC;
3037 def FSAF_D : FSAF_D_ENC, FSAF_D_DESC;
3039 def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC;
3040 def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC;
3042 def FSLE_W : FSLE_W_ENC, FSLE_W_DESC;
3043 def FSLE_D : FSLE_D_ENC, FSLE_D_DESC;
3045 def FSLT_W : FSLT_W_ENC, FSLT_W_DESC;
3046 def FSLT_D : FSLT_D_ENC, FSLT_D_DESC;
3048 def FSNE_W : FSNE_W_ENC, FSNE_W_DESC;
3049 def FSNE_D : FSNE_D_ENC, FSNE_D_DESC;
3051 def FSOR_W : FSOR_W_ENC, FSOR_W_DESC;
3052 def FSOR_D : FSOR_D_ENC, FSOR_D_DESC;
3054 def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC;
3055 def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC;
3057 def FSUB_W : FSUB_W_ENC, FSUB_W_DESC;
3058 def FSUB_D : FSUB_D_ENC, FSUB_D_DESC;
3060 def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC;
3061 def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC;
3063 def FSULE_W : FSULE_W_ENC, FSULE_W_DESC;
3064 def FSULE_D : FSULE_D_ENC, FSULE_D_DESC;
3066 def FSULT_W : FSULT_W_ENC, FSULT_W_DESC;
3067 def FSULT_D : FSULT_D_ENC, FSULT_D_DESC;
3069 def FSUN_W : FSUN_W_ENC, FSUN_W_DESC;
3070 def FSUN_D : FSUN_D_ENC, FSUN_D_DESC;
3072 def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC;
3073 def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC;
3075 def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC;
3076 def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC;
3078 def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC;
3079 def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC;
3081 def FTQ_H : FTQ_H_ENC, FTQ_H_DESC;
3082 def FTQ_W : FTQ_W_ENC, FTQ_W_DESC;
3084 def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC;
3085 def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC;
3087 def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC;
3088 def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC;
3090 def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC;
3091 def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC;
3092 def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC;
3094 def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC;
3095 def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC;
3096 def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC;
3098 def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC;
3099 def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC;
3100 def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC;
3102 def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC;
3103 def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC;
3104 def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC;
3106 def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC;
3107 def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC;
3108 def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC;
3109 def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC;
3111 def ILVL_B : ILVL_B_ENC, ILVL_B_DESC;
3112 def ILVL_H : ILVL_H_ENC, ILVL_H_DESC;
3113 def ILVL_W : ILVL_W_ENC, ILVL_W_DESC;
3114 def ILVL_D : ILVL_D_ENC, ILVL_D_DESC;
3116 def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC;
3117 def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC;
3118 def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC;
3119 def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC;
3121 def ILVR_B : ILVR_B_ENC, ILVR_B_DESC;
3122 def ILVR_H : ILVR_H_ENC, ILVR_H_DESC;
3123 def ILVR_W : ILVR_W_ENC, ILVR_W_DESC;
3124 def ILVR_D : ILVR_D_ENC, ILVR_D_DESC;
3126 def INSERT_B : INSERT_B_ENC, INSERT_B_DESC;
3127 def INSERT_H : INSERT_H_ENC, INSERT_H_DESC;
3128 def INSERT_W : INSERT_W_ENC, INSERT_W_DESC;
3130 // INSERT_FW_PSEUDO defined after INSVE_W
3131 // INSERT_FD_PSEUDO defined after INSVE_D
3133 def INSVE_B : INSVE_B_ENC, INSVE_B_DESC;
3134 def INSVE_H : INSVE_H_ENC, INSVE_H_DESC;
3135 def INSVE_W : INSVE_W_ENC, INSVE_W_DESC;
3136 def INSVE_D : INSVE_D_ENC, INSVE_D_DESC;
3138 def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC;
3139 def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC;
3141 def LD_B: LD_B_ENC, LD_B_DESC;
3142 def LD_H: LD_H_ENC, LD_H_DESC;
3143 def LD_W: LD_W_ENC, LD_W_DESC;
3144 def LD_D: LD_D_ENC, LD_D_DESC;
3146 def LDI_B : LDI_B_ENC, LDI_B_DESC;
3147 def LDI_H : LDI_H_ENC, LDI_H_DESC;
3148 def LDI_W : LDI_W_ENC, LDI_W_DESC;
3149 def LDI_D : LDI_D_ENC, LDI_D_DESC;
3151 def LSA : LSA_ENC, LSA_DESC;
3153 def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC;
3154 def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC;
3156 def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC;
3157 def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC;
3159 def MADDV_B : MADDV_B_ENC, MADDV_B_DESC;
3160 def MADDV_H : MADDV_H_ENC, MADDV_H_DESC;
3161 def MADDV_W : MADDV_W_ENC, MADDV_W_DESC;
3162 def MADDV_D : MADDV_D_ENC, MADDV_D_DESC;
3164 def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC;
3165 def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC;
3166 def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC;
3167 def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC;
3169 def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC;
3170 def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC;
3171 def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC;
3172 def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC;
3174 def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC;
3175 def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC;
3176 def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC;
3177 def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC;
3179 def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC;
3180 def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC;
3181 def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC;
3182 def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC;
3184 def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC;
3185 def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC;
3186 def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC;
3187 def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC;
3189 def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC;
3190 def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC;
3191 def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC;
3192 def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC;
3194 def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC;
3195 def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC;
3196 def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC;
3197 def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC;
3199 def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC;
3200 def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC;
3201 def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC;
3202 def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC;
3204 def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC;
3205 def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC;
3206 def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC;
3207 def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC;
3209 def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC;
3210 def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC;
3211 def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC;
3212 def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC;
3214 def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC;
3215 def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC;
3216 def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC;
3217 def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC;
3219 def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC;
3220 def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC;
3221 def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC;
3222 def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC;
3224 def MOVE_V : MOVE_V_ENC, MOVE_V_DESC;
3226 def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC;
3227 def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC;
3229 def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC;
3230 def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC;
3232 def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC;
3233 def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC;
3234 def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC;
3235 def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC;
3237 def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC;
3238 def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC;
3240 def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC;
3241 def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC;
3243 def MULV_B : MULV_B_ENC, MULV_B_DESC;
3244 def MULV_H : MULV_H_ENC, MULV_H_DESC;
3245 def MULV_W : MULV_W_ENC, MULV_W_DESC;
3246 def MULV_D : MULV_D_ENC, MULV_D_DESC;
3248 def NLOC_B : NLOC_B_ENC, NLOC_B_DESC;
3249 def NLOC_H : NLOC_H_ENC, NLOC_H_DESC;
3250 def NLOC_W : NLOC_W_ENC, NLOC_W_DESC;
3251 def NLOC_D : NLOC_D_ENC, NLOC_D_DESC;
3253 def NLZC_B : NLZC_B_ENC, NLZC_B_DESC;
3254 def NLZC_H : NLZC_H_ENC, NLZC_H_DESC;
3255 def NLZC_W : NLZC_W_ENC, NLZC_W_DESC;
3256 def NLZC_D : NLZC_D_ENC, NLZC_D_DESC;
3258 def NOR_V : NOR_V_ENC, NOR_V_DESC;
3259 def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC,
3260 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3263 def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC,
3264 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3267 def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC,
3268 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3272 def NORI_B : NORI_B_ENC, NORI_B_DESC;
3274 def OR_V : OR_V_ENC, OR_V_DESC;
3275 def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC,
3276 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3279 def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC,
3280 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3283 def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC,
3284 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3288 def ORI_B : ORI_B_ENC, ORI_B_DESC;
3290 def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC;
3291 def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC;
3292 def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC;
3293 def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC;
3295 def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC;
3296 def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC;
3297 def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC;
3298 def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC;
3300 def PCNT_B : PCNT_B_ENC, PCNT_B_DESC;
3301 def PCNT_H : PCNT_H_ENC, PCNT_H_DESC;
3302 def PCNT_W : PCNT_W_ENC, PCNT_W_DESC;
3303 def PCNT_D : PCNT_D_ENC, PCNT_D_DESC;
3305 def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC;
3306 def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC;
3307 def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC;
3308 def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC;
3310 def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC;
3311 def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC;
3312 def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC;
3313 def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC;
3315 def SHF_B : SHF_B_ENC, SHF_B_DESC;
3316 def SHF_H : SHF_H_ENC, SHF_H_DESC;
3317 def SHF_W : SHF_W_ENC, SHF_W_DESC;
3319 def SLD_B : SLD_B_ENC, SLD_B_DESC;
3320 def SLD_H : SLD_H_ENC, SLD_H_DESC;
3321 def SLD_W : SLD_W_ENC, SLD_W_DESC;
3322 def SLD_D : SLD_D_ENC, SLD_D_DESC;
3324 def SLDI_B : SLDI_B_ENC, SLDI_B_DESC;
3325 def SLDI_H : SLDI_H_ENC, SLDI_H_DESC;
3326 def SLDI_W : SLDI_W_ENC, SLDI_W_DESC;
3327 def SLDI_D : SLDI_D_ENC, SLDI_D_DESC;
3329 def SLL_B : SLL_B_ENC, SLL_B_DESC;
3330 def SLL_H : SLL_H_ENC, SLL_H_DESC;
3331 def SLL_W : SLL_W_ENC, SLL_W_DESC;
3332 def SLL_D : SLL_D_ENC, SLL_D_DESC;
3334 def SLLI_B : SLLI_B_ENC, SLLI_B_DESC;
3335 def SLLI_H : SLLI_H_ENC, SLLI_H_DESC;
3336 def SLLI_W : SLLI_W_ENC, SLLI_W_DESC;
3337 def SLLI_D : SLLI_D_ENC, SLLI_D_DESC;
3339 def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC;
3340 def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC;
3341 def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC;
3342 def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC;
3344 def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC;
3345 def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC;
3346 def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC;
3347 def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC;
3349 def SRA_B : SRA_B_ENC, SRA_B_DESC;
3350 def SRA_H : SRA_H_ENC, SRA_H_DESC;
3351 def SRA_W : SRA_W_ENC, SRA_W_DESC;
3352 def SRA_D : SRA_D_ENC, SRA_D_DESC;
3354 def SRAI_B : SRAI_B_ENC, SRAI_B_DESC;
3355 def SRAI_H : SRAI_H_ENC, SRAI_H_DESC;
3356 def SRAI_W : SRAI_W_ENC, SRAI_W_DESC;
3357 def SRAI_D : SRAI_D_ENC, SRAI_D_DESC;
3359 def SRAR_B : SRAR_B_ENC, SRAR_B_DESC;
3360 def SRAR_H : SRAR_H_ENC, SRAR_H_DESC;
3361 def SRAR_W : SRAR_W_ENC, SRAR_W_DESC;
3362 def SRAR_D : SRAR_D_ENC, SRAR_D_DESC;
3364 def SRARI_B : SRARI_B_ENC, SRARI_B_DESC;
3365 def SRARI_H : SRARI_H_ENC, SRARI_H_DESC;
3366 def SRARI_W : SRARI_W_ENC, SRARI_W_DESC;
3367 def SRARI_D : SRARI_D_ENC, SRARI_D_DESC;
3369 def SRL_B : SRL_B_ENC, SRL_B_DESC;
3370 def SRL_H : SRL_H_ENC, SRL_H_DESC;
3371 def SRL_W : SRL_W_ENC, SRL_W_DESC;
3372 def SRL_D : SRL_D_ENC, SRL_D_DESC;
3374 def SRLI_B : SRLI_B_ENC, SRLI_B_DESC;
3375 def SRLI_H : SRLI_H_ENC, SRLI_H_DESC;
3376 def SRLI_W : SRLI_W_ENC, SRLI_W_DESC;
3377 def SRLI_D : SRLI_D_ENC, SRLI_D_DESC;
3379 def SRLR_B : SRLR_B_ENC, SRLR_B_DESC;
3380 def SRLR_H : SRLR_H_ENC, SRLR_H_DESC;
3381 def SRLR_W : SRLR_W_ENC, SRLR_W_DESC;
3382 def SRLR_D : SRLR_D_ENC, SRLR_D_DESC;
3384 def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC;
3385 def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC;
3386 def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC;
3387 def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC;
3389 def ST_B: ST_B_ENC, ST_B_DESC;
3390 def ST_H: ST_H_ENC, ST_H_DESC;
3391 def ST_W: ST_W_ENC, ST_W_DESC;
3392 def ST_D: ST_D_ENC, ST_D_DESC;
3394 def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC;
3395 def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC;
3396 def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC;
3397 def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC;
3399 def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC;
3400 def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC;
3401 def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC;
3402 def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC;
3404 def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC;
3405 def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC;
3406 def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC;
3407 def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC;
3409 def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC;
3410 def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC;
3411 def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC;
3412 def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC;
3414 def SUBV_B : SUBV_B_ENC, SUBV_B_DESC;
3415 def SUBV_H : SUBV_H_ENC, SUBV_H_DESC;
3416 def SUBV_W : SUBV_W_ENC, SUBV_W_DESC;
3417 def SUBV_D : SUBV_D_ENC, SUBV_D_DESC;
3419 def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC;
3420 def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC;
3421 def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC;
3422 def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC;
3424 def VSHF_B : VSHF_B_ENC, VSHF_B_DESC;
3425 def VSHF_H : VSHF_H_ENC, VSHF_H_DESC;
3426 def VSHF_W : VSHF_W_ENC, VSHF_W_DESC;
3427 def VSHF_D : VSHF_D_ENC, VSHF_D_DESC;
3429 def XOR_V : XOR_V_ENC, XOR_V_DESC;
3430 def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC,
3431 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3434 def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC,
3435 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3438 def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC,
3439 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3443 def XORI_B : XORI_B_ENC, XORI_B_DESC;
3446 class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> :
3447 Pat<pattern, result>, Requires<pred>;
3449 def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx),
3450 (COPY_S_W MSA128W:$ws, immZExt4:$idx)>;
3452 def : MSAPat<(v16i8 (load addr:$addr)), (LD_B addr:$addr)>;
3453 def : MSAPat<(v8i16 (load addr:$addr)), (LD_H addr:$addr)>;
3454 def : MSAPat<(v4i32 (load addr:$addr)), (LD_W addr:$addr)>;
3455 def : MSAPat<(v2i64 (load addr:$addr)), (LD_D addr:$addr)>;
3456 def : MSAPat<(v8f16 (load addr:$addr)), (LD_H addr:$addr)>;
3457 def : MSAPat<(v4f32 (load addr:$addr)), (LD_W addr:$addr)>;
3458 def : MSAPat<(v2f64 (load addr:$addr)), (LD_D addr:$addr)>;
3460 def : MSAPat<(v8f16 (load addrRegImm:$addr)), (LD_H addrRegImm:$addr)>;
3461 def : MSAPat<(v4f32 (load addrRegImm:$addr)), (LD_W addrRegImm:$addr)>;
3462 def : MSAPat<(v2f64 (load addrRegImm:$addr)), (LD_D addrRegImm:$addr)>;
3464 def : MSAPat<(store (v16i8 MSA128B:$ws), addr:$addr),
3465 (ST_B MSA128B:$ws, addr:$addr)>;
3466 def : MSAPat<(store (v8i16 MSA128H:$ws), addr:$addr),
3467 (ST_H MSA128H:$ws, addr:$addr)>;
3468 def : MSAPat<(store (v4i32 MSA128W:$ws), addr:$addr),
3469 (ST_W MSA128W:$ws, addr:$addr)>;
3470 def : MSAPat<(store (v2i64 MSA128D:$ws), addr:$addr),
3471 (ST_D MSA128D:$ws, addr:$addr)>;
3472 def : MSAPat<(store (v8f16 MSA128H:$ws), addr:$addr),
3473 (ST_H MSA128H:$ws, addr:$addr)>;
3474 def : MSAPat<(store (v4f32 MSA128W:$ws), addr:$addr),
3475 (ST_W MSA128W:$ws, addr:$addr)>;
3476 def : MSAPat<(store (v2f64 MSA128D:$ws), addr:$addr),
3477 (ST_D MSA128D:$ws, addr:$addr)>;
3479 def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrRegImm:$addr),
3480 (ST_H MSA128H:$ws, addrRegImm:$addr)>;
3481 def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrRegImm:$addr),
3482 (ST_W MSA128W:$ws, addrRegImm:$addr)>;
3483 def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrRegImm:$addr),
3484 (ST_D MSA128D:$ws, addrRegImm:$addr)>;
3486 class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD,
3487 RegisterOperand ROWS = ROWD,
3488 InstrItinClass itin = NoItinerary> :
3489 MipsPseudo<(outs ROWD:$wd),
3491 [(set ROWD:$wd, (fabs ROWS:$ws))]> {
3492 InstrItinClass Itinerary = itin;
3494 def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>,
3495 PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws,
3497 def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>,
3498 PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws,
3501 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3502 RegisterClass DstRC, list<Predicate> preds = [HasMSA]> :
3503 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3504 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3506 // These are endian-independant because the element size doesnt change
3507 def : MSABitconvertPat<v8i16, v8f16, MSA128H>;
3508 def : MSABitconvertPat<v4i32, v4f32, MSA128W>;
3509 def : MSABitconvertPat<v2i64, v2f64, MSA128D>;
3510 def : MSABitconvertPat<v8f16, v8i16, MSA128H>;
3511 def : MSABitconvertPat<v4f32, v4i32, MSA128W>;
3512 def : MSABitconvertPat<v2f64, v2i64, MSA128D>;
3514 // Little endian bitcasts are always no-ops
3515 def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>;
3516 def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>;
3517 def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>;
3518 def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>;
3519 def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>;
3520 def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>;
3522 def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>;
3523 def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>;
3524 def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>;
3525 def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>;
3526 def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>;
3528 def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>;
3529 def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>;
3530 def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>;
3531 def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>;
3532 def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>;
3534 def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>;
3535 def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>;
3536 def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>;
3537 def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>;
3538 def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>;
3540 def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>;
3541 def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>;
3542 def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>;
3543 def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>;
3544 def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>;
3546 def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>;
3547 def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>;
3548 def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>;
3549 def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>;
3550 def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>;
3552 // Big endian bitcasts expand to shuffle instructions.
3553 // This is because bitcast is defined to be a store/load sequence and the
3554 // vector store/load instructions are mixed-endian with respect to the vector
3555 // as a whole (little endian with respect to element order, but big endian
3558 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3559 RegisterClass DstRC, MSAInst Insn,
3560 RegisterClass ViaRC> :
3561 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3562 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3566 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3567 RegisterClass DstRC, MSAInst Insn,
3568 RegisterClass ViaRC> :
3569 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3570 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3574 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3575 RegisterClass DstRC> :
3576 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3578 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3579 RegisterClass DstRC> :
3580 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3582 class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT,
3583 RegisterClass DstRC> :
3584 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3588 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27),
3593 class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT,
3594 RegisterClass DstRC> :
3595 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3597 class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT,
3598 RegisterClass DstRC> :
3599 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3601 class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT,
3602 RegisterClass DstRC> :
3603 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>;
3605 def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>;
3606 def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>;
3607 def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>;
3608 def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>;
3609 def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>;
3610 def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>;
3612 def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>;
3613 def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>;
3614 def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>;
3615 def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>;
3616 def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>;
3618 def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>;
3619 def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>;
3620 def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>;
3621 def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>;
3622 def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>;
3624 def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>;
3625 def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>;
3626 def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>;
3627 def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>;
3628 def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>;
3630 def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>;
3631 def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>;
3632 def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>;
3633 def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>;
3634 def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>;
3636 def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>;
3637 def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>;
3638 def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>;
3639 def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>;
3640 def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>;
3642 def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>;
3643 def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>;
3644 def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>;
3645 def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>;
3646 def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>;
3648 // Pseudos used to implement BNZ.df, and BZ.df
3650 class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode,
3652 InstrItinClass itin = NoItinerary> :
3653 MipsPseudo<(outs GPR32:$dst),
3655 [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> {
3656 bit usesCustomInserter = 1;
3659 def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8,
3660 MSA128B, NoItinerary>;
3661 def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16,
3662 MSA128H, NoItinerary>;
3663 def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32,
3664 MSA128W, NoItinerary>;
3665 def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64,
3666 MSA128D, NoItinerary>;
3667 def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8,
3668 MSA128B, NoItinerary>;
3670 def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8,
3671 MSA128B, NoItinerary>;
3672 def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16,
3673 MSA128H, NoItinerary>;
3674 def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32,
3675 MSA128W, NoItinerary>;
3676 def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64,
3677 MSA128D, NoItinerary>;
3678 def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8,
3679 MSA128B, NoItinerary>;