1 //===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips MSA ASE instructions.
12 //===----------------------------------------------------------------------===//
14 def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;
15 def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
18 SDTCisVT<3, OtherVT>]>;
19 def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
22 SDTCisVT<3, OtherVT>]>;
23 def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>,
24 SDTCisInt<1>, SDTCisVec<1>,
25 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>;
26 def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
27 SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>;
28 def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
29 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
31 def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>;
32 def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>;
33 def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>;
34 def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>;
35 def MipsVSMax : SDNode<"MipsISD::VSMAX", SDTIntBinOp,
36 [SDNPCommutative, SDNPAssociative]>;
37 def MipsVSMin : SDNode<"MipsISD::VSMIN", SDTIntBinOp,
38 [SDNPCommutative, SDNPAssociative]>;
39 def MipsVUMax : SDNode<"MipsISD::VUMAX", SDTIntBinOp,
40 [SDNPCommutative, SDNPAssociative]>;
41 def MipsVUMin : SDNode<"MipsISD::VUMIN", SDTIntBinOp,
42 [SDNPCommutative, SDNPAssociative]>;
43 def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp,
44 [SDNPCommutative, SDNPAssociative]>;
45 def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>;
46 def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>;
47 def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>;
48 def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>;
49 def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>;
50 def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>;
51 def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>;
52 def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>;
54 def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>;
55 def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>;
57 def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT",
58 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
59 def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT",
60 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
64 def uimm2 : Operand<i32> {
65 let PrintMethod = "printUnsignedImm";
68 // The immediate of an LSA instruction needs special handling
69 // as the encoded value should be subtracted by one.
70 def uimm2LSAAsmOperand : AsmOperandClass {
72 let ParserMethod = "parseLSAImm";
73 let RenderMethod = "addImmOperands";
76 def LSAImm : Operand<i32> {
77 let PrintMethod = "printUnsignedImm";
78 let EncoderMethod = "getLSAImmEncoding";
79 let DecoderMethod = "DecodeLSAImm";
80 let ParserMatchClass = uimm2LSAAsmOperand;
83 def uimm3 : Operand<i32> {
84 let PrintMethod = "printUnsignedImm8";
87 def uimm4 : Operand<i32> {
88 let PrintMethod = "printUnsignedImm8";
91 def uimm8 : Operand<i32> {
92 let PrintMethod = "printUnsignedImm8";
95 def simm5 : Operand<i32>;
97 def simm10 : Operand<i32>;
99 def vsplat_uimm1 : Operand<vAny> {
100 let PrintMethod = "printUnsignedImm8";
103 def vsplat_uimm2 : Operand<vAny> {
104 let PrintMethod = "printUnsignedImm8";
107 def vsplat_uimm3 : Operand<vAny> {
108 let PrintMethod = "printUnsignedImm8";
111 def vsplat_uimm4 : Operand<vAny> {
112 let PrintMethod = "printUnsignedImm8";
115 def vsplat_uimm5 : Operand<vAny> {
116 let PrintMethod = "printUnsignedImm8";
119 def vsplat_uimm6 : Operand<vAny> {
120 let PrintMethod = "printUnsignedImm8";
123 def vsplat_uimm8 : Operand<vAny> {
124 let PrintMethod = "printUnsignedImm8";
127 def vsplat_simm5 : Operand<vAny>;
129 def vsplat_simm10 : Operand<vAny>;
131 def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>;
134 def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx),
135 (MipsVExtractSExt node:$vec, node:$idx, i8)>;
136 def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx),
137 (MipsVExtractSExt node:$vec, node:$idx, i16)>;
138 def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx),
139 (MipsVExtractSExt node:$vec, node:$idx, i32)>;
141 def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx),
142 (MipsVExtractZExt node:$vec, node:$idx, i8)>;
143 def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx),
144 (MipsVExtractZExt node:$vec, node:$idx, i16)>;
145 def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx),
146 (MipsVExtractZExt node:$vec, node:$idx, i32)>;
148 def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx),
149 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>;
150 def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx),
151 (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>;
152 def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx),
153 (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>;
155 class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> :
156 PatFrag<(ops node:$lhs, node:$rhs),
157 (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>;
159 // ISD::SETFALSE cannot occur
160 def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
161 def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
162 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
163 def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
164 def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>;
165 def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>;
166 def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>;
167 def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>;
168 def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>;
169 def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>;
170 def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>;
171 def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>;
172 def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>;
173 def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>;
174 def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>;
175 def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>;
176 def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>;
177 def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>;
178 def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>;
179 def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>;
180 def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>;
181 def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>;
182 def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>;
183 def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>;
184 def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
185 def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
186 def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>;
187 def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>;
188 // ISD::SETTRUE cannot occur
189 // ISD::SETFALSE2 cannot occur
190 // ISD::SETTRUE2 cannot occur
192 class vsetcc_type<ValueType ResTy, CondCode CC> :
193 PatFrag<(ops node:$lhs, node:$rhs),
194 (ResTy (vsetcc node:$lhs, node:$rhs, CC))>;
196 def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>;
197 def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>;
198 def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>;
199 def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>;
200 def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>;
201 def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>;
202 def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>;
203 def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>;
204 def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>;
205 def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>;
206 def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>;
207 def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>;
208 def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>;
209 def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>;
210 def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>;
211 def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>;
212 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
213 def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
214 def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
215 def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
217 def vsplati8 : PatFrag<(ops node:$e0),
218 (v16i8 (build_vector node:$e0, node:$e0,
225 node:$e0, node:$e0))>;
226 def vsplati16 : PatFrag<(ops node:$e0),
227 (v8i16 (build_vector node:$e0, node:$e0,
230 node:$e0, node:$e0))>;
231 def vsplati32 : PatFrag<(ops node:$e0),
232 (v4i32 (build_vector node:$e0, node:$e0,
233 node:$e0, node:$e0))>;
234 def vsplati64 : PatFrag<(ops node:$e0),
235 (v2i64 (build_vector:$v0 node:$e0, node:$e0))>;
236 def vsplatf32 : PatFrag<(ops node:$e0),
237 (v4f32 (build_vector node:$e0, node:$e0,
238 node:$e0, node:$e0))>;
239 def vsplatf64 : PatFrag<(ops node:$e0),
240 (v2f64 (build_vector node:$e0, node:$e0))>;
242 def vsplati8_elt : PatFrag<(ops node:$v, node:$i),
243 (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>;
244 def vsplati16_elt : PatFrag<(ops node:$v, node:$i),
245 (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>;
246 def vsplati32_elt : PatFrag<(ops node:$v, node:$i),
247 (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>;
248 def vsplati64_elt : PatFrag<(ops node:$v, node:$i),
249 (MipsVSHF (vsplati64 node:$i), node:$v, node:$v)>;
251 class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}],
252 SDNodeXForm xform = NOOP_SDNodeXForm>
253 : PatLeaf<frag, pred, xform> {
254 Operand OpClass = opclass;
257 class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn,
258 list<SDNode> roots = [],
259 list<SDNodeProperty> props = []> :
260 ComplexPattern<ty, numops, fn, roots, props> {
261 Operand OpClass = opclass;
264 def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1,
266 [build_vector, bitconvert]>;
268 def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1,
270 [build_vector, bitconvert]>;
272 def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1,
274 [build_vector, bitconvert]>;
276 def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1,
278 [build_vector, bitconvert]>;
280 def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1,
282 [build_vector, bitconvert]>;
284 def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1,
286 [build_vector, bitconvert]>;
288 def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1,
290 [build_vector, bitconvert]>;
292 def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1,
294 [build_vector, bitconvert]>;
296 def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1,
298 [build_vector, bitconvert]>;
300 def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1,
302 [build_vector, bitconvert]>;
304 def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1,
306 [build_vector, bitconvert]>;
308 def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1,
310 [build_vector, bitconvert]>;
312 def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1,
314 [build_vector, bitconvert]>;
316 def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1,
318 [build_vector, bitconvert]>;
320 def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1,
322 [build_vector, bitconvert]>;
324 def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1,
326 [build_vector, bitconvert]>;
328 // Any build_vector that is a constant splat with a value that is an exact
330 def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2",
331 [build_vector, bitconvert]>;
333 // Any build_vector that is a constant splat with a value that is the bitwise
334 // inverse of an exact power of 2
335 def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2",
336 [build_vector, bitconvert]>;
338 // Any build_vector that is a constant splat with only a consecutive sequence
339 // of left-most bits set.
340 def vsplat_maskl_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1,
342 [build_vector, bitconvert]>;
344 // Any build_vector that is a constant splat with only a consecutive sequence
345 // of right-most bits set.
346 def vsplat_maskr_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1,
348 [build_vector, bitconvert]>;
350 // Any build_vector that is a constant splat with a value that equals 1
351 // FIXME: These should be a ComplexPattern but we can't use them because the
352 // ISel generator requires the uses to have a name, but providing a name
353 // causes other errors ("used in pattern but not operand list")
354 def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{
356 EVT EltTy = N->getValueType(0).getVectorElementType();
358 return selectVSplat (N, Imm) &&
359 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
362 def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{
364 SDNode *BV = N->getOperand(0).getNode();
365 EVT EltTy = N->getValueType(0).getVectorElementType();
367 return selectVSplat (BV, Imm) &&
368 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
371 def vbclr_b : PatFrag<(ops node:$ws, node:$wt),
372 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
374 def vbclr_h : PatFrag<(ops node:$ws, node:$wt),
375 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
377 def vbclr_w : PatFrag<(ops node:$ws, node:$wt),
378 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
380 def vbclr_d : PatFrag<(ops node:$ws, node:$wt),
381 (and node:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1),
383 (bitconvert (v4i32 immAllOnesV))))>;
385 def vbneg_b : PatFrag<(ops node:$ws, node:$wt),
386 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
387 def vbneg_h : PatFrag<(ops node:$ws, node:$wt),
388 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
389 def vbneg_w : PatFrag<(ops node:$ws, node:$wt),
390 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
391 def vbneg_d : PatFrag<(ops node:$ws, node:$wt),
392 (xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
395 def vbset_b : PatFrag<(ops node:$ws, node:$wt),
396 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
397 def vbset_h : PatFrag<(ops node:$ws, node:$wt),
398 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
399 def vbset_w : PatFrag<(ops node:$ws, node:$wt),
400 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
401 def vbset_d : PatFrag<(ops node:$ws, node:$wt),
402 (or node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
405 def fms : PatFrag<(ops node:$wd, node:$ws, node:$wt),
406 (fsub node:$wd, (fmul node:$ws, node:$wt))>;
408 def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt),
409 (add node:$wd, (mul node:$ws, node:$wt))>;
411 def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt),
412 (sub node:$wd, (mul node:$ws, node:$wt))>;
414 def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt),
415 (fmul node:$ws, (fexp2 node:$wt))>;
418 def immSExt5 : ImmLeaf<i32, [{return isInt<5>(Imm);}]>;
419 def immSExt10: ImmLeaf<i32, [{return isInt<10>(Imm);}]>;
421 // Instruction encoding.
422 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
423 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
424 class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
425 class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>;
427 class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>;
428 class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>;
429 class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>;
430 class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>;
432 class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
433 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
434 class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>;
435 class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>;
437 class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>;
438 class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>;
439 class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>;
440 class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>;
442 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
443 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
444 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
445 class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
447 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
448 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
449 class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>;
450 class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>;
452 class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>;
454 class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>;
456 class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>;
457 class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>;
458 class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>;
459 class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>;
461 class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>;
462 class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>;
463 class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>;
464 class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>;
466 class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>;
467 class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>;
468 class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>;
469 class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>;
471 class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>;
472 class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>;
473 class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>;
474 class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>;
476 class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>;
477 class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>;
478 class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>;
479 class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>;
481 class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>;
482 class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>;
483 class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>;
484 class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>;
486 class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>;
487 class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>;
488 class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>;
489 class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>;
491 class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>;
492 class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>;
493 class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>;
494 class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>;
496 class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>;
497 class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>;
498 class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>;
499 class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>;
501 class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>;
502 class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>;
503 class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>;
504 class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>;
506 class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>;
507 class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>;
508 class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>;
509 class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>;
511 class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>;
512 class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>;
513 class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>;
514 class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>;
516 class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>;
518 class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>;
520 class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>;
522 class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>;
524 class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>;
525 class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>;
526 class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>;
527 class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>;
529 class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>;
530 class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>;
531 class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>;
532 class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>;
534 class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>;
535 class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>;
536 class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>;
537 class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>;
539 class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>;
541 class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>;
543 class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>;
545 class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>;
546 class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>;
547 class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>;
548 class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>;
550 class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>;
551 class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>;
552 class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>;
553 class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>;
555 class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>;
556 class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>;
557 class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>;
558 class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>;
560 class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>;
562 class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>;
563 class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>;
564 class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>;
565 class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>;
567 class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>;
568 class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>;
569 class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>;
570 class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>;
572 class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>;
574 class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>;
575 class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>;
576 class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>;
577 class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>;
579 class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>;
580 class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>;
581 class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>;
582 class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>;
584 class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>;
585 class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>;
586 class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>;
587 class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>;
589 class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>;
590 class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>;
591 class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>;
592 class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>;
594 class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>;
595 class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>;
596 class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>;
597 class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>;
599 class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>;
600 class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>;
601 class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>;
602 class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>;
604 class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>;
605 class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>;
606 class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>;
607 class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>;
609 class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>;
610 class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>;
611 class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>;
612 class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>;
614 class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>;
615 class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>;
616 class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>;
618 class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
619 class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
620 class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
622 class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>;
624 class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>;
625 class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>;
626 class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>;
627 class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>;
629 class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>;
630 class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>;
631 class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>;
632 class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>;
634 class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>;
635 class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>;
636 class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>;
638 class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>;
639 class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>;
640 class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>;
642 class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>;
643 class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>;
644 class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>;
646 class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>;
647 class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>;
648 class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>;
650 class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>;
651 class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>;
652 class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>;
654 class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>;
655 class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>;
656 class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>;
658 class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>;
659 class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>;
661 class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>;
662 class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>;
664 class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>;
665 class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>;
667 class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>;
668 class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>;
670 class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>;
671 class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>;
673 class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>;
674 class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>;
676 class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
677 class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
679 class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
680 class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
682 class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
683 class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
685 class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>;
686 class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>;
688 class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>;
689 class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>;
691 class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>;
692 class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>;
694 class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>;
695 class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>;
697 class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>;
698 class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>;
700 class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>;
701 class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>;
703 class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>;
704 class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>;
706 class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>;
707 class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>;
709 class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>;
710 class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>;
712 class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>;
713 class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>;
715 class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>;
716 class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>;
718 class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>;
719 class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>;
721 class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>;
722 class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>;
724 class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>;
725 class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>;
726 class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>;
728 class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>;
729 class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>;
731 class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>;
732 class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>;
734 class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>;
735 class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>;
737 class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>;
738 class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>;
740 class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>;
741 class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>;
743 class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>;
744 class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>;
746 class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>;
747 class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>;
749 class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>;
750 class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>;
752 class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>;
753 class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>;
755 class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>;
756 class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>;
758 class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>;
759 class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>;
761 class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>;
762 class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>;
764 class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>;
765 class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>;
767 class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>;
768 class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>;
770 class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>;
771 class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>;
773 class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>;
774 class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>;
776 class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>;
777 class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>;
779 class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>;
780 class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>;
782 class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>;
783 class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>;
785 class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>;
786 class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>;
788 class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>;
789 class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>;
791 class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>;
792 class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>;
794 class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>;
795 class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>;
797 class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>;
798 class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>;
800 class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>;
801 class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>;
803 class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>;
804 class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>;
806 class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>;
807 class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>;
809 class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>;
810 class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>;
812 class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>;
813 class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>;
815 class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>;
816 class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>;
817 class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>;
819 class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>;
820 class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>;
821 class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>;
823 class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>;
824 class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>;
825 class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>;
827 class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>;
828 class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>;
829 class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>;
831 class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>;
832 class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>;
833 class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>;
834 class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>;
836 class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>;
837 class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>;
838 class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>;
839 class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>;
841 class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>;
842 class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>;
843 class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>;
844 class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>;
846 class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>;
847 class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>;
848 class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>;
849 class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>;
851 class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>;
852 class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>;
853 class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>;
855 class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>;
856 class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>;
857 class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>;
858 class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>;
860 class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>;
861 class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>;
862 class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>;
863 class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>;
865 class LDI_B_ENC : MSA_I10_FMT<0b110, 0b00, 0b000111>;
866 class LDI_H_ENC : MSA_I10_FMT<0b110, 0b01, 0b000111>;
867 class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>;
868 class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>;
870 class LSA_ENC : SPECIAL_LSA_FMT<0b000101>;
872 class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;
873 class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
875 class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>;
876 class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>;
878 class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>;
879 class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>;
880 class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>;
881 class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>;
883 class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>;
884 class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>;
885 class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>;
886 class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>;
888 class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>;
889 class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>;
890 class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>;
891 class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>;
893 class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>;
894 class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>;
895 class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>;
896 class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>;
898 class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>;
899 class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>;
900 class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>;
901 class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>;
903 class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>;
904 class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>;
905 class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>;
906 class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>;
908 class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>;
909 class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>;
910 class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>;
911 class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>;
913 class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>;
914 class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>;
915 class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>;
916 class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>;
918 class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>;
919 class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>;
920 class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>;
921 class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>;
923 class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>;
924 class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>;
925 class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>;
926 class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>;
928 class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>;
929 class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>;
930 class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>;
931 class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>;
933 class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>;
934 class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>;
935 class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>;
936 class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>;
938 class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>;
939 class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>;
940 class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>;
941 class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>;
943 class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>;
945 class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>;
946 class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>;
948 class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>;
949 class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>;
951 class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>;
952 class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>;
953 class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>;
954 class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>;
956 class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>;
957 class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>;
959 class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>;
960 class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>;
962 class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>;
963 class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>;
964 class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>;
965 class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>;
967 class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>;
968 class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>;
969 class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>;
970 class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>;
972 class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>;
973 class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>;
974 class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>;
975 class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>;
977 class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>;
979 class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>;
981 class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>;
983 class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>;
985 class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>;
986 class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>;
987 class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>;
988 class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>;
990 class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>;
991 class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>;
992 class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>;
993 class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>;
995 class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>;
996 class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>;
997 class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>;
998 class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>;
1000 class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>;
1001 class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>;
1002 class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>;
1003 class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>;
1005 class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>;
1006 class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>;
1007 class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>;
1008 class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>;
1010 class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>;
1011 class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>;
1012 class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>;
1014 class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>;
1015 class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>;
1016 class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>;
1017 class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>;
1019 class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>;
1020 class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>;
1021 class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>;
1022 class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>;
1024 class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>;
1025 class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>;
1026 class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>;
1027 class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>;
1029 class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>;
1030 class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>;
1031 class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>;
1032 class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>;
1034 class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>;
1035 class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>;
1036 class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>;
1037 class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>;
1039 class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>;
1040 class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>;
1041 class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>;
1042 class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>;
1044 class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>;
1045 class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>;
1046 class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>;
1047 class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>;
1049 class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>;
1050 class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>;
1051 class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>;
1052 class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>;
1054 class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>;
1055 class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>;
1056 class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>;
1057 class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>;
1059 class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>;
1060 class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>;
1061 class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>;
1062 class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>;
1064 class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>;
1065 class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>;
1066 class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>;
1067 class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>;
1069 class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>;
1070 class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>;
1071 class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>;
1072 class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>;
1074 class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>;
1075 class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>;
1076 class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>;
1077 class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>;
1079 class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>;
1080 class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>;
1081 class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>;
1082 class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>;
1084 class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>;
1085 class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>;
1086 class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>;
1087 class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>;
1089 class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>;
1090 class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>;
1091 class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>;
1092 class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>;
1094 class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>;
1095 class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>;
1096 class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>;
1097 class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>;
1099 class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>;
1100 class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>;
1101 class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>;
1102 class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>;
1104 class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>;
1105 class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>;
1106 class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>;
1107 class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>;
1109 class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>;
1110 class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>;
1111 class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>;
1112 class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>;
1114 class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>;
1115 class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>;
1116 class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>;
1117 class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>;
1119 class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>;
1120 class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>;
1121 class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>;
1122 class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>;
1124 class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>;
1126 class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>;
1128 // Instruction desc.
1129 class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1130 ComplexPattern Imm, RegisterOperand ROWD,
1131 RegisterOperand ROWS = ROWD,
1132 InstrItinClass itin = NoItinerary> {
1133 dag OutOperandList = (outs ROWD:$wd);
1134 dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m);
1135 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1136 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1137 InstrItinClass Itinerary = itin;
1140 class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1141 ComplexPattern Imm, RegisterOperand ROWD,
1142 RegisterOperand ROWS = ROWD,
1143 InstrItinClass itin = NoItinerary> {
1144 dag OutOperandList = (outs ROWD:$wd);
1145 dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m);
1146 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1147 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1148 InstrItinClass Itinerary = itin;
1151 class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1152 ComplexPattern Imm, RegisterOperand ROWD,
1153 RegisterOperand ROWS = ROWD,
1154 InstrItinClass itin = NoItinerary> {
1155 dag OutOperandList = (outs ROWD:$wd);
1156 dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m);
1157 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1158 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1159 InstrItinClass Itinerary = itin;
1162 class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1163 ComplexPattern Imm, RegisterOperand ROWD,
1164 RegisterOperand ROWS = ROWD,
1165 InstrItinClass itin = NoItinerary> {
1166 dag OutOperandList = (outs ROWD:$wd);
1167 dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m);
1168 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1169 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1170 InstrItinClass Itinerary = itin;
1173 // This class is deprecated and will be removed soon.
1174 class MSA_BIT_B_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1175 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1176 InstrItinClass itin = NoItinerary> {
1177 dag OutOperandList = (outs ROWD:$wd);
1178 dag InOperandList = (ins ROWS:$ws, uimm3:$m);
1179 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1180 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt3:$m))];
1181 InstrItinClass Itinerary = itin;
1184 // This class is deprecated and will be removed soon.
1185 class MSA_BIT_H_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1186 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1187 InstrItinClass itin = NoItinerary> {
1188 dag OutOperandList = (outs ROWD:$wd);
1189 dag InOperandList = (ins ROWS:$ws, uimm4:$m);
1190 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1191 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt4:$m))];
1192 InstrItinClass Itinerary = itin;
1195 // This class is deprecated and will be removed soon.
1196 class MSA_BIT_W_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1197 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1198 InstrItinClass itin = NoItinerary> {
1199 dag OutOperandList = (outs ROWD:$wd);
1200 dag InOperandList = (ins ROWS:$ws, uimm5:$m);
1201 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1202 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt5:$m))];
1203 InstrItinClass Itinerary = itin;
1206 // This class is deprecated and will be removed soon.
1207 class MSA_BIT_D_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1208 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1209 InstrItinClass itin = NoItinerary> {
1210 dag OutOperandList = (outs ROWD:$wd);
1211 dag InOperandList = (ins ROWS:$ws, uimm6:$m);
1212 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1213 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt6:$m))];
1214 InstrItinClass Itinerary = itin;
1217 class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty,
1218 ComplexPattern Mask, RegisterOperand ROWD,
1219 RegisterOperand ROWS = ROWD,
1220 InstrItinClass itin = NoItinerary> {
1221 dag OutOperandList = (outs ROWD:$wd);
1222 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, vsplat_uimm8:$m);
1223 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1224 list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$wd_in),
1226 InstrItinClass Itinerary = itin;
1227 string Constraints = "$wd = $wd_in";
1230 class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty,
1231 RegisterOperand ROWD,
1232 RegisterOperand ROWS = ROWD,
1233 InstrItinClass itin = NoItinerary> :
1234 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskl_bits, ROWD, ROWS, itin>;
1236 class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty,
1237 RegisterOperand ROWD,
1238 RegisterOperand ROWS = ROWD,
1239 InstrItinClass itin = NoItinerary> :
1240 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskr_bits, ROWD, ROWS, itin>;
1242 class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1243 SplatComplexPattern SplatImm,
1244 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1245 InstrItinClass itin = NoItinerary> {
1246 dag OutOperandList = (outs ROWD:$wd);
1247 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m);
1248 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1249 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))];
1250 InstrItinClass Itinerary = itin;
1253 class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1254 ValueType VecTy, RegisterOperand ROD,
1255 RegisterOperand ROWS,
1256 InstrItinClass itin = NoItinerary> {
1257 dag OutOperandList = (outs ROD:$rd);
1258 dag InOperandList = (ins ROWS:$ws, uimm4:$n);
1259 string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]");
1260 list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), immZExt4:$n))];
1261 InstrItinClass Itinerary = itin;
1264 class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1265 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1266 InstrItinClass itin = NoItinerary> {
1267 dag OutOperandList = (outs ROWD:$wd);
1268 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, uimm4:$n);
1269 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1270 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1272 string Constraints = "$wd = $wd_in";
1273 InstrItinClass Itinerary = itin;
1276 class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy,
1277 RegisterClass RCD, RegisterClass RCWS> :
1278 MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, uimm4:$n),
1279 [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), immZExt4:$n))]> {
1280 bit usesCustomInserter = 1;
1283 class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1284 SplatComplexPattern SplatImm, RegisterOperand ROWD,
1285 RegisterOperand ROWS = ROWD,
1286 InstrItinClass itin = NoItinerary> {
1287 dag OutOperandList = (outs ROWD:$wd);
1288 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm);
1289 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm");
1290 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))];
1291 InstrItinClass Itinerary = itin;
1294 class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1295 SplatComplexPattern SplatImm, RegisterOperand ROWD,
1296 RegisterOperand ROWS = ROWD,
1297 InstrItinClass itin = NoItinerary> {
1298 dag OutOperandList = (outs ROWD:$wd);
1299 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8);
1300 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1301 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))];
1302 InstrItinClass Itinerary = itin;
1305 class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1306 RegisterOperand ROWS = ROWD,
1307 InstrItinClass itin = NoItinerary> {
1308 dag OutOperandList = (outs ROWD:$wd);
1309 dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
1310 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1311 list<dag> Pattern = [(set ROWD:$wd, (MipsSHF immZExt8:$u8, ROWS:$ws))];
1312 InstrItinClass Itinerary = itin;
1315 class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1316 InstrItinClass itin = NoItinerary> {
1317 dag OutOperandList = (outs ROWD:$wd);
1318 dag InOperandList = (ins vsplat_simm10:$s10);
1319 string AsmString = !strconcat(instr_asm, "\t$wd, $s10");
1320 // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp
1321 list<dag> Pattern = [];
1322 bit hasSideEffects = 0;
1323 InstrItinClass Itinerary = itin;
1326 class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1327 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1328 InstrItinClass itin = NoItinerary> {
1329 dag OutOperandList = (outs ROWD:$wd);
1330 dag InOperandList = (ins ROWS:$ws);
1331 string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1332 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1333 InstrItinClass Itinerary = itin;
1336 class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT,
1337 SDPatternOperator OpNode, RegisterOperand ROWD,
1338 RegisterOperand ROS = ROWD,
1339 InstrItinClass itin = NoItinerary> {
1340 dag OutOperandList = (outs ROWD:$wd);
1341 dag InOperandList = (ins ROS:$rs);
1342 string AsmString = !strconcat(instr_asm, "\t$wd, $rs");
1343 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))];
1344 InstrItinClass Itinerary = itin;
1347 class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode,
1348 RegisterClass RCWD, RegisterClass RCWS = RCWD> :
1349 MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs),
1350 [(set RCWD:$wd, (OpNode RCWS:$fs))]> {
1351 let usesCustomInserter = 1;
1354 class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1355 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1356 InstrItinClass itin = NoItinerary> {
1357 dag OutOperandList = (outs ROWD:$wd);
1358 dag InOperandList = (ins ROWS:$ws);
1359 string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1360 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1361 InstrItinClass Itinerary = itin;
1364 class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1365 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1366 RegisterOperand ROWT = ROWD,
1367 InstrItinClass itin = NoItinerary> {
1368 dag OutOperandList = (outs ROWD:$wd);
1369 dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1370 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1371 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1372 InstrItinClass Itinerary = itin;
1375 class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1376 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1377 RegisterOperand ROWT = ROWD,
1378 InstrItinClass itin = NoItinerary> {
1379 dag OutOperandList = (outs ROWD:$wd);
1380 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1381 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1382 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1384 string Constraints = "$wd = $wd_in";
1385 InstrItinClass Itinerary = itin;
1388 class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1389 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1390 InstrItinClass itin = NoItinerary> {
1391 dag OutOperandList = (outs ROWD:$wd);
1392 dag InOperandList = (ins ROWS:$ws, GPR32:$rt);
1393 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1394 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32:$rt))];
1395 InstrItinClass Itinerary = itin;
1398 class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1399 RegisterOperand ROWS = ROWD,
1400 RegisterOperand ROWT = ROWD,
1401 InstrItinClass itin = NoItinerary> {
1402 dag OutOperandList = (outs ROWD:$wd);
1403 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1404 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1405 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws,
1407 string Constraints = "$wd = $wd_in";
1408 InstrItinClass Itinerary = itin;
1411 class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1412 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1413 InstrItinClass itin = NoItinerary> {
1414 dag OutOperandList = (outs ROWD:$wd);
1415 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32:$rt);
1416 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1417 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1419 InstrItinClass Itinerary = itin;
1420 string Constraints = "$wd = $wd_in";
1423 class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1424 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1425 RegisterOperand ROWT = ROWD,
1426 InstrItinClass itin = NoItinerary> {
1427 dag OutOperandList = (outs ROWD:$wd);
1428 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1429 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1430 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1432 InstrItinClass Itinerary = itin;
1433 string Constraints = "$wd = $wd_in";
1436 class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1437 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1438 RegisterOperand ROWT = ROWD,
1439 InstrItinClass itin = NoItinerary> :
1440 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1442 class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1443 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1444 RegisterOperand ROWT = ROWD,
1445 InstrItinClass itin = NoItinerary> :
1446 MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1448 class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> {
1449 dag OutOperandList = (outs);
1450 dag InOperandList = (ins ROWD:$wt, brtarget:$offset);
1451 string AsmString = !strconcat(instr_asm, "\t$wt, $offset");
1452 list<dag> Pattern = [];
1453 InstrItinClass Itinerary = IIBranch;
1455 bit isTerminator = 1;
1456 bit hasDelaySlot = 1;
1457 list<Register> Defs = [AT];
1460 class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1461 RegisterOperand ROWD, RegisterOperand ROS,
1462 InstrItinClass itin = NoItinerary> {
1463 dag OutOperandList = (outs ROWD:$wd);
1464 dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, uimm6:$n);
1465 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs");
1466 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1469 InstrItinClass Itinerary = itin;
1470 string Constraints = "$wd = $wd_in";
1473 class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
1474 RegisterOperand ROWD, RegisterOperand ROFS> :
1475 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, uimm6:$n, ROFS:$fs),
1476 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
1478 bit usesCustomInserter = 1;
1479 string Constraints = "$wd = $wd_in";
1482 class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1483 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1484 InstrItinClass itin = NoItinerary> {
1485 dag OutOperandList = (outs ROWD:$wd);
1486 dag InOperandList = (ins ROWD:$wd_in, uimm6:$n, ROWS:$ws);
1487 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[0]");
1488 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1491 InstrItinClass Itinerary = itin;
1492 string Constraints = "$wd = $wd_in";
1495 class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1496 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1497 RegisterOperand ROWT = ROWD,
1498 InstrItinClass itin = NoItinerary> {
1499 dag OutOperandList = (outs ROWD:$wd);
1500 dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1501 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1502 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1503 InstrItinClass Itinerary = itin;
1506 class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm,
1507 RegisterOperand ROWD,
1508 RegisterOperand ROWS = ROWD,
1509 InstrItinClass itin = NoItinerary> {
1510 dag OutOperandList = (outs ROWD:$wd);
1511 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n);
1512 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1513 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws,
1515 InstrItinClass Itinerary = itin;
1518 class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD,
1519 RegisterOperand ROWS = ROWD,
1520 RegisterOperand ROWT = ROWD> :
1521 MSAPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt),
1522 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>;
1524 class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>,
1526 class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>,
1528 class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>,
1530 class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>,
1533 class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b,
1534 MSA128BOpnd>, IsCommutable;
1535 class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h,
1536 MSA128HOpnd>, IsCommutable;
1537 class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w,
1538 MSA128WOpnd>, IsCommutable;
1539 class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d,
1540 MSA128DOpnd>, IsCommutable;
1542 class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b,
1543 MSA128BOpnd>, IsCommutable;
1544 class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h,
1545 MSA128HOpnd>, IsCommutable;
1546 class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w,
1547 MSA128WOpnd>, IsCommutable;
1548 class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d,
1549 MSA128DOpnd>, IsCommutable;
1551 class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b,
1552 MSA128BOpnd>, IsCommutable;
1553 class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h,
1554 MSA128HOpnd>, IsCommutable;
1555 class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w,
1556 MSA128WOpnd>, IsCommutable;
1557 class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d,
1558 MSA128DOpnd>, IsCommutable;
1560 class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable;
1561 class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable;
1562 class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable;
1563 class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable;
1565 class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5,
1567 class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5,
1569 class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5,
1571 class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5,
1574 class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>;
1575 class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>;
1576 class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>;
1577 class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>;
1579 class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8,
1582 class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b,
1584 class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h,
1586 class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w,
1588 class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d,
1591 class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b,
1593 class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h,
1595 class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w,
1597 class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d,
1600 class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>,
1602 class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>,
1604 class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>,
1606 class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>,
1609 class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>,
1611 class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>,
1613 class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>,
1615 class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>,
1618 class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b,
1619 MSA128BOpnd>, IsCommutable;
1620 class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h,
1621 MSA128HOpnd>, IsCommutable;
1622 class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w,
1623 MSA128WOpnd>, IsCommutable;
1624 class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d,
1625 MSA128DOpnd>, IsCommutable;
1627 class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b,
1628 MSA128BOpnd>, IsCommutable;
1629 class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h,
1630 MSA128HOpnd>, IsCommutable;
1631 class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w,
1632 MSA128WOpnd>, IsCommutable;
1633 class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d,
1634 MSA128DOpnd>, IsCommutable;
1636 class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>;
1637 class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>;
1638 class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>;
1639 class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>;
1641 class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2,
1643 class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2,
1645 class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2,
1647 class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2,
1650 class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b,
1652 class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h,
1654 class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w,
1656 class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d,
1659 class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, MSA128BOpnd>;
1660 class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, MSA128HOpnd>;
1661 class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, MSA128WOpnd>;
1662 class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, MSA128DOpnd>;
1664 class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b,
1666 class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h,
1668 class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w,
1670 class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d,
1673 class BINSRI_B_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, MSA128BOpnd>;
1674 class BINSRI_H_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, MSA128HOpnd>;
1675 class BINSRI_W_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, MSA128WOpnd>;
1676 class BINSRI_D_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, MSA128DOpnd>;
1679 dag OutOperandList = (outs MSA128BOpnd:$wd);
1680 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1682 string AsmString = "bmnz.v\t$wd, $ws, $wt";
1683 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1685 MSA128BOpnd:$wd_in))];
1686 InstrItinClass Itinerary = NoItinerary;
1687 string Constraints = "$wd = $wd_in";
1690 class BMNZI_B_DESC {
1691 dag OutOperandList = (outs MSA128BOpnd:$wd);
1692 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1694 string AsmString = "bmnzi.b\t$wd, $ws, $u8";
1695 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1697 MSA128BOpnd:$wd_in))];
1698 InstrItinClass Itinerary = NoItinerary;
1699 string Constraints = "$wd = $wd_in";
1703 dag OutOperandList = (outs MSA128BOpnd:$wd);
1704 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1706 string AsmString = "bmz.v\t$wd, $ws, $wt";
1707 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1710 InstrItinClass Itinerary = NoItinerary;
1711 string Constraints = "$wd = $wd_in";
1715 dag OutOperandList = (outs MSA128BOpnd:$wd);
1716 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1718 string AsmString = "bmzi.b\t$wd, $ws, $u8";
1719 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1722 InstrItinClass Itinerary = NoItinerary;
1723 string Constraints = "$wd = $wd_in";
1726 class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>;
1727 class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>;
1728 class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>;
1729 class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>;
1731 class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2,
1733 class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2,
1735 class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2,
1737 class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2,
1740 class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>;
1741 class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>;
1742 class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>;
1743 class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>;
1745 class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>;
1748 dag OutOperandList = (outs MSA128BOpnd:$wd);
1749 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1751 string AsmString = "bsel.v\t$wd, $ws, $wt";
1752 list<dag> Pattern = [(set MSA128BOpnd:$wd,
1753 (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1755 InstrItinClass Itinerary = NoItinerary;
1756 string Constraints = "$wd = $wd_in";
1759 class BSELI_B_DESC {
1760 dag OutOperandList = (outs MSA128BOpnd:$wd);
1761 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1763 string AsmString = "bseli.b\t$wd, $ws, $u8";
1764 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in,
1766 vsplati8_uimm8:$u8))];
1767 InstrItinClass Itinerary = NoItinerary;
1768 string Constraints = "$wd = $wd_in";
1771 class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>;
1772 class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>;
1773 class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>;
1774 class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>;
1776 class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2,
1778 class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2,
1780 class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2,
1782 class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2,
1785 class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>;
1786 class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>;
1787 class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>;
1788 class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>;
1790 class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>;
1792 class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>,
1794 class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>,
1796 class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>,
1798 class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>,
1801 class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5,
1803 class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5,
1805 class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5,
1807 class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5,
1811 dag OutOperandList = (outs GPR32Opnd:$rd);
1812 dag InOperandList = (ins MSA128CROpnd:$cs);
1813 string AsmString = "cfcmsa\t$rd, $cs";
1814 InstrItinClass Itinerary = NoItinerary;
1815 bit hasSideEffects = 1;
1818 class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>;
1819 class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>;
1820 class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>;
1821 class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>;
1823 class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>;
1824 class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>;
1825 class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>;
1826 class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>;
1828 class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8,
1829 vsplati8_simm5, MSA128BOpnd>;
1830 class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16,
1831 vsplati16_simm5, MSA128HOpnd>;
1832 class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32,
1833 vsplati32_simm5, MSA128WOpnd>;
1834 class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64,
1835 vsplati64_simm5, MSA128DOpnd>;
1837 class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8,
1838 vsplati8_uimm5, MSA128BOpnd>;
1839 class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16,
1840 vsplati16_uimm5, MSA128HOpnd>;
1841 class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32,
1842 vsplati32_uimm5, MSA128WOpnd>;
1843 class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64,
1844 vsplati64_uimm5, MSA128DOpnd>;
1846 class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>;
1847 class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>;
1848 class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>;
1849 class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>;
1851 class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>;
1852 class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>;
1853 class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>;
1854 class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>;
1856 class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8,
1857 vsplati8_simm5, MSA128BOpnd>;
1858 class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16,
1859 vsplati16_simm5, MSA128HOpnd>;
1860 class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32,
1861 vsplati32_simm5, MSA128WOpnd>;
1862 class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64,
1863 vsplati64_simm5, MSA128DOpnd>;
1865 class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8,
1866 vsplati8_uimm5, MSA128BOpnd>;
1867 class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16,
1868 vsplati16_uimm5, MSA128HOpnd>;
1869 class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32,
1870 vsplati32_uimm5, MSA128WOpnd>;
1871 class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64,
1872 vsplati64_uimm5, MSA128DOpnd>;
1874 class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8,
1875 GPR32Opnd, MSA128BOpnd>;
1876 class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16,
1877 GPR32Opnd, MSA128HOpnd>;
1878 class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32,
1879 GPR32Opnd, MSA128WOpnd>;
1881 class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8,
1882 GPR32Opnd, MSA128BOpnd>;
1883 class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16,
1884 GPR32Opnd, MSA128HOpnd>;
1885 class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32,
1886 GPR32Opnd, MSA128WOpnd>;
1888 class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, FGR32,
1890 class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, FGR64,
1894 dag OutOperandList = (outs);
1895 dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs);
1896 string AsmString = "ctcmsa\t$cd, $rs";
1897 InstrItinClass Itinerary = NoItinerary;
1898 bit hasSideEffects = 1;
1901 class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>;
1902 class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>;
1903 class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>;
1904 class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>;
1906 class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>;
1907 class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>;
1908 class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>;
1909 class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>;
1911 class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h,
1912 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1914 class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w,
1915 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1917 class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d,
1918 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1921 class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h,
1922 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1924 class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w,
1925 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1927 class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d,
1928 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1931 class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h,
1932 MSA128HOpnd, MSA128BOpnd,
1933 MSA128BOpnd>, IsCommutable;
1934 class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w,
1935 MSA128WOpnd, MSA128HOpnd,
1936 MSA128HOpnd>, IsCommutable;
1937 class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d,
1938 MSA128DOpnd, MSA128WOpnd,
1939 MSA128WOpnd>, IsCommutable;
1941 class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h,
1942 MSA128HOpnd, MSA128BOpnd,
1943 MSA128BOpnd>, IsCommutable;
1944 class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w,
1945 MSA128WOpnd, MSA128HOpnd,
1946 MSA128HOpnd>, IsCommutable;
1947 class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d,
1948 MSA128DOpnd, MSA128WOpnd,
1949 MSA128WOpnd>, IsCommutable;
1951 class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h,
1952 MSA128HOpnd, MSA128BOpnd,
1954 class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w,
1955 MSA128WOpnd, MSA128HOpnd,
1957 class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d,
1958 MSA128DOpnd, MSA128WOpnd,
1961 class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h,
1962 MSA128HOpnd, MSA128BOpnd,
1964 class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w,
1965 MSA128WOpnd, MSA128HOpnd,
1967 class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d,
1968 MSA128DOpnd, MSA128WOpnd,
1971 class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>,
1973 class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>,
1976 class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>,
1978 class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>,
1981 class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>,
1983 class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>,
1986 class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w,
1988 class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d,
1991 class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>;
1992 class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>;
1994 class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>;
1995 class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>;
1997 class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>,
1999 class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>,
2002 class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>,
2004 class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>,
2007 class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>,
2009 class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>,
2012 class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>,
2014 class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>,
2017 class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>,
2019 class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>,
2022 class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>,
2024 class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>,
2027 class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>,
2029 class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>,
2032 class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>;
2033 class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>;
2035 class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h,
2036 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2037 class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w,
2038 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2040 // The fexp2.df instruction multiplies the first operand by 2 to the power of
2041 // the second operand. We therefore need a pseudo-insn in order to invent the
2042 // 1.0 when we only need to match ISD::FEXP2.
2043 class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>;
2044 class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>;
2045 let usesCustomInserter = 1 in {
2046 class FEXP2_W_1_PSEUDO_DESC :
2047 MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws),
2048 [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>;
2049 class FEXP2_D_1_PSEUDO_DESC :
2050 MSAPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws),
2051 [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>;
2054 class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w,
2055 MSA128WOpnd, MSA128HOpnd>;
2056 class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d,
2057 MSA128DOpnd, MSA128WOpnd>;
2059 class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w,
2060 MSA128WOpnd, MSA128HOpnd>;
2061 class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d,
2062 MSA128DOpnd, MSA128WOpnd>;
2064 class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>;
2065 class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>;
2067 class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>;
2068 class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>;
2070 class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w,
2071 MSA128WOpnd, MSA128HOpnd>;
2072 class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d,
2073 MSA128DOpnd, MSA128WOpnd>;
2075 class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w,
2076 MSA128WOpnd, MSA128HOpnd>;
2077 class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d,
2078 MSA128DOpnd, MSA128WOpnd>;
2080 class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8,
2081 MSA128BOpnd, GPR32Opnd>;
2082 class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16,
2083 MSA128HOpnd, GPR32Opnd>;
2084 class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32,
2085 MSA128WOpnd, GPR32Opnd>;
2087 class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W,
2089 class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D,
2092 class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>;
2093 class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>;
2095 class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>;
2096 class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>;
2098 class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>;
2099 class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>;
2101 class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w,
2103 class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d,
2106 class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>;
2107 class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>;
2109 class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w,
2111 class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d,
2114 class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", fms, MSA128WOpnd>;
2115 class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", fms, MSA128DOpnd>;
2117 class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>;
2118 class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>;
2120 class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>;
2121 class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>;
2123 class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>;
2124 class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>;
2126 class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w,
2128 class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d,
2131 class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>;
2132 class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>;
2134 class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>;
2135 class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>;
2137 class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>;
2138 class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>;
2140 class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>;
2141 class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>;
2143 class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>;
2144 class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>;
2146 class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>;
2147 class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>;
2149 class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>;
2150 class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>;
2152 class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>;
2153 class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>;
2155 class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w,
2157 class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d,
2160 class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w,
2162 class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d,
2165 class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w,
2167 class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d,
2170 class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w,
2172 class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d,
2175 class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w,
2177 class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d,
2180 class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w,
2182 class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d,
2185 class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w,
2187 class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d,
2190 class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h,
2191 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2192 class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w,
2193 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2195 class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint,
2197 class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint,
2200 class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint,
2202 class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint,
2205 class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h,
2206 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2207 class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w,
2208 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2209 class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d,
2210 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2212 class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h,
2213 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2214 class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w,
2215 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2216 class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d,
2217 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2219 class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h,
2220 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2221 class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w,
2222 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2223 class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d,
2224 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2226 class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h,
2227 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2228 class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w,
2229 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2230 class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d,
2231 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2233 class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>;
2234 class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>;
2235 class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>;
2236 class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>;
2238 class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>;
2239 class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>;
2240 class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>;
2241 class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>;
2243 class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>;
2244 class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>;
2245 class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>;
2246 class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>;
2248 class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>;
2249 class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>;
2250 class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>;
2251 class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>;
2253 class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8,
2254 MSA128BOpnd, GPR32Opnd>;
2255 class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16,
2256 MSA128HOpnd, GPR32Opnd>;
2257 class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32,
2258 MSA128WOpnd, GPR32Opnd>;
2260 class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32,
2261 MSA128WOpnd, FGR32Opnd>;
2262 class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64,
2263 MSA128DOpnd, FGR64Opnd>;
2265 class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", int_mips_insve_b,
2267 class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", int_mips_insve_h,
2269 class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", int_mips_insve_w,
2271 class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", int_mips_insve_d,
2274 class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2275 ValueType TyNode, RegisterOperand ROWD,
2276 Operand MemOpnd = mem_msa, ComplexPattern Addr = addrRegImm,
2277 InstrItinClass itin = NoItinerary> {
2278 dag OutOperandList = (outs ROWD:$wd);
2279 dag InOperandList = (ins MemOpnd:$addr);
2280 string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2281 list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))];
2282 InstrItinClass Itinerary = itin;
2283 string DecoderMethod = "DecodeMSA128Mem";
2286 class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd>;
2287 class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd>;
2288 class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd>;
2289 class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd>;
2291 class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>;
2292 class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>;
2293 class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>;
2294 class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>;
2297 dag OutOperandList = (outs GPR32Opnd:$rd);
2298 dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, LSAImm:$sa);
2299 string AsmString = "lsa\t$rd, $rs, $rt, $sa";
2300 list<dag> Pattern = [(set GPR32Opnd:$rd, (add GPR32Opnd:$rt,
2302 immZExt2Lsa:$sa)))];
2303 InstrItinClass Itinerary = NoItinerary;
2306 class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h,
2308 class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w,
2311 class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h,
2313 class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w,
2316 class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>;
2317 class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>;
2318 class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>;
2319 class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>;
2321 class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>;
2322 class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>;
2323 class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>;
2324 class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>;
2326 class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", MipsVSMax, MSA128BOpnd>;
2327 class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", MipsVSMax, MSA128HOpnd>;
2328 class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", MipsVSMax, MSA128WOpnd>;
2329 class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", MipsVSMax, MSA128DOpnd>;
2331 class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", MipsVUMax, MSA128BOpnd>;
2332 class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", MipsVUMax, MSA128HOpnd>;
2333 class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", MipsVUMax, MSA128WOpnd>;
2334 class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", MipsVUMax, MSA128DOpnd>;
2336 class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", MipsVSMax, vsplati8_simm5,
2338 class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", MipsVSMax, vsplati16_simm5,
2340 class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", MipsVSMax, vsplati32_simm5,
2342 class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", MipsVSMax, vsplati64_simm5,
2345 class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", MipsVUMax, vsplati8_uimm5,
2347 class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", MipsVUMax, vsplati16_uimm5,
2349 class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", MipsVUMax, vsplati32_uimm5,
2351 class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", MipsVUMax, vsplati64_uimm5,
2354 class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>;
2355 class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>;
2356 class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>;
2357 class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>;
2359 class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", MipsVSMin, MSA128BOpnd>;
2360 class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", MipsVSMin, MSA128HOpnd>;
2361 class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", MipsVSMin, MSA128WOpnd>;
2362 class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", MipsVSMin, MSA128DOpnd>;
2364 class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", MipsVUMin, MSA128BOpnd>;
2365 class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", MipsVUMin, MSA128HOpnd>;
2366 class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", MipsVUMin, MSA128WOpnd>;
2367 class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", MipsVUMin, MSA128DOpnd>;
2369 class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", MipsVSMin, vsplati8_simm5,
2371 class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", MipsVSMin, vsplati16_simm5,
2373 class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", MipsVSMin, vsplati32_simm5,
2375 class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", MipsVSMin, vsplati64_simm5,
2378 class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", MipsVUMin, vsplati8_uimm5,
2380 class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", MipsVUMin, vsplati16_uimm5,
2382 class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", MipsVUMin, vsplati32_uimm5,
2384 class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", MipsVUMin, vsplati64_uimm5,
2387 class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>;
2388 class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>;
2389 class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>;
2390 class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>;
2392 class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>;
2393 class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>;
2394 class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>;
2395 class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>;
2398 dag OutOperandList = (outs MSA128BOpnd:$wd);
2399 dag InOperandList = (ins MSA128BOpnd:$ws);
2400 string AsmString = "move.v\t$wd, $ws";
2401 list<dag> Pattern = [];
2402 InstrItinClass Itinerary = NoItinerary;
2405 class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h,
2407 class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w,
2410 class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h,
2412 class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w,
2415 class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>;
2416 class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>;
2417 class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>;
2418 class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>;
2420 class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h,
2422 class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w,
2425 class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h,
2427 class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w,
2430 class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>;
2431 class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>;
2432 class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>;
2433 class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>;
2435 class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>;
2436 class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>;
2437 class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>;
2438 class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>;
2440 class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>;
2441 class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>;
2442 class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>;
2443 class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>;
2445 class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>;
2446 class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>;
2447 class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>;
2448 class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>;
2450 class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8,
2453 class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>;
2454 class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>;
2455 class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>;
2456 class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>;
2458 class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>;
2460 class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>;
2461 class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>;
2462 class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>;
2463 class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>;
2465 class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>;
2466 class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>;
2467 class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>;
2468 class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>;
2470 class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>;
2471 class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>;
2472 class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>;
2473 class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>;
2475 class SAT_S_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b,
2477 class SAT_S_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h,
2479 class SAT_S_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w,
2481 class SAT_S_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d,
2484 class SAT_U_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b,
2486 class SAT_U_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h,
2488 class SAT_U_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w,
2490 class SAT_U_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d,
2493 class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>;
2494 class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>;
2495 class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>;
2497 class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>;
2498 class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>;
2499 class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>;
2500 class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>;
2502 class SLDI_B_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.b", int_mips_sldi_b,
2504 class SLDI_H_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.h", int_mips_sldi_h,
2506 class SLDI_W_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.w", int_mips_sldi_w,
2508 class SLDI_D_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.d", int_mips_sldi_d,
2511 class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>;
2512 class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>;
2513 class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>;
2514 class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>;
2516 class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3,
2518 class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4,
2520 class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5,
2522 class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6,
2525 class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt,
2527 class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt,
2529 class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt,
2531 class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt,
2534 class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4,
2536 class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3,
2538 class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2,
2540 class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1,
2543 class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>;
2544 class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>;
2545 class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>;
2546 class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>;
2548 class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3,
2550 class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4,
2552 class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5,
2554 class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6,
2557 class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>;
2558 class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>;
2559 class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>;
2560 class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>;
2562 class SRARI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srari.b", int_mips_srari_b,
2564 class SRARI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srari.h", int_mips_srari_h,
2566 class SRARI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srari.w", int_mips_srari_w,
2568 class SRARI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srari.d", int_mips_srari_d,
2571 class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>;
2572 class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>;
2573 class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>;
2574 class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>;
2576 class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3,
2578 class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4,
2580 class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5,
2582 class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6,
2585 class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>;
2586 class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>;
2587 class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>;
2588 class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>;
2590 class SRLRI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srlri.b", int_mips_srlri_b,
2592 class SRLRI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srlri.h", int_mips_srlri_h,
2594 class SRLRI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srlri.w", int_mips_srlri_w,
2596 class SRLRI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srlri.d", int_mips_srlri_d,
2599 class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2600 ValueType TyNode, RegisterOperand ROWD,
2601 Operand MemOpnd = mem_msa, ComplexPattern Addr = addrRegImm,
2602 InstrItinClass itin = NoItinerary> {
2603 dag OutOperandList = (outs);
2604 dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr);
2605 string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2606 list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)];
2607 InstrItinClass Itinerary = itin;
2608 string DecoderMethod = "DecodeMSA128Mem";
2611 class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd>;
2612 class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd>;
2613 class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd>;
2614 class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd>;
2616 class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b,
2618 class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h,
2620 class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w,
2622 class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d,
2625 class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b,
2627 class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h,
2629 class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w,
2631 class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d,
2634 class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b,
2636 class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h,
2638 class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w,
2640 class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d,
2643 class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b,
2645 class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h,
2647 class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w,
2649 class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d,
2652 class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>;
2653 class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>;
2654 class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>;
2655 class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>;
2657 class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5,
2659 class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5,
2661 class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5,
2663 class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5,
2666 class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>;
2667 class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>;
2668 class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>;
2669 class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>;
2671 class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>;
2672 class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>;
2673 class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>;
2674 class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>;
2676 class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8,
2679 // Instruction defs.
2680 def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC;
2681 def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC;
2682 def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC;
2683 def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC;
2685 def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC;
2686 def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC;
2687 def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC;
2688 def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC;
2690 def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC;
2691 def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC;
2692 def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC;
2693 def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC;
2695 def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC;
2696 def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC;
2697 def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC;
2698 def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC;
2700 def ADDV_B : ADDV_B_ENC, ADDV_B_DESC;
2701 def ADDV_H : ADDV_H_ENC, ADDV_H_DESC;
2702 def ADDV_W : ADDV_W_ENC, ADDV_W_DESC;
2703 def ADDV_D : ADDV_D_ENC, ADDV_D_DESC;
2705 def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC;
2706 def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC;
2707 def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC;
2708 def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC;
2710 def AND_V : AND_V_ENC, AND_V_DESC;
2711 def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC,
2712 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2715 def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC,
2716 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2719 def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC,
2720 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2724 def ANDI_B : ANDI_B_ENC, ANDI_B_DESC;
2726 def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC;
2727 def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC;
2728 def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC;
2729 def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC;
2731 def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC;
2732 def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC;
2733 def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC;
2734 def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC;
2736 def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC;
2737 def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC;
2738 def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC;
2739 def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC;
2741 def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC;
2742 def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC;
2743 def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC;
2744 def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC;
2746 def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC;
2747 def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC;
2748 def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC;
2749 def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC;
2751 def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC;
2752 def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC;
2753 def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC;
2754 def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC;
2756 def BCLR_B : BCLR_B_ENC, BCLR_B_DESC;
2757 def BCLR_H : BCLR_H_ENC, BCLR_H_DESC;
2758 def BCLR_W : BCLR_W_ENC, BCLR_W_DESC;
2759 def BCLR_D : BCLR_D_ENC, BCLR_D_DESC;
2761 def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC;
2762 def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC;
2763 def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC;
2764 def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC;
2766 def BINSL_B : BINSL_B_ENC, BINSL_B_DESC;
2767 def BINSL_H : BINSL_H_ENC, BINSL_H_DESC;
2768 def BINSL_W : BINSL_W_ENC, BINSL_W_DESC;
2769 def BINSL_D : BINSL_D_ENC, BINSL_D_DESC;
2771 def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC;
2772 def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC;
2773 def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC;
2774 def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC;
2776 def BINSR_B : BINSR_B_ENC, BINSR_B_DESC;
2777 def BINSR_H : BINSR_H_ENC, BINSR_H_DESC;
2778 def BINSR_W : BINSR_W_ENC, BINSR_W_DESC;
2779 def BINSR_D : BINSR_D_ENC, BINSR_D_DESC;
2781 def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC;
2782 def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC;
2783 def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC;
2784 def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC;
2786 def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC;
2788 def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC;
2790 def BMZ_V : BMZ_V_ENC, BMZ_V_DESC;
2792 def BMZI_B : BMZI_B_ENC, BMZI_B_DESC;
2794 def BNEG_B : BNEG_B_ENC, BNEG_B_DESC;
2795 def BNEG_H : BNEG_H_ENC, BNEG_H_DESC;
2796 def BNEG_W : BNEG_W_ENC, BNEG_W_DESC;
2797 def BNEG_D : BNEG_D_ENC, BNEG_D_DESC;
2799 def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC;
2800 def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC;
2801 def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC;
2802 def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC;
2804 def BNZ_B : BNZ_B_ENC, BNZ_B_DESC;
2805 def BNZ_H : BNZ_H_ENC, BNZ_H_DESC;
2806 def BNZ_W : BNZ_W_ENC, BNZ_W_DESC;
2807 def BNZ_D : BNZ_D_ENC, BNZ_D_DESC;
2809 def BNZ_V : BNZ_V_ENC, BNZ_V_DESC;
2811 def BSEL_V : BSEL_V_ENC, BSEL_V_DESC;
2813 class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> :
2814 MSAPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt),
2815 [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$ws, RO:$wt)))]>,
2816 PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in,
2817 MSA128BOpnd:$ws, MSA128BOpnd:$wt)> {
2818 let Constraints = "$wd_in = $wd";
2821 def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>;
2822 def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>;
2823 def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>;
2824 def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>;
2825 def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>;
2827 def BSELI_B : BSELI_B_ENC, BSELI_B_DESC;
2829 def BSET_B : BSET_B_ENC, BSET_B_DESC;
2830 def BSET_H : BSET_H_ENC, BSET_H_DESC;
2831 def BSET_W : BSET_W_ENC, BSET_W_DESC;
2832 def BSET_D : BSET_D_ENC, BSET_D_DESC;
2834 def BSETI_B : BSETI_B_ENC, BSETI_B_DESC;
2835 def BSETI_H : BSETI_H_ENC, BSETI_H_DESC;
2836 def BSETI_W : BSETI_W_ENC, BSETI_W_DESC;
2837 def BSETI_D : BSETI_D_ENC, BSETI_D_DESC;
2839 def BZ_B : BZ_B_ENC, BZ_B_DESC;
2840 def BZ_H : BZ_H_ENC, BZ_H_DESC;
2841 def BZ_W : BZ_W_ENC, BZ_W_DESC;
2842 def BZ_D : BZ_D_ENC, BZ_D_DESC;
2844 def BZ_V : BZ_V_ENC, BZ_V_DESC;
2846 def CEQ_B : CEQ_B_ENC, CEQ_B_DESC;
2847 def CEQ_H : CEQ_H_ENC, CEQ_H_DESC;
2848 def CEQ_W : CEQ_W_ENC, CEQ_W_DESC;
2849 def CEQ_D : CEQ_D_ENC, CEQ_D_DESC;
2851 def CEQI_B : CEQI_B_ENC, CEQI_B_DESC;
2852 def CEQI_H : CEQI_H_ENC, CEQI_H_DESC;
2853 def CEQI_W : CEQI_W_ENC, CEQI_W_DESC;
2854 def CEQI_D : CEQI_D_ENC, CEQI_D_DESC;
2856 def CFCMSA : CFCMSA_ENC, CFCMSA_DESC;
2858 def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC;
2859 def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC;
2860 def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC;
2861 def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC;
2863 def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC;
2864 def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC;
2865 def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC;
2866 def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC;
2868 def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC;
2869 def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC;
2870 def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC;
2871 def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC;
2873 def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC;
2874 def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC;
2875 def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC;
2876 def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC;
2878 def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC;
2879 def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC;
2880 def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC;
2881 def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC;
2883 def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC;
2884 def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC;
2885 def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC;
2886 def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC;
2888 def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC;
2889 def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC;
2890 def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC;
2891 def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC;
2893 def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC;
2894 def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC;
2895 def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC;
2896 def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC;
2898 def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC;
2899 def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC;
2900 def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC;
2902 def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC;
2903 def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC;
2904 def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC;
2906 def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC;
2907 def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC;
2909 def CTCMSA : CTCMSA_ENC, CTCMSA_DESC;
2911 def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC;
2912 def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC;
2913 def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC;
2914 def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC;
2916 def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC;
2917 def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC;
2918 def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC;
2919 def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC;
2921 def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC;
2922 def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC;
2923 def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC;
2925 def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC;
2926 def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC;
2927 def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC;
2929 def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC;
2930 def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC;
2931 def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC;
2933 def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC;
2934 def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC;
2935 def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC;
2937 def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC;
2938 def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC;
2939 def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC;
2941 def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC;
2942 def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC;
2943 def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC;
2945 def FADD_W : FADD_W_ENC, FADD_W_DESC;
2946 def FADD_D : FADD_D_ENC, FADD_D_DESC;
2948 def FCAF_W : FCAF_W_ENC, FCAF_W_DESC;
2949 def FCAF_D : FCAF_D_ENC, FCAF_D_DESC;
2951 def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC;
2952 def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC;
2954 def FCLE_W : FCLE_W_ENC, FCLE_W_DESC;
2955 def FCLE_D : FCLE_D_ENC, FCLE_D_DESC;
2957 def FCLT_W : FCLT_W_ENC, FCLT_W_DESC;
2958 def FCLT_D : FCLT_D_ENC, FCLT_D_DESC;
2960 def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC;
2961 def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC;
2963 def FCNE_W : FCNE_W_ENC, FCNE_W_DESC;
2964 def FCNE_D : FCNE_D_ENC, FCNE_D_DESC;
2966 def FCOR_W : FCOR_W_ENC, FCOR_W_DESC;
2967 def FCOR_D : FCOR_D_ENC, FCOR_D_DESC;
2969 def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC;
2970 def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC;
2972 def FCULE_W : FCULE_W_ENC, FCULE_W_DESC;
2973 def FCULE_D : FCULE_D_ENC, FCULE_D_DESC;
2975 def FCULT_W : FCULT_W_ENC, FCULT_W_DESC;
2976 def FCULT_D : FCULT_D_ENC, FCULT_D_DESC;
2978 def FCUN_W : FCUN_W_ENC, FCUN_W_DESC;
2979 def FCUN_D : FCUN_D_ENC, FCUN_D_DESC;
2981 def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC;
2982 def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC;
2984 def FDIV_W : FDIV_W_ENC, FDIV_W_DESC;
2985 def FDIV_D : FDIV_D_ENC, FDIV_D_DESC;
2987 def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC;
2988 def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC;
2990 def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC;
2991 def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC;
2992 def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC;
2993 def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC;
2995 def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC;
2996 def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC;
2998 def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC;
2999 def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC;
3001 def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC;
3002 def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC;
3004 def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC;
3005 def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC;
3007 def FFQL_W : FFQL_W_ENC, FFQL_W_DESC;
3008 def FFQL_D : FFQL_D_ENC, FFQL_D_DESC;
3010 def FFQR_W : FFQR_W_ENC, FFQR_W_DESC;
3011 def FFQR_D : FFQR_D_ENC, FFQR_D_DESC;
3013 def FILL_B : FILL_B_ENC, FILL_B_DESC;
3014 def FILL_H : FILL_H_ENC, FILL_H_DESC;
3015 def FILL_W : FILL_W_ENC, FILL_W_DESC;
3016 def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC;
3017 def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC;
3019 def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC;
3020 def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC;
3022 def FMADD_W : FMADD_W_ENC, FMADD_W_DESC;
3023 def FMADD_D : FMADD_D_ENC, FMADD_D_DESC;
3025 def FMAX_W : FMAX_W_ENC, FMAX_W_DESC;
3026 def FMAX_D : FMAX_D_ENC, FMAX_D_DESC;
3028 def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC;
3029 def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC;
3031 def FMIN_W : FMIN_W_ENC, FMIN_W_DESC;
3032 def FMIN_D : FMIN_D_ENC, FMIN_D_DESC;
3034 def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC;
3035 def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC;
3037 def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC;
3038 def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC;
3040 def FMUL_W : FMUL_W_ENC, FMUL_W_DESC;
3041 def FMUL_D : FMUL_D_ENC, FMUL_D_DESC;
3043 def FRINT_W : FRINT_W_ENC, FRINT_W_DESC;
3044 def FRINT_D : FRINT_D_ENC, FRINT_D_DESC;
3046 def FRCP_W : FRCP_W_ENC, FRCP_W_DESC;
3047 def FRCP_D : FRCP_D_ENC, FRCP_D_DESC;
3049 def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC;
3050 def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC;
3052 def FSAF_W : FSAF_W_ENC, FSAF_W_DESC;
3053 def FSAF_D : FSAF_D_ENC, FSAF_D_DESC;
3055 def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC;
3056 def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC;
3058 def FSLE_W : FSLE_W_ENC, FSLE_W_DESC;
3059 def FSLE_D : FSLE_D_ENC, FSLE_D_DESC;
3061 def FSLT_W : FSLT_W_ENC, FSLT_W_DESC;
3062 def FSLT_D : FSLT_D_ENC, FSLT_D_DESC;
3064 def FSNE_W : FSNE_W_ENC, FSNE_W_DESC;
3065 def FSNE_D : FSNE_D_ENC, FSNE_D_DESC;
3067 def FSOR_W : FSOR_W_ENC, FSOR_W_DESC;
3068 def FSOR_D : FSOR_D_ENC, FSOR_D_DESC;
3070 def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC;
3071 def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC;
3073 def FSUB_W : FSUB_W_ENC, FSUB_W_DESC;
3074 def FSUB_D : FSUB_D_ENC, FSUB_D_DESC;
3076 def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC;
3077 def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC;
3079 def FSULE_W : FSULE_W_ENC, FSULE_W_DESC;
3080 def FSULE_D : FSULE_D_ENC, FSULE_D_DESC;
3082 def FSULT_W : FSULT_W_ENC, FSULT_W_DESC;
3083 def FSULT_D : FSULT_D_ENC, FSULT_D_DESC;
3085 def FSUN_W : FSUN_W_ENC, FSUN_W_DESC;
3086 def FSUN_D : FSUN_D_ENC, FSUN_D_DESC;
3088 def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC;
3089 def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC;
3091 def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC;
3092 def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC;
3094 def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC;
3095 def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC;
3097 def FTQ_H : FTQ_H_ENC, FTQ_H_DESC;
3098 def FTQ_W : FTQ_W_ENC, FTQ_W_DESC;
3100 def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC;
3101 def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC;
3103 def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC;
3104 def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC;
3106 def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC;
3107 def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC;
3108 def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC;
3110 def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC;
3111 def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC;
3112 def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC;
3114 def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC;
3115 def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC;
3116 def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC;
3118 def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC;
3119 def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC;
3120 def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC;
3122 def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC;
3123 def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC;
3124 def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC;
3125 def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC;
3127 def ILVL_B : ILVL_B_ENC, ILVL_B_DESC;
3128 def ILVL_H : ILVL_H_ENC, ILVL_H_DESC;
3129 def ILVL_W : ILVL_W_ENC, ILVL_W_DESC;
3130 def ILVL_D : ILVL_D_ENC, ILVL_D_DESC;
3132 def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC;
3133 def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC;
3134 def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC;
3135 def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC;
3137 def ILVR_B : ILVR_B_ENC, ILVR_B_DESC;
3138 def ILVR_H : ILVR_H_ENC, ILVR_H_DESC;
3139 def ILVR_W : ILVR_W_ENC, ILVR_W_DESC;
3140 def ILVR_D : ILVR_D_ENC, ILVR_D_DESC;
3142 def INSERT_B : INSERT_B_ENC, INSERT_B_DESC;
3143 def INSERT_H : INSERT_H_ENC, INSERT_H_DESC;
3144 def INSERT_W : INSERT_W_ENC, INSERT_W_DESC;
3146 // INSERT_FW_PSEUDO defined after INSVE_W
3147 // INSERT_FD_PSEUDO defined after INSVE_D
3149 def INSVE_B : INSVE_B_ENC, INSVE_B_DESC;
3150 def INSVE_H : INSVE_H_ENC, INSVE_H_DESC;
3151 def INSVE_W : INSVE_W_ENC, INSVE_W_DESC;
3152 def INSVE_D : INSVE_D_ENC, INSVE_D_DESC;
3154 def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC;
3155 def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC;
3157 def LD_B: LD_B_ENC, LD_B_DESC;
3158 def LD_H: LD_H_ENC, LD_H_DESC;
3159 def LD_W: LD_W_ENC, LD_W_DESC;
3160 def LD_D: LD_D_ENC, LD_D_DESC;
3162 def LDI_B : LDI_B_ENC, LDI_B_DESC;
3163 def LDI_H : LDI_H_ENC, LDI_H_DESC;
3164 def LDI_W : LDI_W_ENC, LDI_W_DESC;
3165 def LDI_D : LDI_D_ENC, LDI_D_DESC;
3167 def LSA : LSA_ENC, LSA_DESC;
3169 def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC;
3170 def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC;
3172 def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC;
3173 def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC;
3175 def MADDV_B : MADDV_B_ENC, MADDV_B_DESC;
3176 def MADDV_H : MADDV_H_ENC, MADDV_H_DESC;
3177 def MADDV_W : MADDV_W_ENC, MADDV_W_DESC;
3178 def MADDV_D : MADDV_D_ENC, MADDV_D_DESC;
3180 def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC;
3181 def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC;
3182 def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC;
3183 def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC;
3185 def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC;
3186 def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC;
3187 def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC;
3188 def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC;
3190 def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC;
3191 def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC;
3192 def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC;
3193 def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC;
3195 def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC;
3196 def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC;
3197 def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC;
3198 def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC;
3200 def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC;
3201 def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC;
3202 def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC;
3203 def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC;
3205 def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC;
3206 def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC;
3207 def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC;
3208 def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC;
3210 def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC;
3211 def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC;
3212 def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC;
3213 def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC;
3215 def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC;
3216 def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC;
3217 def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC;
3218 def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC;
3220 def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC;
3221 def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC;
3222 def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC;
3223 def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC;
3225 def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC;
3226 def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC;
3227 def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC;
3228 def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC;
3230 def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC;
3231 def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC;
3232 def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC;
3233 def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC;
3235 def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC;
3236 def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC;
3237 def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC;
3238 def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC;
3240 def MOVE_V : MOVE_V_ENC, MOVE_V_DESC;
3242 def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC;
3243 def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC;
3245 def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC;
3246 def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC;
3248 def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC;
3249 def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC;
3250 def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC;
3251 def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC;
3253 def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC;
3254 def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC;
3256 def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC;
3257 def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC;
3259 def MULV_B : MULV_B_ENC, MULV_B_DESC;
3260 def MULV_H : MULV_H_ENC, MULV_H_DESC;
3261 def MULV_W : MULV_W_ENC, MULV_W_DESC;
3262 def MULV_D : MULV_D_ENC, MULV_D_DESC;
3264 def NLOC_B : NLOC_B_ENC, NLOC_B_DESC;
3265 def NLOC_H : NLOC_H_ENC, NLOC_H_DESC;
3266 def NLOC_W : NLOC_W_ENC, NLOC_W_DESC;
3267 def NLOC_D : NLOC_D_ENC, NLOC_D_DESC;
3269 def NLZC_B : NLZC_B_ENC, NLZC_B_DESC;
3270 def NLZC_H : NLZC_H_ENC, NLZC_H_DESC;
3271 def NLZC_W : NLZC_W_ENC, NLZC_W_DESC;
3272 def NLZC_D : NLZC_D_ENC, NLZC_D_DESC;
3274 def NOR_V : NOR_V_ENC, NOR_V_DESC;
3275 def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC,
3276 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3279 def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC,
3280 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3283 def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC,
3284 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3288 def NORI_B : NORI_B_ENC, NORI_B_DESC;
3290 def OR_V : OR_V_ENC, OR_V_DESC;
3291 def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC,
3292 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3295 def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC,
3296 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3299 def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC,
3300 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3304 def ORI_B : ORI_B_ENC, ORI_B_DESC;
3306 def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC;
3307 def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC;
3308 def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC;
3309 def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC;
3311 def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC;
3312 def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC;
3313 def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC;
3314 def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC;
3316 def PCNT_B : PCNT_B_ENC, PCNT_B_DESC;
3317 def PCNT_H : PCNT_H_ENC, PCNT_H_DESC;
3318 def PCNT_W : PCNT_W_ENC, PCNT_W_DESC;
3319 def PCNT_D : PCNT_D_ENC, PCNT_D_DESC;
3321 def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC;
3322 def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC;
3323 def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC;
3324 def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC;
3326 def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC;
3327 def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC;
3328 def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC;
3329 def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC;
3331 def SHF_B : SHF_B_ENC, SHF_B_DESC;
3332 def SHF_H : SHF_H_ENC, SHF_H_DESC;
3333 def SHF_W : SHF_W_ENC, SHF_W_DESC;
3335 def SLD_B : SLD_B_ENC, SLD_B_DESC;
3336 def SLD_H : SLD_H_ENC, SLD_H_DESC;
3337 def SLD_W : SLD_W_ENC, SLD_W_DESC;
3338 def SLD_D : SLD_D_ENC, SLD_D_DESC;
3340 def SLDI_B : SLDI_B_ENC, SLDI_B_DESC;
3341 def SLDI_H : SLDI_H_ENC, SLDI_H_DESC;
3342 def SLDI_W : SLDI_W_ENC, SLDI_W_DESC;
3343 def SLDI_D : SLDI_D_ENC, SLDI_D_DESC;
3345 def SLL_B : SLL_B_ENC, SLL_B_DESC;
3346 def SLL_H : SLL_H_ENC, SLL_H_DESC;
3347 def SLL_W : SLL_W_ENC, SLL_W_DESC;
3348 def SLL_D : SLL_D_ENC, SLL_D_DESC;
3350 def SLLI_B : SLLI_B_ENC, SLLI_B_DESC;
3351 def SLLI_H : SLLI_H_ENC, SLLI_H_DESC;
3352 def SLLI_W : SLLI_W_ENC, SLLI_W_DESC;
3353 def SLLI_D : SLLI_D_ENC, SLLI_D_DESC;
3355 def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC;
3356 def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC;
3357 def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC;
3358 def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC;
3360 def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC;
3361 def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC;
3362 def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC;
3363 def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC;
3365 def SRA_B : SRA_B_ENC, SRA_B_DESC;
3366 def SRA_H : SRA_H_ENC, SRA_H_DESC;
3367 def SRA_W : SRA_W_ENC, SRA_W_DESC;
3368 def SRA_D : SRA_D_ENC, SRA_D_DESC;
3370 def SRAI_B : SRAI_B_ENC, SRAI_B_DESC;
3371 def SRAI_H : SRAI_H_ENC, SRAI_H_DESC;
3372 def SRAI_W : SRAI_W_ENC, SRAI_W_DESC;
3373 def SRAI_D : SRAI_D_ENC, SRAI_D_DESC;
3375 def SRAR_B : SRAR_B_ENC, SRAR_B_DESC;
3376 def SRAR_H : SRAR_H_ENC, SRAR_H_DESC;
3377 def SRAR_W : SRAR_W_ENC, SRAR_W_DESC;
3378 def SRAR_D : SRAR_D_ENC, SRAR_D_DESC;
3380 def SRARI_B : SRARI_B_ENC, SRARI_B_DESC;
3381 def SRARI_H : SRARI_H_ENC, SRARI_H_DESC;
3382 def SRARI_W : SRARI_W_ENC, SRARI_W_DESC;
3383 def SRARI_D : SRARI_D_ENC, SRARI_D_DESC;
3385 def SRL_B : SRL_B_ENC, SRL_B_DESC;
3386 def SRL_H : SRL_H_ENC, SRL_H_DESC;
3387 def SRL_W : SRL_W_ENC, SRL_W_DESC;
3388 def SRL_D : SRL_D_ENC, SRL_D_DESC;
3390 def SRLI_B : SRLI_B_ENC, SRLI_B_DESC;
3391 def SRLI_H : SRLI_H_ENC, SRLI_H_DESC;
3392 def SRLI_W : SRLI_W_ENC, SRLI_W_DESC;
3393 def SRLI_D : SRLI_D_ENC, SRLI_D_DESC;
3395 def SRLR_B : SRLR_B_ENC, SRLR_B_DESC;
3396 def SRLR_H : SRLR_H_ENC, SRLR_H_DESC;
3397 def SRLR_W : SRLR_W_ENC, SRLR_W_DESC;
3398 def SRLR_D : SRLR_D_ENC, SRLR_D_DESC;
3400 def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC;
3401 def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC;
3402 def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC;
3403 def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC;
3405 def ST_B: ST_B_ENC, ST_B_DESC;
3406 def ST_H: ST_H_ENC, ST_H_DESC;
3407 def ST_W: ST_W_ENC, ST_W_DESC;
3408 def ST_D: ST_D_ENC, ST_D_DESC;
3410 def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC;
3411 def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC;
3412 def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC;
3413 def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC;
3415 def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC;
3416 def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC;
3417 def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC;
3418 def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC;
3420 def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC;
3421 def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC;
3422 def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC;
3423 def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC;
3425 def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC;
3426 def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC;
3427 def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC;
3428 def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC;
3430 def SUBV_B : SUBV_B_ENC, SUBV_B_DESC;
3431 def SUBV_H : SUBV_H_ENC, SUBV_H_DESC;
3432 def SUBV_W : SUBV_W_ENC, SUBV_W_DESC;
3433 def SUBV_D : SUBV_D_ENC, SUBV_D_DESC;
3435 def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC;
3436 def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC;
3437 def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC;
3438 def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC;
3440 def VSHF_B : VSHF_B_ENC, VSHF_B_DESC;
3441 def VSHF_H : VSHF_H_ENC, VSHF_H_DESC;
3442 def VSHF_W : VSHF_W_ENC, VSHF_W_DESC;
3443 def VSHF_D : VSHF_D_ENC, VSHF_D_DESC;
3445 def XOR_V : XOR_V_ENC, XOR_V_DESC;
3446 def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC,
3447 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3450 def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC,
3451 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3454 def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC,
3455 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3459 def XORI_B : XORI_B_ENC, XORI_B_DESC;
3462 class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> :
3463 Pat<pattern, result>, Requires<pred>;
3465 def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx),
3466 (COPY_S_W MSA128W:$ws, immZExt4:$idx)>;
3468 def : MSAPat<(v16i8 (load addr:$addr)), (LD_B addr:$addr)>;
3469 def : MSAPat<(v8i16 (load addr:$addr)), (LD_H addr:$addr)>;
3470 def : MSAPat<(v4i32 (load addr:$addr)), (LD_W addr:$addr)>;
3471 def : MSAPat<(v2i64 (load addr:$addr)), (LD_D addr:$addr)>;
3472 def : MSAPat<(v8f16 (load addr:$addr)), (LD_H addr:$addr)>;
3473 def : MSAPat<(v4f32 (load addr:$addr)), (LD_W addr:$addr)>;
3474 def : MSAPat<(v2f64 (load addr:$addr)), (LD_D addr:$addr)>;
3476 def : MSAPat<(v8f16 (load addrRegImm:$addr)), (LD_H addrRegImm:$addr)>;
3477 def : MSAPat<(v4f32 (load addrRegImm:$addr)), (LD_W addrRegImm:$addr)>;
3478 def : MSAPat<(v2f64 (load addrRegImm:$addr)), (LD_D addrRegImm:$addr)>;
3480 def : MSAPat<(store (v16i8 MSA128B:$ws), addr:$addr),
3481 (ST_B MSA128B:$ws, addr:$addr)>;
3482 def : MSAPat<(store (v8i16 MSA128H:$ws), addr:$addr),
3483 (ST_H MSA128H:$ws, addr:$addr)>;
3484 def : MSAPat<(store (v4i32 MSA128W:$ws), addr:$addr),
3485 (ST_W MSA128W:$ws, addr:$addr)>;
3486 def : MSAPat<(store (v2i64 MSA128D:$ws), addr:$addr),
3487 (ST_D MSA128D:$ws, addr:$addr)>;
3488 def : MSAPat<(store (v8f16 MSA128H:$ws), addr:$addr),
3489 (ST_H MSA128H:$ws, addr:$addr)>;
3490 def : MSAPat<(store (v4f32 MSA128W:$ws), addr:$addr),
3491 (ST_W MSA128W:$ws, addr:$addr)>;
3492 def : MSAPat<(store (v2f64 MSA128D:$ws), addr:$addr),
3493 (ST_D MSA128D:$ws, addr:$addr)>;
3495 def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrRegImm:$addr),
3496 (ST_H MSA128H:$ws, addrRegImm:$addr)>;
3497 def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrRegImm:$addr),
3498 (ST_W MSA128W:$ws, addrRegImm:$addr)>;
3499 def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrRegImm:$addr),
3500 (ST_D MSA128D:$ws, addrRegImm:$addr)>;
3502 class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD,
3503 RegisterOperand ROWS = ROWD,
3504 InstrItinClass itin = NoItinerary> :
3505 MSAPseudo<(outs ROWD:$wd),
3507 [(set ROWD:$wd, (fabs ROWS:$ws))]> {
3508 InstrItinClass Itinerary = itin;
3510 def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>,
3511 PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws,
3513 def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>,
3514 PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws,
3517 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3518 RegisterClass DstRC, list<Predicate> preds = [HasMSA]> :
3519 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3520 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3522 // These are endian-independant because the element size doesnt change
3523 def : MSABitconvertPat<v8i16, v8f16, MSA128H>;
3524 def : MSABitconvertPat<v4i32, v4f32, MSA128W>;
3525 def : MSABitconvertPat<v2i64, v2f64, MSA128D>;
3526 def : MSABitconvertPat<v8f16, v8i16, MSA128H>;
3527 def : MSABitconvertPat<v4f32, v4i32, MSA128W>;
3528 def : MSABitconvertPat<v2f64, v2i64, MSA128D>;
3530 // Little endian bitcasts are always no-ops
3531 def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>;
3532 def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>;
3533 def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>;
3534 def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>;
3535 def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>;
3536 def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>;
3538 def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>;
3539 def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>;
3540 def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>;
3541 def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>;
3542 def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>;
3544 def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>;
3545 def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>;
3546 def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>;
3547 def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>;
3548 def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>;
3550 def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>;
3551 def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>;
3552 def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>;
3553 def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>;
3554 def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>;
3556 def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>;
3557 def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>;
3558 def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>;
3559 def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>;
3560 def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>;
3562 def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>;
3563 def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>;
3564 def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>;
3565 def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>;
3566 def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>;
3568 // Big endian bitcasts expand to shuffle instructions.
3569 // This is because bitcast is defined to be a store/load sequence and the
3570 // vector store/load instructions are mixed-endian with respect to the vector
3571 // as a whole (little endian with respect to element order, but big endian
3574 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3575 RegisterClass DstRC, MSAInst Insn,
3576 RegisterClass ViaRC> :
3577 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3578 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3582 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3583 RegisterClass DstRC, MSAInst Insn,
3584 RegisterClass ViaRC> :
3585 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3586 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3590 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3591 RegisterClass DstRC> :
3592 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3594 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3595 RegisterClass DstRC> :
3596 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3598 class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT,
3599 RegisterClass DstRC> :
3600 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3604 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27),
3609 class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT,
3610 RegisterClass DstRC> :
3611 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3613 class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT,
3614 RegisterClass DstRC> :
3615 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3617 class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT,
3618 RegisterClass DstRC> :
3619 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>;
3621 def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>;
3622 def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>;
3623 def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>;
3624 def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>;
3625 def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>;
3626 def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>;
3628 def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>;
3629 def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>;
3630 def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>;
3631 def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>;
3632 def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>;
3634 def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>;
3635 def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>;
3636 def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>;
3637 def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>;
3638 def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>;
3640 def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>;
3641 def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>;
3642 def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>;
3643 def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>;
3644 def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>;
3646 def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>;
3647 def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>;
3648 def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>;
3649 def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>;
3650 def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>;
3652 def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>;
3653 def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>;
3654 def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>;
3655 def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>;
3656 def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>;
3658 def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>;
3659 def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>;
3660 def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>;
3661 def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>;
3662 def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>;
3664 // Pseudos used to implement BNZ.df, and BZ.df
3666 class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode,
3668 InstrItinClass itin = NoItinerary> :
3669 MipsPseudo<(outs GPR32:$dst),
3671 [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> {
3672 bit usesCustomInserter = 1;
3675 def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8,
3676 MSA128B, NoItinerary>;
3677 def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16,
3678 MSA128H, NoItinerary>;
3679 def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32,
3680 MSA128W, NoItinerary>;
3681 def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64,
3682 MSA128D, NoItinerary>;
3683 def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8,
3684 MSA128B, NoItinerary>;
3686 def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8,
3687 MSA128B, NoItinerary>;
3688 def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16,
3689 MSA128H, NoItinerary>;
3690 def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32,
3691 MSA128W, NoItinerary>;
3692 def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64,
3693 MSA128D, NoItinerary>;
3694 def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8,
3695 MSA128B, NoItinerary>;