1 //===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips MSA ASE instructions.
12 //===----------------------------------------------------------------------===//
14 def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;
15 def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
18 SDTCisVT<3, OtherVT>]>;
19 def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
22 SDTCisVT<3, OtherVT>]>;
23 def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>,
24 SDTCisInt<1>, SDTCisVec<1>,
25 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>;
26 def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
27 SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>;
28 def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
29 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
31 def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>;
32 def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>;
33 def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>;
34 def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>;
35 def MipsVSMax : SDNode<"MipsISD::VSMAX", SDTIntBinOp,
36 [SDNPCommutative, SDNPAssociative]>;
37 def MipsVSMin : SDNode<"MipsISD::VSMIN", SDTIntBinOp,
38 [SDNPCommutative, SDNPAssociative]>;
39 def MipsVUMax : SDNode<"MipsISD::VUMAX", SDTIntBinOp,
40 [SDNPCommutative, SDNPAssociative]>;
41 def MipsVUMin : SDNode<"MipsISD::VUMIN", SDTIntBinOp,
42 [SDNPCommutative, SDNPAssociative]>;
43 def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp,
44 [SDNPCommutative, SDNPAssociative]>;
45 def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>;
46 def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>;
47 def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>;
48 def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>;
49 def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>;
50 def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>;
51 def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>;
52 def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>;
54 def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>;
55 def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>;
57 def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT",
58 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
59 def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT",
60 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
64 def uimm2 : Operand<i32> {
65 let PrintMethod = "printUnsignedImm";
68 // The immediate of an LSA instruction needs special handling
69 // as the encoded value should be subtracted by one.
70 def uimm2LSAAsmOperand : AsmOperandClass {
72 let ParserMethod = "parseLSAImm";
73 let RenderMethod = "addImmOperands";
76 def LSAImm : Operand<i32> {
77 let PrintMethod = "printUnsignedImm";
78 let EncoderMethod = "getLSAImmEncoding";
79 let DecoderMethod = "DecodeLSAImm";
80 let ParserMatchClass = uimm2LSAAsmOperand;
83 def uimm3 : Operand<i32> {
84 let PrintMethod = "printUnsignedImm8";
87 def uimm4 : Operand<i32> {
88 let PrintMethod = "printUnsignedImm8";
91 def uimm8 : Operand<i32> {
92 let PrintMethod = "printUnsignedImm8";
95 def simm5 : Operand<i32>;
97 def simm10 : Operand<i32>;
99 def vsplat_uimm1 : Operand<vAny> {
100 let PrintMethod = "printUnsignedImm8";
103 def vsplat_uimm2 : Operand<vAny> {
104 let PrintMethod = "printUnsignedImm8";
107 def vsplat_uimm3 : Operand<vAny> {
108 let PrintMethod = "printUnsignedImm8";
111 def vsplat_uimm4 : Operand<vAny> {
112 let PrintMethod = "printUnsignedImm8";
115 def vsplat_uimm5 : Operand<vAny> {
116 let PrintMethod = "printUnsignedImm8";
119 def vsplat_uimm6 : Operand<vAny> {
120 let PrintMethod = "printUnsignedImm8";
123 def vsplat_uimm8 : Operand<vAny> {
124 let PrintMethod = "printUnsignedImm8";
127 def vsplat_simm5 : Operand<vAny>;
129 def vsplat_simm10 : Operand<vAny>;
131 def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>;
134 def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx),
135 (MipsVExtractSExt node:$vec, node:$idx, i8)>;
136 def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx),
137 (MipsVExtractSExt node:$vec, node:$idx, i16)>;
138 def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx),
139 (MipsVExtractSExt node:$vec, node:$idx, i32)>;
140 def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx),
141 (MipsVExtractSExt node:$vec, node:$idx, i64)>;
143 def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx),
144 (MipsVExtractZExt node:$vec, node:$idx, i8)>;
145 def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx),
146 (MipsVExtractZExt node:$vec, node:$idx, i16)>;
147 def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx),
148 (MipsVExtractZExt node:$vec, node:$idx, i32)>;
149 def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx),
150 (MipsVExtractZExt node:$vec, node:$idx, i64)>;
152 def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx),
153 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>;
154 def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx),
155 (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>;
156 def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx),
157 (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>;
159 class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> :
160 PatFrag<(ops node:$lhs, node:$rhs),
161 (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>;
163 // ISD::SETFALSE cannot occur
164 def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
165 def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
166 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
167 def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
168 def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>;
169 def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>;
170 def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>;
171 def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>;
172 def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>;
173 def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>;
174 def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>;
175 def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>;
176 def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>;
177 def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>;
178 def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>;
179 def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>;
180 def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>;
181 def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>;
182 def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>;
183 def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>;
184 def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>;
185 def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>;
186 def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>;
187 def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>;
188 def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
189 def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
190 def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>;
191 def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>;
192 // ISD::SETTRUE cannot occur
193 // ISD::SETFALSE2 cannot occur
194 // ISD::SETTRUE2 cannot occur
196 class vsetcc_type<ValueType ResTy, CondCode CC> :
197 PatFrag<(ops node:$lhs, node:$rhs),
198 (ResTy (vsetcc node:$lhs, node:$rhs, CC))>;
200 def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>;
201 def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>;
202 def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>;
203 def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>;
204 def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>;
205 def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>;
206 def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>;
207 def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>;
208 def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>;
209 def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>;
210 def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>;
211 def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>;
212 def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>;
213 def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>;
214 def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>;
215 def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>;
216 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
217 def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
218 def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
219 def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
221 def vsplati8 : PatFrag<(ops node:$e0),
222 (v16i8 (build_vector node:$e0, node:$e0,
229 node:$e0, node:$e0))>;
230 def vsplati16 : PatFrag<(ops node:$e0),
231 (v8i16 (build_vector node:$e0, node:$e0,
234 node:$e0, node:$e0))>;
235 def vsplati32 : PatFrag<(ops node:$e0),
236 (v4i32 (build_vector node:$e0, node:$e0,
237 node:$e0, node:$e0))>;
238 def vsplati64 : PatFrag<(ops node:$e0),
239 (v2i64 (build_vector node:$e0, node:$e0))>;
240 def vsplatf32 : PatFrag<(ops node:$e0),
241 (v4f32 (build_vector node:$e0, node:$e0,
242 node:$e0, node:$e0))>;
243 def vsplatf64 : PatFrag<(ops node:$e0),
244 (v2f64 (build_vector node:$e0, node:$e0))>;
246 def vsplati8_elt : PatFrag<(ops node:$v, node:$i),
247 (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>;
248 def vsplati16_elt : PatFrag<(ops node:$v, node:$i),
249 (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>;
250 def vsplati32_elt : PatFrag<(ops node:$v, node:$i),
251 (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>;
252 def vsplati64_elt : PatFrag<(ops node:$v, node:$i),
253 (MipsVSHF (vsplati64 node:$i), node:$v, node:$v)>;
255 class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}],
256 SDNodeXForm xform = NOOP_SDNodeXForm>
257 : PatLeaf<frag, pred, xform> {
258 Operand OpClass = opclass;
261 class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn,
262 list<SDNode> roots = [],
263 list<SDNodeProperty> props = []> :
264 ComplexPattern<ty, numops, fn, roots, props> {
265 Operand OpClass = opclass;
268 def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1,
270 [build_vector, bitconvert]>;
272 def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1,
274 [build_vector, bitconvert]>;
276 def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1,
278 [build_vector, bitconvert]>;
280 def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1,
282 [build_vector, bitconvert]>;
284 def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1,
286 [build_vector, bitconvert]>;
288 def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1,
290 [build_vector, bitconvert]>;
292 def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1,
294 [build_vector, bitconvert]>;
296 def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1,
298 [build_vector, bitconvert]>;
300 def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1,
302 [build_vector, bitconvert]>;
304 def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1,
306 [build_vector, bitconvert]>;
308 def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1,
310 [build_vector, bitconvert]>;
312 def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1,
314 [build_vector, bitconvert]>;
316 def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1,
318 [build_vector, bitconvert]>;
320 def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1,
322 [build_vector, bitconvert]>;
324 def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1,
326 [build_vector, bitconvert]>;
328 def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1,
330 [build_vector, bitconvert]>;
332 // Any build_vector that is a constant splat with a value that is an exact
334 def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2",
335 [build_vector, bitconvert]>;
337 // Any build_vector that is a constant splat with a value that is the bitwise
338 // inverse of an exact power of 2
339 def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2",
340 [build_vector, bitconvert]>;
342 // Any build_vector that is a constant splat with only a consecutive sequence
343 // of left-most bits set.
344 def vsplat_maskl_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1,
346 [build_vector, bitconvert]>;
348 // Any build_vector that is a constant splat with only a consecutive sequence
349 // of right-most bits set.
350 def vsplat_maskr_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1,
352 [build_vector, bitconvert]>;
354 // Any build_vector that is a constant splat with a value that equals 1
355 // FIXME: These should be a ComplexPattern but we can't use them because the
356 // ISel generator requires the uses to have a name, but providing a name
357 // causes other errors ("used in pattern but not operand list")
358 def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{
360 EVT EltTy = N->getValueType(0).getVectorElementType();
362 return selectVSplat (N, Imm) &&
363 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
366 def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{
368 SDNode *BV = N->getOperand(0).getNode();
369 EVT EltTy = N->getValueType(0).getVectorElementType();
371 return selectVSplat (BV, Imm) &&
372 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
375 def vbclr_b : PatFrag<(ops node:$ws, node:$wt),
376 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
378 def vbclr_h : PatFrag<(ops node:$ws, node:$wt),
379 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
381 def vbclr_w : PatFrag<(ops node:$ws, node:$wt),
382 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
384 def vbclr_d : PatFrag<(ops node:$ws, node:$wt),
385 (and node:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1),
387 (bitconvert (v4i32 immAllOnesV))))>;
389 def vbneg_b : PatFrag<(ops node:$ws, node:$wt),
390 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
391 def vbneg_h : PatFrag<(ops node:$ws, node:$wt),
392 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
393 def vbneg_w : PatFrag<(ops node:$ws, node:$wt),
394 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
395 def vbneg_d : PatFrag<(ops node:$ws, node:$wt),
396 (xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
399 def vbset_b : PatFrag<(ops node:$ws, node:$wt),
400 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
401 def vbset_h : PatFrag<(ops node:$ws, node:$wt),
402 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
403 def vbset_w : PatFrag<(ops node:$ws, node:$wt),
404 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
405 def vbset_d : PatFrag<(ops node:$ws, node:$wt),
406 (or node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
409 def fms : PatFrag<(ops node:$wd, node:$ws, node:$wt),
410 (fsub node:$wd, (fmul node:$ws, node:$wt))>;
412 def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt),
413 (add node:$wd, (mul node:$ws, node:$wt))>;
415 def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt),
416 (sub node:$wd, (mul node:$ws, node:$wt))>;
418 def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt),
419 (fmul node:$ws, (fexp2 node:$wt))>;
422 def immSExt5 : ImmLeaf<i32, [{return isInt<5>(Imm);}]>;
423 def immSExt10: ImmLeaf<i32, [{return isInt<10>(Imm);}]>;
425 // Instruction encoding.
426 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
427 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
428 class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
429 class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>;
431 class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>;
432 class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>;
433 class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>;
434 class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>;
436 class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
437 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
438 class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>;
439 class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>;
441 class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>;
442 class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>;
443 class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>;
444 class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>;
446 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
447 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
448 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
449 class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
451 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
452 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
453 class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>;
454 class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>;
456 class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>;
458 class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>;
460 class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>;
461 class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>;
462 class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>;
463 class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>;
465 class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>;
466 class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>;
467 class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>;
468 class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>;
470 class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>;
471 class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>;
472 class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>;
473 class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>;
475 class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>;
476 class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>;
477 class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>;
478 class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>;
480 class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>;
481 class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>;
482 class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>;
483 class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>;
485 class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>;
486 class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>;
487 class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>;
488 class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>;
490 class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>;
491 class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>;
492 class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>;
493 class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>;
495 class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>;
496 class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>;
497 class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>;
498 class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>;
500 class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>;
501 class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>;
502 class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>;
503 class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>;
505 class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>;
506 class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>;
507 class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>;
508 class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>;
510 class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>;
511 class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>;
512 class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>;
513 class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>;
515 class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>;
516 class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>;
517 class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>;
518 class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>;
520 class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>;
522 class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>;
524 class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>;
526 class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>;
528 class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>;
529 class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>;
530 class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>;
531 class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>;
533 class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>;
534 class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>;
535 class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>;
536 class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>;
538 class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>;
539 class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>;
540 class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>;
541 class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>;
543 class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>;
545 class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>;
547 class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>;
549 class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>;
550 class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>;
551 class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>;
552 class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>;
554 class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>;
555 class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>;
556 class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>;
557 class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>;
559 class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>;
560 class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>;
561 class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>;
562 class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>;
564 class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>;
566 class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>;
567 class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>;
568 class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>;
569 class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>;
571 class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>;
572 class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>;
573 class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>;
574 class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>;
576 class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>;
578 class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>;
579 class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>;
580 class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>;
581 class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>;
583 class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>;
584 class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>;
585 class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>;
586 class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>;
588 class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>;
589 class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>;
590 class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>;
591 class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>;
593 class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>;
594 class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>;
595 class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>;
596 class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>;
598 class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>;
599 class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>;
600 class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>;
601 class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>;
603 class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>;
604 class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>;
605 class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>;
606 class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>;
608 class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>;
609 class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>;
610 class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>;
611 class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>;
613 class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>;
614 class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>;
615 class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>;
616 class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>;
618 class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>;
619 class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>;
620 class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>;
621 class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>;
623 class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
624 class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
625 class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
626 class COPY_U_D_ENC : MSA_ELM_COPY_D_FMT<0b0011, 0b011001>;
628 class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>;
630 class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>;
631 class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>;
632 class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>;
633 class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>;
635 class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>;
636 class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>;
637 class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>;
638 class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>;
640 class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>;
641 class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>;
642 class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>;
644 class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>;
645 class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>;
646 class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>;
648 class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>;
649 class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>;
650 class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>;
652 class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>;
653 class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>;
654 class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>;
656 class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>;
657 class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>;
658 class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>;
660 class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>;
661 class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>;
662 class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>;
664 class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>;
665 class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>;
667 class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>;
668 class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>;
670 class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>;
671 class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>;
673 class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>;
674 class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>;
676 class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>;
677 class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>;
679 class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>;
680 class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>;
682 class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
683 class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
685 class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
686 class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
688 class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
689 class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
691 class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>;
692 class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>;
694 class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>;
695 class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>;
697 class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>;
698 class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>;
700 class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>;
701 class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>;
703 class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>;
704 class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>;
706 class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>;
707 class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>;
709 class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>;
710 class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>;
712 class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>;
713 class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>;
715 class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>;
716 class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>;
718 class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>;
719 class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>;
721 class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>;
722 class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>;
724 class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>;
725 class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>;
727 class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>;
728 class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>;
730 class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>;
731 class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>;
732 class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>;
733 class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>;
735 class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>;
736 class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>;
738 class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>;
739 class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>;
741 class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>;
742 class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>;
744 class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>;
745 class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>;
747 class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>;
748 class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>;
750 class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>;
751 class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>;
753 class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>;
754 class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>;
756 class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>;
757 class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>;
759 class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>;
760 class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>;
762 class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>;
763 class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>;
765 class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>;
766 class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>;
768 class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>;
769 class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>;
771 class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>;
772 class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>;
774 class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>;
775 class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>;
777 class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>;
778 class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>;
780 class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>;
781 class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>;
783 class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>;
784 class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>;
786 class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>;
787 class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>;
789 class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>;
790 class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>;
792 class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>;
793 class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>;
795 class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>;
796 class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>;
798 class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>;
799 class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>;
801 class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>;
802 class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>;
804 class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>;
805 class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>;
807 class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>;
808 class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>;
810 class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>;
811 class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>;
813 class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>;
814 class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>;
816 class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>;
817 class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>;
819 class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>;
820 class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>;
822 class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>;
823 class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>;
824 class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>;
826 class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>;
827 class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>;
828 class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>;
830 class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>;
831 class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>;
832 class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>;
834 class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>;
835 class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>;
836 class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>;
838 class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>;
839 class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>;
840 class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>;
841 class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>;
843 class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>;
844 class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>;
845 class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>;
846 class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>;
848 class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>;
849 class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>;
850 class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>;
851 class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>;
853 class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>;
854 class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>;
855 class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>;
856 class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>;
858 class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>;
859 class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>;
860 class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>;
862 class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>;
863 class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>;
864 class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>;
865 class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>;
867 class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>;
868 class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>;
869 class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>;
870 class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>;
872 class LDI_B_ENC : MSA_I10_FMT<0b110, 0b00, 0b000111>;
873 class LDI_H_ENC : MSA_I10_FMT<0b110, 0b01, 0b000111>;
874 class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>;
875 class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>;
877 class LSA_ENC : SPECIAL_LSA_FMT<0b000101>;
879 class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;
880 class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
882 class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>;
883 class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>;
885 class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>;
886 class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>;
887 class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>;
888 class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>;
890 class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>;
891 class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>;
892 class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>;
893 class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>;
895 class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>;
896 class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>;
897 class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>;
898 class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>;
900 class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>;
901 class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>;
902 class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>;
903 class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>;
905 class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>;
906 class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>;
907 class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>;
908 class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>;
910 class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>;
911 class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>;
912 class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>;
913 class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>;
915 class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>;
916 class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>;
917 class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>;
918 class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>;
920 class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>;
921 class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>;
922 class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>;
923 class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>;
925 class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>;
926 class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>;
927 class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>;
928 class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>;
930 class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>;
931 class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>;
932 class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>;
933 class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>;
935 class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>;
936 class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>;
937 class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>;
938 class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>;
940 class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>;
941 class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>;
942 class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>;
943 class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>;
945 class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>;
946 class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>;
947 class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>;
948 class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>;
950 class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>;
952 class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>;
953 class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>;
955 class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>;
956 class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>;
958 class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>;
959 class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>;
960 class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>;
961 class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>;
963 class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>;
964 class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>;
966 class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>;
967 class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>;
969 class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>;
970 class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>;
971 class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>;
972 class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>;
974 class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>;
975 class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>;
976 class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>;
977 class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>;
979 class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>;
980 class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>;
981 class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>;
982 class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>;
984 class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>;
986 class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>;
988 class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>;
990 class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>;
992 class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>;
993 class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>;
994 class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>;
995 class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>;
997 class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>;
998 class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>;
999 class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>;
1000 class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>;
1002 class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>;
1003 class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>;
1004 class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>;
1005 class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>;
1007 class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>;
1008 class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>;
1009 class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>;
1010 class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>;
1012 class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>;
1013 class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>;
1014 class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>;
1015 class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>;
1017 class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>;
1018 class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>;
1019 class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>;
1021 class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>;
1022 class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>;
1023 class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>;
1024 class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>;
1026 class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>;
1027 class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>;
1028 class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>;
1029 class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>;
1031 class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>;
1032 class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>;
1033 class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>;
1034 class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>;
1036 class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>;
1037 class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>;
1038 class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>;
1039 class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>;
1041 class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>;
1042 class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>;
1043 class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>;
1044 class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>;
1046 class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>;
1047 class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>;
1048 class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>;
1049 class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>;
1051 class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>;
1052 class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>;
1053 class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>;
1054 class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>;
1056 class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>;
1057 class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>;
1058 class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>;
1059 class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>;
1061 class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>;
1062 class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>;
1063 class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>;
1064 class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>;
1066 class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>;
1067 class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>;
1068 class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>;
1069 class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>;
1071 class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>;
1072 class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>;
1073 class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>;
1074 class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>;
1076 class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>;
1077 class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>;
1078 class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>;
1079 class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>;
1081 class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>;
1082 class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>;
1083 class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>;
1084 class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>;
1086 class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>;
1087 class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>;
1088 class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>;
1089 class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>;
1091 class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>;
1092 class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>;
1093 class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>;
1094 class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>;
1096 class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>;
1097 class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>;
1098 class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>;
1099 class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>;
1101 class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>;
1102 class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>;
1103 class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>;
1104 class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>;
1106 class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>;
1107 class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>;
1108 class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>;
1109 class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>;
1111 class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>;
1112 class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>;
1113 class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>;
1114 class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>;
1116 class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>;
1117 class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>;
1118 class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>;
1119 class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>;
1121 class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>;
1122 class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>;
1123 class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>;
1124 class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>;
1126 class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>;
1127 class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>;
1128 class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>;
1129 class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>;
1131 class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>;
1133 class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>;
1135 // Instruction desc.
1136 class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1137 ComplexPattern Imm, RegisterOperand ROWD,
1138 RegisterOperand ROWS = ROWD,
1139 InstrItinClass itin = NoItinerary> {
1140 dag OutOperandList = (outs ROWD:$wd);
1141 dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m);
1142 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1143 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1144 InstrItinClass Itinerary = itin;
1147 class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1148 ComplexPattern Imm, RegisterOperand ROWD,
1149 RegisterOperand ROWS = ROWD,
1150 InstrItinClass itin = NoItinerary> {
1151 dag OutOperandList = (outs ROWD:$wd);
1152 dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m);
1153 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1154 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1155 InstrItinClass Itinerary = itin;
1158 class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1159 ComplexPattern Imm, RegisterOperand ROWD,
1160 RegisterOperand ROWS = ROWD,
1161 InstrItinClass itin = NoItinerary> {
1162 dag OutOperandList = (outs ROWD:$wd);
1163 dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m);
1164 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1165 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1166 InstrItinClass Itinerary = itin;
1169 class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1170 ComplexPattern Imm, RegisterOperand ROWD,
1171 RegisterOperand ROWS = ROWD,
1172 InstrItinClass itin = NoItinerary> {
1173 dag OutOperandList = (outs ROWD:$wd);
1174 dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m);
1175 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1176 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1177 InstrItinClass Itinerary = itin;
1180 // This class is deprecated and will be removed soon.
1181 class MSA_BIT_B_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1182 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1183 InstrItinClass itin = NoItinerary> {
1184 dag OutOperandList = (outs ROWD:$wd);
1185 dag InOperandList = (ins ROWS:$ws, uimm3:$m);
1186 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1187 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt3:$m))];
1188 InstrItinClass Itinerary = itin;
1191 // This class is deprecated and will be removed soon.
1192 class MSA_BIT_H_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1193 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1194 InstrItinClass itin = NoItinerary> {
1195 dag OutOperandList = (outs ROWD:$wd);
1196 dag InOperandList = (ins ROWS:$ws, uimm4:$m);
1197 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1198 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt4:$m))];
1199 InstrItinClass Itinerary = itin;
1202 // This class is deprecated and will be removed soon.
1203 class MSA_BIT_W_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1204 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1205 InstrItinClass itin = NoItinerary> {
1206 dag OutOperandList = (outs ROWD:$wd);
1207 dag InOperandList = (ins ROWS:$ws, uimm5:$m);
1208 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1209 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt5:$m))];
1210 InstrItinClass Itinerary = itin;
1213 // This class is deprecated and will be removed soon.
1214 class MSA_BIT_D_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1215 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1216 InstrItinClass itin = NoItinerary> {
1217 dag OutOperandList = (outs ROWD:$wd);
1218 dag InOperandList = (ins ROWS:$ws, uimm6:$m);
1219 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1220 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt6:$m))];
1221 InstrItinClass Itinerary = itin;
1224 class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty,
1225 ComplexPattern Mask, RegisterOperand ROWD,
1226 RegisterOperand ROWS = ROWD,
1227 InstrItinClass itin = NoItinerary> {
1228 dag OutOperandList = (outs ROWD:$wd);
1229 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, vsplat_uimm8:$m);
1230 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1231 list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$wd_in),
1233 InstrItinClass Itinerary = itin;
1234 string Constraints = "$wd = $wd_in";
1237 class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty,
1238 RegisterOperand ROWD,
1239 RegisterOperand ROWS = ROWD,
1240 InstrItinClass itin = NoItinerary> :
1241 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskl_bits, ROWD, ROWS, itin>;
1243 class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty,
1244 RegisterOperand ROWD,
1245 RegisterOperand ROWS = ROWD,
1246 InstrItinClass itin = NoItinerary> :
1247 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskr_bits, ROWD, ROWS, itin>;
1249 class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1250 SplatComplexPattern SplatImm,
1251 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1252 InstrItinClass itin = NoItinerary> {
1253 dag OutOperandList = (outs ROWD:$wd);
1254 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m);
1255 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1256 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))];
1257 InstrItinClass Itinerary = itin;
1260 class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1261 ValueType VecTy, RegisterOperand ROD,
1262 RegisterOperand ROWS,
1263 InstrItinClass itin = NoItinerary> {
1264 dag OutOperandList = (outs ROD:$rd);
1265 dag InOperandList = (ins ROWS:$ws, uimm4:$n);
1266 string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]");
1267 list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), immZExt4:$n))];
1268 InstrItinClass Itinerary = itin;
1271 class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1272 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1273 InstrItinClass itin = NoItinerary> {
1274 dag OutOperandList = (outs ROWD:$wd);
1275 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, uimm4:$n);
1276 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1277 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1279 string Constraints = "$wd = $wd_in";
1280 InstrItinClass Itinerary = itin;
1283 class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy,
1284 RegisterClass RCD, RegisterClass RCWS> :
1285 MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, uimm4:$n),
1286 [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), immZExt4:$n))]> {
1287 bit usesCustomInserter = 1;
1290 class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1291 SplatComplexPattern SplatImm, RegisterOperand ROWD,
1292 RegisterOperand ROWS = ROWD,
1293 InstrItinClass itin = NoItinerary> {
1294 dag OutOperandList = (outs ROWD:$wd);
1295 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm);
1296 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm");
1297 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))];
1298 InstrItinClass Itinerary = itin;
1301 class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1302 SplatComplexPattern SplatImm, RegisterOperand ROWD,
1303 RegisterOperand ROWS = ROWD,
1304 InstrItinClass itin = NoItinerary> {
1305 dag OutOperandList = (outs ROWD:$wd);
1306 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8);
1307 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1308 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))];
1309 InstrItinClass Itinerary = itin;
1312 class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1313 RegisterOperand ROWS = ROWD,
1314 InstrItinClass itin = NoItinerary> {
1315 dag OutOperandList = (outs ROWD:$wd);
1316 dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
1317 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1318 list<dag> Pattern = [(set ROWD:$wd, (MipsSHF immZExt8:$u8, ROWS:$ws))];
1319 InstrItinClass Itinerary = itin;
1322 class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1323 InstrItinClass itin = NoItinerary> {
1324 dag OutOperandList = (outs ROWD:$wd);
1325 dag InOperandList = (ins vsplat_simm10:$s10);
1326 string AsmString = !strconcat(instr_asm, "\t$wd, $s10");
1327 // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp
1328 list<dag> Pattern = [];
1329 bit hasSideEffects = 0;
1330 InstrItinClass Itinerary = itin;
1333 class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1334 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1335 InstrItinClass itin = NoItinerary> {
1336 dag OutOperandList = (outs ROWD:$wd);
1337 dag InOperandList = (ins ROWS:$ws);
1338 string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1339 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1340 InstrItinClass Itinerary = itin;
1343 class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT,
1344 SDPatternOperator OpNode, RegisterOperand ROWD,
1345 RegisterOperand ROS = ROWD,
1346 InstrItinClass itin = NoItinerary> {
1347 dag OutOperandList = (outs ROWD:$wd);
1348 dag InOperandList = (ins ROS:$rs);
1349 string AsmString = !strconcat(instr_asm, "\t$wd, $rs");
1350 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))];
1351 InstrItinClass Itinerary = itin;
1354 class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode,
1355 RegisterClass RCWD, RegisterClass RCWS = RCWD> :
1356 MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs),
1357 [(set RCWD:$wd, (OpNode RCWS:$fs))]> {
1358 let usesCustomInserter = 1;
1361 class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1362 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1363 InstrItinClass itin = NoItinerary> {
1364 dag OutOperandList = (outs ROWD:$wd);
1365 dag InOperandList = (ins ROWS:$ws);
1366 string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1367 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1368 InstrItinClass Itinerary = itin;
1371 class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1372 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1373 RegisterOperand ROWT = ROWD,
1374 InstrItinClass itin = NoItinerary> {
1375 dag OutOperandList = (outs ROWD:$wd);
1376 dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1377 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1378 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1379 InstrItinClass Itinerary = itin;
1382 class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1383 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1384 RegisterOperand ROWT = ROWD,
1385 InstrItinClass itin = NoItinerary> {
1386 dag OutOperandList = (outs ROWD:$wd);
1387 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1388 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1389 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1391 string Constraints = "$wd = $wd_in";
1392 InstrItinClass Itinerary = itin;
1395 class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1396 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1397 InstrItinClass itin = NoItinerary> {
1398 dag OutOperandList = (outs ROWD:$wd);
1399 dag InOperandList = (ins ROWS:$ws, GPR32:$rt);
1400 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1401 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32:$rt))];
1402 InstrItinClass Itinerary = itin;
1405 class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1406 RegisterOperand ROWS = ROWD,
1407 RegisterOperand ROWT = ROWD,
1408 InstrItinClass itin = NoItinerary> {
1409 dag OutOperandList = (outs ROWD:$wd);
1410 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1411 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1412 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws,
1414 string Constraints = "$wd = $wd_in";
1415 InstrItinClass Itinerary = itin;
1418 class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1419 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1420 InstrItinClass itin = NoItinerary> {
1421 dag OutOperandList = (outs ROWD:$wd);
1422 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32:$rt);
1423 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1424 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1426 InstrItinClass Itinerary = itin;
1427 string Constraints = "$wd = $wd_in";
1430 class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1431 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1432 RegisterOperand ROWT = ROWD,
1433 InstrItinClass itin = NoItinerary> {
1434 dag OutOperandList = (outs ROWD:$wd);
1435 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1436 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1437 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1439 InstrItinClass Itinerary = itin;
1440 string Constraints = "$wd = $wd_in";
1443 class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1444 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1445 RegisterOperand ROWT = ROWD,
1446 InstrItinClass itin = NoItinerary> :
1447 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1449 class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1450 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1451 RegisterOperand ROWT = ROWD,
1452 InstrItinClass itin = NoItinerary> :
1453 MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1455 class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> {
1456 dag OutOperandList = (outs);
1457 dag InOperandList = (ins ROWD:$wt, brtarget:$offset);
1458 string AsmString = !strconcat(instr_asm, "\t$wt, $offset");
1459 list<dag> Pattern = [];
1460 InstrItinClass Itinerary = IIBranch;
1462 bit isTerminator = 1;
1463 bit hasDelaySlot = 1;
1464 list<Register> Defs = [AT];
1467 class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1468 RegisterOperand ROWD, RegisterOperand ROS,
1469 InstrItinClass itin = NoItinerary> {
1470 dag OutOperandList = (outs ROWD:$wd);
1471 dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, uimm6:$n);
1472 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs");
1473 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1476 InstrItinClass Itinerary = itin;
1477 string Constraints = "$wd = $wd_in";
1480 class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
1481 RegisterOperand ROWD, RegisterOperand ROFS> :
1482 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, uimm6:$n, ROFS:$fs),
1483 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
1485 bit usesCustomInserter = 1;
1486 string Constraints = "$wd = $wd_in";
1489 class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1490 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1491 InstrItinClass itin = NoItinerary> {
1492 dag OutOperandList = (outs ROWD:$wd);
1493 dag InOperandList = (ins ROWD:$wd_in, uimm6:$n, ROWS:$ws);
1494 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[0]");
1495 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1498 InstrItinClass Itinerary = itin;
1499 string Constraints = "$wd = $wd_in";
1502 class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1503 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1504 RegisterOperand ROWT = ROWD,
1505 InstrItinClass itin = NoItinerary> {
1506 dag OutOperandList = (outs ROWD:$wd);
1507 dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1508 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1509 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1510 InstrItinClass Itinerary = itin;
1513 class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm,
1514 RegisterOperand ROWD,
1515 RegisterOperand ROWS = ROWD,
1516 InstrItinClass itin = NoItinerary> {
1517 dag OutOperandList = (outs ROWD:$wd);
1518 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n);
1519 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1520 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws,
1522 InstrItinClass Itinerary = itin;
1525 class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD,
1526 RegisterOperand ROWS = ROWD,
1527 RegisterOperand ROWT = ROWD> :
1528 MSAPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt),
1529 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>;
1531 class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>,
1533 class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>,
1535 class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>,
1537 class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>,
1540 class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b,
1541 MSA128BOpnd>, IsCommutable;
1542 class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h,
1543 MSA128HOpnd>, IsCommutable;
1544 class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w,
1545 MSA128WOpnd>, IsCommutable;
1546 class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d,
1547 MSA128DOpnd>, IsCommutable;
1549 class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b,
1550 MSA128BOpnd>, IsCommutable;
1551 class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h,
1552 MSA128HOpnd>, IsCommutable;
1553 class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w,
1554 MSA128WOpnd>, IsCommutable;
1555 class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d,
1556 MSA128DOpnd>, IsCommutable;
1558 class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b,
1559 MSA128BOpnd>, IsCommutable;
1560 class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h,
1561 MSA128HOpnd>, IsCommutable;
1562 class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w,
1563 MSA128WOpnd>, IsCommutable;
1564 class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d,
1565 MSA128DOpnd>, IsCommutable;
1567 class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable;
1568 class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable;
1569 class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable;
1570 class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable;
1572 class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5,
1574 class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5,
1576 class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5,
1578 class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5,
1581 class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>;
1582 class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>;
1583 class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>;
1584 class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>;
1586 class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8,
1589 class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b,
1591 class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h,
1593 class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w,
1595 class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d,
1598 class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b,
1600 class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h,
1602 class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w,
1604 class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d,
1607 class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>,
1609 class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>,
1611 class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>,
1613 class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>,
1616 class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>,
1618 class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>,
1620 class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>,
1622 class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>,
1625 class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b,
1626 MSA128BOpnd>, IsCommutable;
1627 class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h,
1628 MSA128HOpnd>, IsCommutable;
1629 class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w,
1630 MSA128WOpnd>, IsCommutable;
1631 class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d,
1632 MSA128DOpnd>, IsCommutable;
1634 class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b,
1635 MSA128BOpnd>, IsCommutable;
1636 class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h,
1637 MSA128HOpnd>, IsCommutable;
1638 class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w,
1639 MSA128WOpnd>, IsCommutable;
1640 class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d,
1641 MSA128DOpnd>, IsCommutable;
1643 class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>;
1644 class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>;
1645 class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>;
1646 class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>;
1648 class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2,
1650 class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2,
1652 class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2,
1654 class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2,
1657 class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b,
1659 class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h,
1661 class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w,
1663 class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d,
1666 class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, MSA128BOpnd>;
1667 class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, MSA128HOpnd>;
1668 class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, MSA128WOpnd>;
1669 class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, MSA128DOpnd>;
1671 class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b,
1673 class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h,
1675 class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w,
1677 class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d,
1680 class BINSRI_B_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, MSA128BOpnd>;
1681 class BINSRI_H_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, MSA128HOpnd>;
1682 class BINSRI_W_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, MSA128WOpnd>;
1683 class BINSRI_D_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, MSA128DOpnd>;
1686 dag OutOperandList = (outs MSA128BOpnd:$wd);
1687 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1689 string AsmString = "bmnz.v\t$wd, $ws, $wt";
1690 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1692 MSA128BOpnd:$wd_in))];
1693 InstrItinClass Itinerary = NoItinerary;
1694 string Constraints = "$wd = $wd_in";
1697 class BMNZI_B_DESC {
1698 dag OutOperandList = (outs MSA128BOpnd:$wd);
1699 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1701 string AsmString = "bmnzi.b\t$wd, $ws, $u8";
1702 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1704 MSA128BOpnd:$wd_in))];
1705 InstrItinClass Itinerary = NoItinerary;
1706 string Constraints = "$wd = $wd_in";
1710 dag OutOperandList = (outs MSA128BOpnd:$wd);
1711 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1713 string AsmString = "bmz.v\t$wd, $ws, $wt";
1714 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1717 InstrItinClass Itinerary = NoItinerary;
1718 string Constraints = "$wd = $wd_in";
1722 dag OutOperandList = (outs MSA128BOpnd:$wd);
1723 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1725 string AsmString = "bmzi.b\t$wd, $ws, $u8";
1726 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1729 InstrItinClass Itinerary = NoItinerary;
1730 string Constraints = "$wd = $wd_in";
1733 class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>;
1734 class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>;
1735 class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>;
1736 class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>;
1738 class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2,
1740 class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2,
1742 class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2,
1744 class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2,
1747 class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>;
1748 class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>;
1749 class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>;
1750 class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>;
1752 class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>;
1755 dag OutOperandList = (outs MSA128BOpnd:$wd);
1756 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1758 string AsmString = "bsel.v\t$wd, $ws, $wt";
1759 list<dag> Pattern = [(set MSA128BOpnd:$wd,
1760 (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1762 InstrItinClass Itinerary = NoItinerary;
1763 string Constraints = "$wd = $wd_in";
1766 class BSELI_B_DESC {
1767 dag OutOperandList = (outs MSA128BOpnd:$wd);
1768 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1770 string AsmString = "bseli.b\t$wd, $ws, $u8";
1771 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in,
1773 vsplati8_uimm8:$u8))];
1774 InstrItinClass Itinerary = NoItinerary;
1775 string Constraints = "$wd = $wd_in";
1778 class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>;
1779 class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>;
1780 class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>;
1781 class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>;
1783 class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2,
1785 class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2,
1787 class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2,
1789 class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2,
1792 class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>;
1793 class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>;
1794 class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>;
1795 class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>;
1797 class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>;
1799 class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>,
1801 class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>,
1803 class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>,
1805 class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>,
1808 class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5,
1810 class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5,
1812 class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5,
1814 class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5,
1818 dag OutOperandList = (outs GPR32Opnd:$rd);
1819 dag InOperandList = (ins MSA128CROpnd:$cs);
1820 string AsmString = "cfcmsa\t$rd, $cs";
1821 InstrItinClass Itinerary = NoItinerary;
1822 bit hasSideEffects = 1;
1825 class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>;
1826 class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>;
1827 class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>;
1828 class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>;
1830 class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>;
1831 class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>;
1832 class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>;
1833 class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>;
1835 class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8,
1836 vsplati8_simm5, MSA128BOpnd>;
1837 class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16,
1838 vsplati16_simm5, MSA128HOpnd>;
1839 class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32,
1840 vsplati32_simm5, MSA128WOpnd>;
1841 class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64,
1842 vsplati64_simm5, MSA128DOpnd>;
1844 class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8,
1845 vsplati8_uimm5, MSA128BOpnd>;
1846 class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16,
1847 vsplati16_uimm5, MSA128HOpnd>;
1848 class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32,
1849 vsplati32_uimm5, MSA128WOpnd>;
1850 class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64,
1851 vsplati64_uimm5, MSA128DOpnd>;
1853 class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>;
1854 class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>;
1855 class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>;
1856 class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>;
1858 class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>;
1859 class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>;
1860 class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>;
1861 class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>;
1863 class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8,
1864 vsplati8_simm5, MSA128BOpnd>;
1865 class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16,
1866 vsplati16_simm5, MSA128HOpnd>;
1867 class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32,
1868 vsplati32_simm5, MSA128WOpnd>;
1869 class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64,
1870 vsplati64_simm5, MSA128DOpnd>;
1872 class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8,
1873 vsplati8_uimm5, MSA128BOpnd>;
1874 class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16,
1875 vsplati16_uimm5, MSA128HOpnd>;
1876 class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32,
1877 vsplati32_uimm5, MSA128WOpnd>;
1878 class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64,
1879 vsplati64_uimm5, MSA128DOpnd>;
1881 class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8,
1882 GPR32Opnd, MSA128BOpnd>;
1883 class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16,
1884 GPR32Opnd, MSA128HOpnd>;
1885 class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32,
1886 GPR32Opnd, MSA128WOpnd>;
1887 class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64,
1888 GPR64Opnd, MSA128DOpnd>;
1890 class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8,
1891 GPR32Opnd, MSA128BOpnd>;
1892 class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16,
1893 GPR32Opnd, MSA128HOpnd>;
1894 class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32,
1895 GPR32Opnd, MSA128WOpnd>;
1896 class COPY_U_D_DESC : MSA_COPY_DESC_BASE<"copy_u.d", vextract_zext_i64, v2i64,
1897 GPR64Opnd, MSA128DOpnd>;
1899 class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, FGR32,
1901 class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, FGR64,
1905 dag OutOperandList = (outs);
1906 dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs);
1907 string AsmString = "ctcmsa\t$cd, $rs";
1908 InstrItinClass Itinerary = NoItinerary;
1909 bit hasSideEffects = 1;
1912 class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>;
1913 class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>;
1914 class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>;
1915 class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>;
1917 class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>;
1918 class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>;
1919 class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>;
1920 class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>;
1922 class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h,
1923 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1925 class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w,
1926 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1928 class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d,
1929 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1932 class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h,
1933 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1935 class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w,
1936 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1938 class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d,
1939 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1942 class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h,
1943 MSA128HOpnd, MSA128BOpnd,
1944 MSA128BOpnd>, IsCommutable;
1945 class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w,
1946 MSA128WOpnd, MSA128HOpnd,
1947 MSA128HOpnd>, IsCommutable;
1948 class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d,
1949 MSA128DOpnd, MSA128WOpnd,
1950 MSA128WOpnd>, IsCommutable;
1952 class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h,
1953 MSA128HOpnd, MSA128BOpnd,
1954 MSA128BOpnd>, IsCommutable;
1955 class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w,
1956 MSA128WOpnd, MSA128HOpnd,
1957 MSA128HOpnd>, IsCommutable;
1958 class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d,
1959 MSA128DOpnd, MSA128WOpnd,
1960 MSA128WOpnd>, IsCommutable;
1962 class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h,
1963 MSA128HOpnd, MSA128BOpnd,
1965 class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w,
1966 MSA128WOpnd, MSA128HOpnd,
1968 class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d,
1969 MSA128DOpnd, MSA128WOpnd,
1972 class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h,
1973 MSA128HOpnd, MSA128BOpnd,
1975 class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w,
1976 MSA128WOpnd, MSA128HOpnd,
1978 class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d,
1979 MSA128DOpnd, MSA128WOpnd,
1982 class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>,
1984 class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>,
1987 class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>,
1989 class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>,
1992 class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>,
1994 class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>,
1997 class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w,
1999 class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d,
2002 class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>;
2003 class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>;
2005 class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>;
2006 class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>;
2008 class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>,
2010 class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>,
2013 class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>,
2015 class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>,
2018 class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>,
2020 class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>,
2023 class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>,
2025 class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>,
2028 class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>,
2030 class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>,
2033 class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>,
2035 class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>,
2038 class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>,
2040 class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>,
2043 class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>;
2044 class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>;
2046 class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h,
2047 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2048 class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w,
2049 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2051 // The fexp2.df instruction multiplies the first operand by 2 to the power of
2052 // the second operand. We therefore need a pseudo-insn in order to invent the
2053 // 1.0 when we only need to match ISD::FEXP2.
2054 class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>;
2055 class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>;
2056 let usesCustomInserter = 1 in {
2057 class FEXP2_W_1_PSEUDO_DESC :
2058 MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws),
2059 [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>;
2060 class FEXP2_D_1_PSEUDO_DESC :
2061 MSAPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws),
2062 [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>;
2065 class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w,
2066 MSA128WOpnd, MSA128HOpnd>;
2067 class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d,
2068 MSA128DOpnd, MSA128WOpnd>;
2070 class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w,
2071 MSA128WOpnd, MSA128HOpnd>;
2072 class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d,
2073 MSA128DOpnd, MSA128WOpnd>;
2075 class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>;
2076 class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>;
2078 class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>;
2079 class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>;
2081 class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w,
2082 MSA128WOpnd, MSA128HOpnd>;
2083 class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d,
2084 MSA128DOpnd, MSA128WOpnd>;
2086 class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w,
2087 MSA128WOpnd, MSA128HOpnd>;
2088 class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d,
2089 MSA128DOpnd, MSA128WOpnd>;
2091 class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8,
2092 MSA128BOpnd, GPR32Opnd>;
2093 class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16,
2094 MSA128HOpnd, GPR32Opnd>;
2095 class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32,
2096 MSA128WOpnd, GPR32Opnd>;
2097 class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64,
2098 MSA128DOpnd, GPR64Opnd>;
2100 class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W,
2102 class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D,
2105 class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>;
2106 class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>;
2108 class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>;
2109 class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>;
2111 class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>;
2112 class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>;
2114 class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w,
2116 class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d,
2119 class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>;
2120 class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>;
2122 class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w,
2124 class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d,
2127 class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", fms, MSA128WOpnd>;
2128 class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", fms, MSA128DOpnd>;
2130 class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>;
2131 class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>;
2133 class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>;
2134 class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>;
2136 class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>;
2137 class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>;
2139 class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w,
2141 class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d,
2144 class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>;
2145 class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>;
2147 class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>;
2148 class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>;
2150 class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>;
2151 class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>;
2153 class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>;
2154 class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>;
2156 class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>;
2157 class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>;
2159 class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>;
2160 class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>;
2162 class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>;
2163 class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>;
2165 class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>;
2166 class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>;
2168 class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w,
2170 class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d,
2173 class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w,
2175 class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d,
2178 class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w,
2180 class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d,
2183 class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w,
2185 class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d,
2188 class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w,
2190 class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d,
2193 class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w,
2195 class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d,
2198 class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w,
2200 class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d,
2203 class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h,
2204 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2205 class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w,
2206 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2208 class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint,
2210 class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint,
2213 class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint,
2215 class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint,
2218 class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h,
2219 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2220 class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w,
2221 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2222 class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d,
2223 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2225 class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h,
2226 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2227 class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w,
2228 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2229 class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d,
2230 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2232 class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h,
2233 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2234 class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w,
2235 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2236 class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d,
2237 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2239 class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h,
2240 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2241 class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w,
2242 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2243 class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d,
2244 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2246 class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>;
2247 class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>;
2248 class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>;
2249 class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>;
2251 class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>;
2252 class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>;
2253 class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>;
2254 class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>;
2256 class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>;
2257 class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>;
2258 class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>;
2259 class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>;
2261 class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>;
2262 class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>;
2263 class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>;
2264 class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>;
2266 class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8,
2267 MSA128BOpnd, GPR32Opnd>;
2268 class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16,
2269 MSA128HOpnd, GPR32Opnd>;
2270 class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32,
2271 MSA128WOpnd, GPR32Opnd>;
2273 class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32,
2274 MSA128WOpnd, FGR32Opnd>;
2275 class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64,
2276 MSA128DOpnd, FGR64Opnd>;
2278 class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", int_mips_insve_b,
2280 class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", int_mips_insve_h,
2282 class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", int_mips_insve_w,
2284 class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", int_mips_insve_d,
2287 class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2288 ValueType TyNode, RegisterOperand ROWD,
2289 Operand MemOpnd = mem_msa, ComplexPattern Addr = addrRegImm,
2290 InstrItinClass itin = NoItinerary> {
2291 dag OutOperandList = (outs ROWD:$wd);
2292 dag InOperandList = (ins MemOpnd:$addr);
2293 string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2294 list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))];
2295 InstrItinClass Itinerary = itin;
2296 string DecoderMethod = "DecodeMSA128Mem";
2299 class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd>;
2300 class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd>;
2301 class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd>;
2302 class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd>;
2304 class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>;
2305 class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>;
2306 class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>;
2307 class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>;
2310 dag OutOperandList = (outs GPR32Opnd:$rd);
2311 dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, LSAImm:$sa);
2312 string AsmString = "lsa\t$rd, $rs, $rt, $sa";
2313 list<dag> Pattern = [(set GPR32Opnd:$rd, (add GPR32Opnd:$rt,
2315 immZExt2Lsa:$sa)))];
2316 InstrItinClass Itinerary = NoItinerary;
2319 class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h,
2321 class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w,
2324 class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h,
2326 class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w,
2329 class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>;
2330 class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>;
2331 class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>;
2332 class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>;
2334 class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>;
2335 class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>;
2336 class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>;
2337 class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>;
2339 class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", MipsVSMax, MSA128BOpnd>;
2340 class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", MipsVSMax, MSA128HOpnd>;
2341 class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", MipsVSMax, MSA128WOpnd>;
2342 class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", MipsVSMax, MSA128DOpnd>;
2344 class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", MipsVUMax, MSA128BOpnd>;
2345 class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", MipsVUMax, MSA128HOpnd>;
2346 class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", MipsVUMax, MSA128WOpnd>;
2347 class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", MipsVUMax, MSA128DOpnd>;
2349 class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", MipsVSMax, vsplati8_simm5,
2351 class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", MipsVSMax, vsplati16_simm5,
2353 class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", MipsVSMax, vsplati32_simm5,
2355 class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", MipsVSMax, vsplati64_simm5,
2358 class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", MipsVUMax, vsplati8_uimm5,
2360 class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", MipsVUMax, vsplati16_uimm5,
2362 class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", MipsVUMax, vsplati32_uimm5,
2364 class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", MipsVUMax, vsplati64_uimm5,
2367 class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>;
2368 class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>;
2369 class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>;
2370 class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>;
2372 class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", MipsVSMin, MSA128BOpnd>;
2373 class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", MipsVSMin, MSA128HOpnd>;
2374 class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", MipsVSMin, MSA128WOpnd>;
2375 class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", MipsVSMin, MSA128DOpnd>;
2377 class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", MipsVUMin, MSA128BOpnd>;
2378 class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", MipsVUMin, MSA128HOpnd>;
2379 class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", MipsVUMin, MSA128WOpnd>;
2380 class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", MipsVUMin, MSA128DOpnd>;
2382 class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", MipsVSMin, vsplati8_simm5,
2384 class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", MipsVSMin, vsplati16_simm5,
2386 class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", MipsVSMin, vsplati32_simm5,
2388 class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", MipsVSMin, vsplati64_simm5,
2391 class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", MipsVUMin, vsplati8_uimm5,
2393 class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", MipsVUMin, vsplati16_uimm5,
2395 class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", MipsVUMin, vsplati32_uimm5,
2397 class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", MipsVUMin, vsplati64_uimm5,
2400 class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>;
2401 class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>;
2402 class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>;
2403 class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>;
2405 class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>;
2406 class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>;
2407 class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>;
2408 class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>;
2411 dag OutOperandList = (outs MSA128BOpnd:$wd);
2412 dag InOperandList = (ins MSA128BOpnd:$ws);
2413 string AsmString = "move.v\t$wd, $ws";
2414 list<dag> Pattern = [];
2415 InstrItinClass Itinerary = NoItinerary;
2418 class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h,
2420 class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w,
2423 class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h,
2425 class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w,
2428 class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>;
2429 class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>;
2430 class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>;
2431 class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>;
2433 class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h,
2435 class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w,
2438 class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h,
2440 class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w,
2443 class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>;
2444 class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>;
2445 class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>;
2446 class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>;
2448 class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>;
2449 class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>;
2450 class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>;
2451 class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>;
2453 class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>;
2454 class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>;
2455 class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>;
2456 class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>;
2458 class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>;
2459 class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>;
2460 class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>;
2461 class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>;
2463 class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8,
2466 class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>;
2467 class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>;
2468 class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>;
2469 class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>;
2471 class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>;
2473 class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>;
2474 class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>;
2475 class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>;
2476 class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>;
2478 class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>;
2479 class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>;
2480 class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>;
2481 class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>;
2483 class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>;
2484 class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>;
2485 class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>;
2486 class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>;
2488 class SAT_S_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b,
2490 class SAT_S_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h,
2492 class SAT_S_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w,
2494 class SAT_S_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d,
2497 class SAT_U_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b,
2499 class SAT_U_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h,
2501 class SAT_U_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w,
2503 class SAT_U_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d,
2506 class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>;
2507 class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>;
2508 class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>;
2510 class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>;
2511 class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>;
2512 class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>;
2513 class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>;
2515 class SLDI_B_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.b", int_mips_sldi_b,
2517 class SLDI_H_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.h", int_mips_sldi_h,
2519 class SLDI_W_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.w", int_mips_sldi_w,
2521 class SLDI_D_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.d", int_mips_sldi_d,
2524 class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>;
2525 class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>;
2526 class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>;
2527 class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>;
2529 class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3,
2531 class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4,
2533 class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5,
2535 class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6,
2538 class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt,
2540 class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt,
2542 class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt,
2544 class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt,
2547 class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4,
2549 class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3,
2551 class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2,
2553 class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1,
2556 class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>;
2557 class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>;
2558 class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>;
2559 class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>;
2561 class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3,
2563 class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4,
2565 class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5,
2567 class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6,
2570 class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>;
2571 class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>;
2572 class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>;
2573 class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>;
2575 class SRARI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srari.b", int_mips_srari_b,
2577 class SRARI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srari.h", int_mips_srari_h,
2579 class SRARI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srari.w", int_mips_srari_w,
2581 class SRARI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srari.d", int_mips_srari_d,
2584 class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>;
2585 class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>;
2586 class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>;
2587 class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>;
2589 class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3,
2591 class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4,
2593 class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5,
2595 class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6,
2598 class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>;
2599 class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>;
2600 class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>;
2601 class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>;
2603 class SRLRI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srlri.b", int_mips_srlri_b,
2605 class SRLRI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srlri.h", int_mips_srlri_h,
2607 class SRLRI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srlri.w", int_mips_srlri_w,
2609 class SRLRI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srlri.d", int_mips_srlri_d,
2612 class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2613 ValueType TyNode, RegisterOperand ROWD,
2614 Operand MemOpnd = mem_msa, ComplexPattern Addr = addrRegImm,
2615 InstrItinClass itin = NoItinerary> {
2616 dag OutOperandList = (outs);
2617 dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr);
2618 string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2619 list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)];
2620 InstrItinClass Itinerary = itin;
2621 string DecoderMethod = "DecodeMSA128Mem";
2624 class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd>;
2625 class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd>;
2626 class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd>;
2627 class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd>;
2629 class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b,
2631 class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h,
2633 class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w,
2635 class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d,
2638 class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b,
2640 class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h,
2642 class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w,
2644 class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d,
2647 class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b,
2649 class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h,
2651 class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w,
2653 class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d,
2656 class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b,
2658 class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h,
2660 class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w,
2662 class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d,
2665 class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>;
2666 class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>;
2667 class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>;
2668 class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>;
2670 class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5,
2672 class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5,
2674 class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5,
2676 class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5,
2679 class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>;
2680 class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>;
2681 class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>;
2682 class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>;
2684 class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>;
2685 class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>;
2686 class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>;
2687 class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>;
2689 class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8,
2692 // Instruction defs.
2693 def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC;
2694 def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC;
2695 def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC;
2696 def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC;
2698 def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC;
2699 def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC;
2700 def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC;
2701 def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC;
2703 def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC;
2704 def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC;
2705 def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC;
2706 def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC;
2708 def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC;
2709 def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC;
2710 def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC;
2711 def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC;
2713 def ADDV_B : ADDV_B_ENC, ADDV_B_DESC;
2714 def ADDV_H : ADDV_H_ENC, ADDV_H_DESC;
2715 def ADDV_W : ADDV_W_ENC, ADDV_W_DESC;
2716 def ADDV_D : ADDV_D_ENC, ADDV_D_DESC;
2718 def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC;
2719 def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC;
2720 def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC;
2721 def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC;
2723 def AND_V : AND_V_ENC, AND_V_DESC;
2724 def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC,
2725 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2728 def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC,
2729 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2732 def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC,
2733 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2737 def ANDI_B : ANDI_B_ENC, ANDI_B_DESC;
2739 def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC;
2740 def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC;
2741 def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC;
2742 def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC;
2744 def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC;
2745 def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC;
2746 def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC;
2747 def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC;
2749 def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC;
2750 def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC;
2751 def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC;
2752 def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC;
2754 def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC;
2755 def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC;
2756 def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC;
2757 def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC;
2759 def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC;
2760 def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC;
2761 def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC;
2762 def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC;
2764 def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC;
2765 def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC;
2766 def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC;
2767 def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC;
2769 def BCLR_B : BCLR_B_ENC, BCLR_B_DESC;
2770 def BCLR_H : BCLR_H_ENC, BCLR_H_DESC;
2771 def BCLR_W : BCLR_W_ENC, BCLR_W_DESC;
2772 def BCLR_D : BCLR_D_ENC, BCLR_D_DESC;
2774 def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC;
2775 def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC;
2776 def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC;
2777 def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC;
2779 def BINSL_B : BINSL_B_ENC, BINSL_B_DESC;
2780 def BINSL_H : BINSL_H_ENC, BINSL_H_DESC;
2781 def BINSL_W : BINSL_W_ENC, BINSL_W_DESC;
2782 def BINSL_D : BINSL_D_ENC, BINSL_D_DESC;
2784 def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC;
2785 def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC;
2786 def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC;
2787 def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC;
2789 def BINSR_B : BINSR_B_ENC, BINSR_B_DESC;
2790 def BINSR_H : BINSR_H_ENC, BINSR_H_DESC;
2791 def BINSR_W : BINSR_W_ENC, BINSR_W_DESC;
2792 def BINSR_D : BINSR_D_ENC, BINSR_D_DESC;
2794 def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC;
2795 def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC;
2796 def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC;
2797 def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC;
2799 def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC;
2801 def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC;
2803 def BMZ_V : BMZ_V_ENC, BMZ_V_DESC;
2805 def BMZI_B : BMZI_B_ENC, BMZI_B_DESC;
2807 def BNEG_B : BNEG_B_ENC, BNEG_B_DESC;
2808 def BNEG_H : BNEG_H_ENC, BNEG_H_DESC;
2809 def BNEG_W : BNEG_W_ENC, BNEG_W_DESC;
2810 def BNEG_D : BNEG_D_ENC, BNEG_D_DESC;
2812 def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC;
2813 def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC;
2814 def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC;
2815 def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC;
2817 def BNZ_B : BNZ_B_ENC, BNZ_B_DESC;
2818 def BNZ_H : BNZ_H_ENC, BNZ_H_DESC;
2819 def BNZ_W : BNZ_W_ENC, BNZ_W_DESC;
2820 def BNZ_D : BNZ_D_ENC, BNZ_D_DESC;
2822 def BNZ_V : BNZ_V_ENC, BNZ_V_DESC;
2824 def BSEL_V : BSEL_V_ENC, BSEL_V_DESC;
2826 class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> :
2827 MSAPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt),
2828 [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$ws, RO:$wt)))]>,
2829 PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in,
2830 MSA128BOpnd:$ws, MSA128BOpnd:$wt)> {
2831 let Constraints = "$wd_in = $wd";
2834 def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>;
2835 def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>;
2836 def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>;
2837 def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>;
2838 def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>;
2840 def BSELI_B : BSELI_B_ENC, BSELI_B_DESC;
2842 def BSET_B : BSET_B_ENC, BSET_B_DESC;
2843 def BSET_H : BSET_H_ENC, BSET_H_DESC;
2844 def BSET_W : BSET_W_ENC, BSET_W_DESC;
2845 def BSET_D : BSET_D_ENC, BSET_D_DESC;
2847 def BSETI_B : BSETI_B_ENC, BSETI_B_DESC;
2848 def BSETI_H : BSETI_H_ENC, BSETI_H_DESC;
2849 def BSETI_W : BSETI_W_ENC, BSETI_W_DESC;
2850 def BSETI_D : BSETI_D_ENC, BSETI_D_DESC;
2852 def BZ_B : BZ_B_ENC, BZ_B_DESC;
2853 def BZ_H : BZ_H_ENC, BZ_H_DESC;
2854 def BZ_W : BZ_W_ENC, BZ_W_DESC;
2855 def BZ_D : BZ_D_ENC, BZ_D_DESC;
2857 def BZ_V : BZ_V_ENC, BZ_V_DESC;
2859 def CEQ_B : CEQ_B_ENC, CEQ_B_DESC;
2860 def CEQ_H : CEQ_H_ENC, CEQ_H_DESC;
2861 def CEQ_W : CEQ_W_ENC, CEQ_W_DESC;
2862 def CEQ_D : CEQ_D_ENC, CEQ_D_DESC;
2864 def CEQI_B : CEQI_B_ENC, CEQI_B_DESC;
2865 def CEQI_H : CEQI_H_ENC, CEQI_H_DESC;
2866 def CEQI_W : CEQI_W_ENC, CEQI_W_DESC;
2867 def CEQI_D : CEQI_D_ENC, CEQI_D_DESC;
2869 def CFCMSA : CFCMSA_ENC, CFCMSA_DESC;
2871 def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC;
2872 def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC;
2873 def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC;
2874 def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC;
2876 def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC;
2877 def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC;
2878 def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC;
2879 def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC;
2881 def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC;
2882 def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC;
2883 def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC;
2884 def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC;
2886 def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC;
2887 def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC;
2888 def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC;
2889 def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC;
2891 def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC;
2892 def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC;
2893 def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC;
2894 def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC;
2896 def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC;
2897 def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC;
2898 def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC;
2899 def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC;
2901 def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC;
2902 def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC;
2903 def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC;
2904 def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC;
2906 def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC;
2907 def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC;
2908 def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC;
2909 def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC;
2911 def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC;
2912 def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC;
2913 def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC;
2914 def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC;
2916 def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC;
2917 def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC;
2918 def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC;
2919 def COPY_U_D : COPY_U_D_ENC, COPY_U_D_DESC;
2921 def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC;
2922 def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC;
2924 def CTCMSA : CTCMSA_ENC, CTCMSA_DESC;
2926 def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC;
2927 def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC;
2928 def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC;
2929 def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC;
2931 def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC;
2932 def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC;
2933 def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC;
2934 def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC;
2936 def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC;
2937 def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC;
2938 def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC;
2940 def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC;
2941 def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC;
2942 def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC;
2944 def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC;
2945 def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC;
2946 def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC;
2948 def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC;
2949 def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC;
2950 def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC;
2952 def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC;
2953 def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC;
2954 def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC;
2956 def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC;
2957 def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC;
2958 def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC;
2960 def FADD_W : FADD_W_ENC, FADD_W_DESC;
2961 def FADD_D : FADD_D_ENC, FADD_D_DESC;
2963 def FCAF_W : FCAF_W_ENC, FCAF_W_DESC;
2964 def FCAF_D : FCAF_D_ENC, FCAF_D_DESC;
2966 def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC;
2967 def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC;
2969 def FCLE_W : FCLE_W_ENC, FCLE_W_DESC;
2970 def FCLE_D : FCLE_D_ENC, FCLE_D_DESC;
2972 def FCLT_W : FCLT_W_ENC, FCLT_W_DESC;
2973 def FCLT_D : FCLT_D_ENC, FCLT_D_DESC;
2975 def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC;
2976 def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC;
2978 def FCNE_W : FCNE_W_ENC, FCNE_W_DESC;
2979 def FCNE_D : FCNE_D_ENC, FCNE_D_DESC;
2981 def FCOR_W : FCOR_W_ENC, FCOR_W_DESC;
2982 def FCOR_D : FCOR_D_ENC, FCOR_D_DESC;
2984 def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC;
2985 def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC;
2987 def FCULE_W : FCULE_W_ENC, FCULE_W_DESC;
2988 def FCULE_D : FCULE_D_ENC, FCULE_D_DESC;
2990 def FCULT_W : FCULT_W_ENC, FCULT_W_DESC;
2991 def FCULT_D : FCULT_D_ENC, FCULT_D_DESC;
2993 def FCUN_W : FCUN_W_ENC, FCUN_W_DESC;
2994 def FCUN_D : FCUN_D_ENC, FCUN_D_DESC;
2996 def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC;
2997 def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC;
2999 def FDIV_W : FDIV_W_ENC, FDIV_W_DESC;
3000 def FDIV_D : FDIV_D_ENC, FDIV_D_DESC;
3002 def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC;
3003 def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC;
3005 def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC;
3006 def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC;
3007 def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC;
3008 def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC;
3010 def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC;
3011 def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC;
3013 def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC;
3014 def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC;
3016 def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC;
3017 def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC;
3019 def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC;
3020 def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC;
3022 def FFQL_W : FFQL_W_ENC, FFQL_W_DESC;
3023 def FFQL_D : FFQL_D_ENC, FFQL_D_DESC;
3025 def FFQR_W : FFQR_W_ENC, FFQR_W_DESC;
3026 def FFQR_D : FFQR_D_ENC, FFQR_D_DESC;
3028 def FILL_B : FILL_B_ENC, FILL_B_DESC;
3029 def FILL_H : FILL_H_ENC, FILL_H_DESC;
3030 def FILL_W : FILL_W_ENC, FILL_W_DESC;
3031 def FILL_D : FILL_D_ENC, FILL_D_DESC;
3032 def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC;
3033 def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC;
3035 def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC;
3036 def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC;
3038 def FMADD_W : FMADD_W_ENC, FMADD_W_DESC;
3039 def FMADD_D : FMADD_D_ENC, FMADD_D_DESC;
3041 def FMAX_W : FMAX_W_ENC, FMAX_W_DESC;
3042 def FMAX_D : FMAX_D_ENC, FMAX_D_DESC;
3044 def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC;
3045 def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC;
3047 def FMIN_W : FMIN_W_ENC, FMIN_W_DESC;
3048 def FMIN_D : FMIN_D_ENC, FMIN_D_DESC;
3050 def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC;
3051 def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC;
3053 def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC;
3054 def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC;
3056 def FMUL_W : FMUL_W_ENC, FMUL_W_DESC;
3057 def FMUL_D : FMUL_D_ENC, FMUL_D_DESC;
3059 def FRINT_W : FRINT_W_ENC, FRINT_W_DESC;
3060 def FRINT_D : FRINT_D_ENC, FRINT_D_DESC;
3062 def FRCP_W : FRCP_W_ENC, FRCP_W_DESC;
3063 def FRCP_D : FRCP_D_ENC, FRCP_D_DESC;
3065 def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC;
3066 def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC;
3068 def FSAF_W : FSAF_W_ENC, FSAF_W_DESC;
3069 def FSAF_D : FSAF_D_ENC, FSAF_D_DESC;
3071 def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC;
3072 def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC;
3074 def FSLE_W : FSLE_W_ENC, FSLE_W_DESC;
3075 def FSLE_D : FSLE_D_ENC, FSLE_D_DESC;
3077 def FSLT_W : FSLT_W_ENC, FSLT_W_DESC;
3078 def FSLT_D : FSLT_D_ENC, FSLT_D_DESC;
3080 def FSNE_W : FSNE_W_ENC, FSNE_W_DESC;
3081 def FSNE_D : FSNE_D_ENC, FSNE_D_DESC;
3083 def FSOR_W : FSOR_W_ENC, FSOR_W_DESC;
3084 def FSOR_D : FSOR_D_ENC, FSOR_D_DESC;
3086 def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC;
3087 def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC;
3089 def FSUB_W : FSUB_W_ENC, FSUB_W_DESC;
3090 def FSUB_D : FSUB_D_ENC, FSUB_D_DESC;
3092 def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC;
3093 def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC;
3095 def FSULE_W : FSULE_W_ENC, FSULE_W_DESC;
3096 def FSULE_D : FSULE_D_ENC, FSULE_D_DESC;
3098 def FSULT_W : FSULT_W_ENC, FSULT_W_DESC;
3099 def FSULT_D : FSULT_D_ENC, FSULT_D_DESC;
3101 def FSUN_W : FSUN_W_ENC, FSUN_W_DESC;
3102 def FSUN_D : FSUN_D_ENC, FSUN_D_DESC;
3104 def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC;
3105 def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC;
3107 def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC;
3108 def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC;
3110 def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC;
3111 def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC;
3113 def FTQ_H : FTQ_H_ENC, FTQ_H_DESC;
3114 def FTQ_W : FTQ_W_ENC, FTQ_W_DESC;
3116 def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC;
3117 def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC;
3119 def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC;
3120 def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC;
3122 def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC;
3123 def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC;
3124 def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC;
3126 def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC;
3127 def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC;
3128 def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC;
3130 def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC;
3131 def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC;
3132 def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC;
3134 def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC;
3135 def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC;
3136 def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC;
3138 def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC;
3139 def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC;
3140 def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC;
3141 def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC;
3143 def ILVL_B : ILVL_B_ENC, ILVL_B_DESC;
3144 def ILVL_H : ILVL_H_ENC, ILVL_H_DESC;
3145 def ILVL_W : ILVL_W_ENC, ILVL_W_DESC;
3146 def ILVL_D : ILVL_D_ENC, ILVL_D_DESC;
3148 def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC;
3149 def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC;
3150 def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC;
3151 def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC;
3153 def ILVR_B : ILVR_B_ENC, ILVR_B_DESC;
3154 def ILVR_H : ILVR_H_ENC, ILVR_H_DESC;
3155 def ILVR_W : ILVR_W_ENC, ILVR_W_DESC;
3156 def ILVR_D : ILVR_D_ENC, ILVR_D_DESC;
3158 def INSERT_B : INSERT_B_ENC, INSERT_B_DESC;
3159 def INSERT_H : INSERT_H_ENC, INSERT_H_DESC;
3160 def INSERT_W : INSERT_W_ENC, INSERT_W_DESC;
3162 // INSERT_FW_PSEUDO defined after INSVE_W
3163 // INSERT_FD_PSEUDO defined after INSVE_D
3165 def INSVE_B : INSVE_B_ENC, INSVE_B_DESC;
3166 def INSVE_H : INSVE_H_ENC, INSVE_H_DESC;
3167 def INSVE_W : INSVE_W_ENC, INSVE_W_DESC;
3168 def INSVE_D : INSVE_D_ENC, INSVE_D_DESC;
3170 def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC;
3171 def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC;
3173 def LD_B: LD_B_ENC, LD_B_DESC;
3174 def LD_H: LD_H_ENC, LD_H_DESC;
3175 def LD_W: LD_W_ENC, LD_W_DESC;
3176 def LD_D: LD_D_ENC, LD_D_DESC;
3178 def LDI_B : LDI_B_ENC, LDI_B_DESC;
3179 def LDI_H : LDI_H_ENC, LDI_H_DESC;
3180 def LDI_W : LDI_W_ENC, LDI_W_DESC;
3181 def LDI_D : LDI_D_ENC, LDI_D_DESC;
3183 def LSA : LSA_ENC, LSA_DESC;
3185 def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC;
3186 def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC;
3188 def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC;
3189 def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC;
3191 def MADDV_B : MADDV_B_ENC, MADDV_B_DESC;
3192 def MADDV_H : MADDV_H_ENC, MADDV_H_DESC;
3193 def MADDV_W : MADDV_W_ENC, MADDV_W_DESC;
3194 def MADDV_D : MADDV_D_ENC, MADDV_D_DESC;
3196 def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC;
3197 def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC;
3198 def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC;
3199 def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC;
3201 def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC;
3202 def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC;
3203 def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC;
3204 def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC;
3206 def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC;
3207 def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC;
3208 def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC;
3209 def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC;
3211 def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC;
3212 def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC;
3213 def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC;
3214 def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC;
3216 def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC;
3217 def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC;
3218 def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC;
3219 def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC;
3221 def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC;
3222 def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC;
3223 def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC;
3224 def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC;
3226 def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC;
3227 def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC;
3228 def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC;
3229 def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC;
3231 def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC;
3232 def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC;
3233 def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC;
3234 def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC;
3236 def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC;
3237 def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC;
3238 def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC;
3239 def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC;
3241 def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC;
3242 def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC;
3243 def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC;
3244 def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC;
3246 def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC;
3247 def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC;
3248 def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC;
3249 def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC;
3251 def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC;
3252 def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC;
3253 def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC;
3254 def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC;
3256 def MOVE_V : MOVE_V_ENC, MOVE_V_DESC;
3258 def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC;
3259 def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC;
3261 def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC;
3262 def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC;
3264 def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC;
3265 def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC;
3266 def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC;
3267 def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC;
3269 def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC;
3270 def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC;
3272 def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC;
3273 def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC;
3275 def MULV_B : MULV_B_ENC, MULV_B_DESC;
3276 def MULV_H : MULV_H_ENC, MULV_H_DESC;
3277 def MULV_W : MULV_W_ENC, MULV_W_DESC;
3278 def MULV_D : MULV_D_ENC, MULV_D_DESC;
3280 def NLOC_B : NLOC_B_ENC, NLOC_B_DESC;
3281 def NLOC_H : NLOC_H_ENC, NLOC_H_DESC;
3282 def NLOC_W : NLOC_W_ENC, NLOC_W_DESC;
3283 def NLOC_D : NLOC_D_ENC, NLOC_D_DESC;
3285 def NLZC_B : NLZC_B_ENC, NLZC_B_DESC;
3286 def NLZC_H : NLZC_H_ENC, NLZC_H_DESC;
3287 def NLZC_W : NLZC_W_ENC, NLZC_W_DESC;
3288 def NLZC_D : NLZC_D_ENC, NLZC_D_DESC;
3290 def NOR_V : NOR_V_ENC, NOR_V_DESC;
3291 def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC,
3292 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3295 def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC,
3296 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3299 def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC,
3300 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3304 def NORI_B : NORI_B_ENC, NORI_B_DESC;
3306 def OR_V : OR_V_ENC, OR_V_DESC;
3307 def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC,
3308 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3311 def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC,
3312 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3315 def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC,
3316 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3320 def ORI_B : ORI_B_ENC, ORI_B_DESC;
3322 def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC;
3323 def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC;
3324 def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC;
3325 def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC;
3327 def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC;
3328 def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC;
3329 def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC;
3330 def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC;
3332 def PCNT_B : PCNT_B_ENC, PCNT_B_DESC;
3333 def PCNT_H : PCNT_H_ENC, PCNT_H_DESC;
3334 def PCNT_W : PCNT_W_ENC, PCNT_W_DESC;
3335 def PCNT_D : PCNT_D_ENC, PCNT_D_DESC;
3337 def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC;
3338 def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC;
3339 def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC;
3340 def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC;
3342 def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC;
3343 def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC;
3344 def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC;
3345 def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC;
3347 def SHF_B : SHF_B_ENC, SHF_B_DESC;
3348 def SHF_H : SHF_H_ENC, SHF_H_DESC;
3349 def SHF_W : SHF_W_ENC, SHF_W_DESC;
3351 def SLD_B : SLD_B_ENC, SLD_B_DESC;
3352 def SLD_H : SLD_H_ENC, SLD_H_DESC;
3353 def SLD_W : SLD_W_ENC, SLD_W_DESC;
3354 def SLD_D : SLD_D_ENC, SLD_D_DESC;
3356 def SLDI_B : SLDI_B_ENC, SLDI_B_DESC;
3357 def SLDI_H : SLDI_H_ENC, SLDI_H_DESC;
3358 def SLDI_W : SLDI_W_ENC, SLDI_W_DESC;
3359 def SLDI_D : SLDI_D_ENC, SLDI_D_DESC;
3361 def SLL_B : SLL_B_ENC, SLL_B_DESC;
3362 def SLL_H : SLL_H_ENC, SLL_H_DESC;
3363 def SLL_W : SLL_W_ENC, SLL_W_DESC;
3364 def SLL_D : SLL_D_ENC, SLL_D_DESC;
3366 def SLLI_B : SLLI_B_ENC, SLLI_B_DESC;
3367 def SLLI_H : SLLI_H_ENC, SLLI_H_DESC;
3368 def SLLI_W : SLLI_W_ENC, SLLI_W_DESC;
3369 def SLLI_D : SLLI_D_ENC, SLLI_D_DESC;
3371 def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC;
3372 def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC;
3373 def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC;
3374 def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC;
3376 def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC;
3377 def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC;
3378 def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC;
3379 def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC;
3381 def SRA_B : SRA_B_ENC, SRA_B_DESC;
3382 def SRA_H : SRA_H_ENC, SRA_H_DESC;
3383 def SRA_W : SRA_W_ENC, SRA_W_DESC;
3384 def SRA_D : SRA_D_ENC, SRA_D_DESC;
3386 def SRAI_B : SRAI_B_ENC, SRAI_B_DESC;
3387 def SRAI_H : SRAI_H_ENC, SRAI_H_DESC;
3388 def SRAI_W : SRAI_W_ENC, SRAI_W_DESC;
3389 def SRAI_D : SRAI_D_ENC, SRAI_D_DESC;
3391 def SRAR_B : SRAR_B_ENC, SRAR_B_DESC;
3392 def SRAR_H : SRAR_H_ENC, SRAR_H_DESC;
3393 def SRAR_W : SRAR_W_ENC, SRAR_W_DESC;
3394 def SRAR_D : SRAR_D_ENC, SRAR_D_DESC;
3396 def SRARI_B : SRARI_B_ENC, SRARI_B_DESC;
3397 def SRARI_H : SRARI_H_ENC, SRARI_H_DESC;
3398 def SRARI_W : SRARI_W_ENC, SRARI_W_DESC;
3399 def SRARI_D : SRARI_D_ENC, SRARI_D_DESC;
3401 def SRL_B : SRL_B_ENC, SRL_B_DESC;
3402 def SRL_H : SRL_H_ENC, SRL_H_DESC;
3403 def SRL_W : SRL_W_ENC, SRL_W_DESC;
3404 def SRL_D : SRL_D_ENC, SRL_D_DESC;
3406 def SRLI_B : SRLI_B_ENC, SRLI_B_DESC;
3407 def SRLI_H : SRLI_H_ENC, SRLI_H_DESC;
3408 def SRLI_W : SRLI_W_ENC, SRLI_W_DESC;
3409 def SRLI_D : SRLI_D_ENC, SRLI_D_DESC;
3411 def SRLR_B : SRLR_B_ENC, SRLR_B_DESC;
3412 def SRLR_H : SRLR_H_ENC, SRLR_H_DESC;
3413 def SRLR_W : SRLR_W_ENC, SRLR_W_DESC;
3414 def SRLR_D : SRLR_D_ENC, SRLR_D_DESC;
3416 def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC;
3417 def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC;
3418 def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC;
3419 def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC;
3421 def ST_B: ST_B_ENC, ST_B_DESC;
3422 def ST_H: ST_H_ENC, ST_H_DESC;
3423 def ST_W: ST_W_ENC, ST_W_DESC;
3424 def ST_D: ST_D_ENC, ST_D_DESC;
3426 def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC;
3427 def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC;
3428 def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC;
3429 def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC;
3431 def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC;
3432 def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC;
3433 def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC;
3434 def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC;
3436 def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC;
3437 def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC;
3438 def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC;
3439 def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC;
3441 def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC;
3442 def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC;
3443 def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC;
3444 def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC;
3446 def SUBV_B : SUBV_B_ENC, SUBV_B_DESC;
3447 def SUBV_H : SUBV_H_ENC, SUBV_H_DESC;
3448 def SUBV_W : SUBV_W_ENC, SUBV_W_DESC;
3449 def SUBV_D : SUBV_D_ENC, SUBV_D_DESC;
3451 def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC;
3452 def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC;
3453 def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC;
3454 def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC;
3456 def VSHF_B : VSHF_B_ENC, VSHF_B_DESC;
3457 def VSHF_H : VSHF_H_ENC, VSHF_H_DESC;
3458 def VSHF_W : VSHF_W_ENC, VSHF_W_DESC;
3459 def VSHF_D : VSHF_D_ENC, VSHF_D_DESC;
3461 def XOR_V : XOR_V_ENC, XOR_V_DESC;
3462 def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC,
3463 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3466 def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC,
3467 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3470 def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC,
3471 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3475 def XORI_B : XORI_B_ENC, XORI_B_DESC;
3478 class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> :
3479 Pat<pattern, result>, Requires<pred>;
3481 def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx),
3482 (COPY_S_W MSA128W:$ws, immZExt4:$idx)>;
3484 def : MSAPat<(v16i8 (load addr:$addr)), (LD_B addr:$addr)>;
3485 def : MSAPat<(v8i16 (load addr:$addr)), (LD_H addr:$addr)>;
3486 def : MSAPat<(v4i32 (load addr:$addr)), (LD_W addr:$addr)>;
3487 def : MSAPat<(v2i64 (load addr:$addr)), (LD_D addr:$addr)>;
3488 def : MSAPat<(v8f16 (load addr:$addr)), (LD_H addr:$addr)>;
3489 def : MSAPat<(v4f32 (load addr:$addr)), (LD_W addr:$addr)>;
3490 def : MSAPat<(v2f64 (load addr:$addr)), (LD_D addr:$addr)>;
3492 def : MSAPat<(v8f16 (load addrRegImm:$addr)), (LD_H addrRegImm:$addr)>;
3493 def : MSAPat<(v4f32 (load addrRegImm:$addr)), (LD_W addrRegImm:$addr)>;
3494 def : MSAPat<(v2f64 (load addrRegImm:$addr)), (LD_D addrRegImm:$addr)>;
3496 def : MSAPat<(store (v16i8 MSA128B:$ws), addr:$addr),
3497 (ST_B MSA128B:$ws, addr:$addr)>;
3498 def : MSAPat<(store (v8i16 MSA128H:$ws), addr:$addr),
3499 (ST_H MSA128H:$ws, addr:$addr)>;
3500 def : MSAPat<(store (v4i32 MSA128W:$ws), addr:$addr),
3501 (ST_W MSA128W:$ws, addr:$addr)>;
3502 def : MSAPat<(store (v2i64 MSA128D:$ws), addr:$addr),
3503 (ST_D MSA128D:$ws, addr:$addr)>;
3504 def : MSAPat<(store (v8f16 MSA128H:$ws), addr:$addr),
3505 (ST_H MSA128H:$ws, addr:$addr)>;
3506 def : MSAPat<(store (v4f32 MSA128W:$ws), addr:$addr),
3507 (ST_W MSA128W:$ws, addr:$addr)>;
3508 def : MSAPat<(store (v2f64 MSA128D:$ws), addr:$addr),
3509 (ST_D MSA128D:$ws, addr:$addr)>;
3511 def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrRegImm:$addr),
3512 (ST_H MSA128H:$ws, addrRegImm:$addr)>;
3513 def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrRegImm:$addr),
3514 (ST_W MSA128W:$ws, addrRegImm:$addr)>;
3515 def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrRegImm:$addr),
3516 (ST_D MSA128D:$ws, addrRegImm:$addr)>;
3518 class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD,
3519 RegisterOperand ROWS = ROWD,
3520 InstrItinClass itin = NoItinerary> :
3521 MSAPseudo<(outs ROWD:$wd),
3523 [(set ROWD:$wd, (fabs ROWS:$ws))]> {
3524 InstrItinClass Itinerary = itin;
3526 def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>,
3527 PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws,
3529 def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>,
3530 PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws,
3533 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3534 RegisterClass DstRC, list<Predicate> preds = [HasMSA]> :
3535 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3536 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3538 // These are endian-independent because the element size doesnt change
3539 def : MSABitconvertPat<v8i16, v8f16, MSA128H>;
3540 def : MSABitconvertPat<v4i32, v4f32, MSA128W>;
3541 def : MSABitconvertPat<v2i64, v2f64, MSA128D>;
3542 def : MSABitconvertPat<v8f16, v8i16, MSA128H>;
3543 def : MSABitconvertPat<v4f32, v4i32, MSA128W>;
3544 def : MSABitconvertPat<v2f64, v2i64, MSA128D>;
3546 // Little endian bitcasts are always no-ops
3547 def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>;
3548 def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>;
3549 def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>;
3550 def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>;
3551 def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>;
3552 def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>;
3554 def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>;
3555 def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>;
3556 def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>;
3557 def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>;
3558 def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>;
3560 def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>;
3561 def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>;
3562 def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>;
3563 def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>;
3564 def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>;
3566 def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>;
3567 def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>;
3568 def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>;
3569 def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>;
3570 def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>;
3572 def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>;
3573 def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>;
3574 def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>;
3575 def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>;
3576 def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>;
3578 def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>;
3579 def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>;
3580 def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>;
3581 def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>;
3582 def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>;
3584 // Big endian bitcasts expand to shuffle instructions.
3585 // This is because bitcast is defined to be a store/load sequence and the
3586 // vector store/load instructions are mixed-endian with respect to the vector
3587 // as a whole (little endian with respect to element order, but big endian
3590 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3591 RegisterClass DstRC, MSAInst Insn,
3592 RegisterClass ViaRC> :
3593 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3594 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3598 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3599 RegisterClass DstRC, MSAInst Insn,
3600 RegisterClass ViaRC> :
3601 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3602 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3606 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3607 RegisterClass DstRC> :
3608 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3610 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3611 RegisterClass DstRC> :
3612 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3614 class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT,
3615 RegisterClass DstRC> :
3616 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3620 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27),
3625 class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT,
3626 RegisterClass DstRC> :
3627 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3629 class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT,
3630 RegisterClass DstRC> :
3631 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3633 class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT,
3634 RegisterClass DstRC> :
3635 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>;
3637 def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>;
3638 def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>;
3639 def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>;
3640 def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>;
3641 def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>;
3642 def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>;
3644 def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>;
3645 def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>;
3646 def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>;
3647 def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>;
3648 def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>;
3650 def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>;
3651 def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>;
3652 def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>;
3653 def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>;
3654 def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>;
3656 def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>;
3657 def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>;
3658 def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>;
3659 def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>;
3660 def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>;
3662 def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>;
3663 def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>;
3664 def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>;
3665 def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>;
3666 def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>;
3668 def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>;
3669 def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>;
3670 def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>;
3671 def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>;
3672 def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>;
3674 def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>;
3675 def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>;
3676 def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>;
3677 def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>;
3678 def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>;
3680 // Pseudos used to implement BNZ.df, and BZ.df
3682 class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode,
3684 InstrItinClass itin = NoItinerary> :
3685 MipsPseudo<(outs GPR32:$dst),
3687 [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> {
3688 bit usesCustomInserter = 1;
3691 def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8,
3692 MSA128B, NoItinerary>;
3693 def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16,
3694 MSA128H, NoItinerary>;
3695 def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32,
3696 MSA128W, NoItinerary>;
3697 def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64,
3698 MSA128D, NoItinerary>;
3699 def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8,
3700 MSA128B, NoItinerary>;
3702 def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8,
3703 MSA128B, NoItinerary>;
3704 def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16,
3705 MSA128H, NoItinerary>;
3706 def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32,
3707 MSA128W, NoItinerary>;
3708 def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64,
3709 MSA128D, NoItinerary>;
3710 def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8,
3711 MSA128B, NoItinerary>;