1 //===-- MipsOptionRecord.h - Abstraction for storing information ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // MipsOptionRecord - Abstraction for storing arbitrary information in
11 // ELF files. Arbitrary information (e.g. register usage) can be stored in Mips
12 // specific ELF sections like .Mips.options. Specific records should subclass
13 // MipsOptionRecord and provide an implementation to EmitMipsOptionRecord which
14 // basically just dumps the information into an ELF section. More information
15 // about .Mips.option can be found in the SysV ABI and the 64-bit ELF Object
18 //===----------------------------------------------------------------------===//
20 #ifndef LLVM_LIB_TARGET_MIPS_MIPSOPTIONRECORD_H
21 #define LLVM_LIB_TARGET_MIPS_MIPSOPTIONRECORD_H
23 #include "MCTargetDesc/MipsMCTargetDesc.h"
24 #include "llvm/MC/MCContext.h"
25 #include "llvm/MC/MCRegisterInfo.h"
30 class MipsELFStreamer;
31 class MCSubtargetInfo;
34 class MipsOptionRecord {
36 virtual ~MipsOptionRecord(){};
37 virtual void EmitMipsOptionRecord() = 0;
40 class MipsRegInfoRecord : public MipsOptionRecord {
42 MipsRegInfoRecord(MipsELFStreamer *S, MCContext &Context,
43 const MCSubtargetInfo &STI)
44 : Streamer(S), Context(Context), STI(STI) {
46 ri_cprmask[0] = ri_cprmask[1] = ri_cprmask[2] = ri_cprmask[3] = 0;
49 const MCRegisterInfo *TRI = Context.getRegisterInfo();
50 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID));
51 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID));
52 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID));
53 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID));
54 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID));
55 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID));
56 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID));
57 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID));
59 ~MipsRegInfoRecord() {}
61 void EmitMipsOptionRecord();
62 void SetPhysRegUsed(unsigned Reg, const MCRegisterInfo *MCRegInfo);
65 MipsELFStreamer *Streamer;
67 const MCSubtargetInfo &STI;
68 const MCRegisterClass *GPR32RegClass;
69 const MCRegisterClass *GPR64RegClass;
70 const MCRegisterClass *FGR32RegClass;
71 const MCRegisterClass *FGR64RegClass;
72 const MCRegisterClass *AFGR64RegClass;
73 const MCRegisterClass *MSA128BRegClass;
74 const MCRegisterClass *COP2RegClass;
75 const MCRegisterClass *COP3RegClass;
77 uint32_t ri_cprmask[4];