1 //===-- MipsOptionRecord.h - Abstraction for storing information ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // MipsOptionRecord - Abstraction for storing arbitrary information in
11 // ELF files. Arbitrary information (e.g. register usage) can be stored in Mips
12 // specific ELF sections like .Mips.options. Specific records should subclass
13 // MipsOptionRecord and provide an implementation to EmitMipsOptionRecord which
14 // basically just dumps the information into an ELF section. More information
15 // about .Mips.option can be found in the SysV ABI and the 64-bit ELF Object
18 //===----------------------------------------------------------------------===//
20 #ifndef LLVM_LIB_TARGET_MIPS_MIPSOPTIONRECORD_H
21 #define LLVM_LIB_TARGET_MIPS_MIPSOPTIONRECORD_H
23 #include "MCTargetDesc/MipsMCTargetDesc.h"
24 #include "llvm/MC/MCContext.h"
25 #include "llvm/MC/MCRegisterInfo.h"
28 class MipsELFStreamer;
29 class MCSubtargetInfo;
31 class MipsOptionRecord {
33 virtual ~MipsOptionRecord(){};
34 virtual void EmitMipsOptionRecord() = 0;
37 class MipsRegInfoRecord : public MipsOptionRecord {
39 MipsRegInfoRecord(MipsELFStreamer *S, MCContext &Context)
40 : Streamer(S), Context(Context) {
42 ri_cprmask[0] = ri_cprmask[1] = ri_cprmask[2] = ri_cprmask[3] = 0;
45 const MCRegisterInfo *TRI = Context.getRegisterInfo();
46 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID));
47 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID));
48 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID));
49 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID));
50 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID));
51 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID));
52 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID));
53 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID));
55 ~MipsRegInfoRecord() {}
57 void EmitMipsOptionRecord() override;
58 void SetPhysRegUsed(unsigned Reg, const MCRegisterInfo *MCRegInfo);
61 MipsELFStreamer *Streamer;
63 const MCRegisterClass *GPR32RegClass;
64 const MCRegisterClass *GPR64RegClass;
65 const MCRegisterClass *FGR32RegClass;
66 const MCRegisterClass *FGR64RegClass;
67 const MCRegisterClass *AFGR64RegClass;
68 const MCRegisterClass *MSA128BRegClass;
69 const MCRegisterClass *COP2RegClass;
70 const MCRegisterClass *COP3RegClass;
72 uint32_t ri_cprmask[4];