1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-reg-info"
16 #include "MipsRegisterInfo.h"
18 #include "MipsAnalyzeImmediate.h"
19 #include "MipsInstrInfo.h"
20 #include "MipsMachineFunction.h"
21 #include "MipsSubtarget.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/ValueTypes.h"
28 #include "llvm/DebugInfo.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameLowering.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
40 #define GET_REGINFO_TARGET_DESC
41 #include "MipsGenRegisterInfo.inc"
45 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST)
46 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {}
48 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
50 const TargetRegisterClass *
51 MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
52 unsigned Kind) const {
53 return Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
57 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
58 MachineFunction &MF) const {
59 switch (RC->getID()) {
62 case Mips::GPR32RegClassID:
63 case Mips::GPR64RegClassID:
64 case Mips::DSPRRegClassID: {
65 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
66 return 28 - TFI->hasFP(MF);
68 case Mips::FGR32RegClassID:
70 case Mips::AFGR64RegClassID:
72 case Mips::FGR64RegClassID:
77 //===----------------------------------------------------------------------===//
78 // Callee Saved Registers methods
79 //===----------------------------------------------------------------------===//
81 /// Mips Callee Saved Registers
82 const uint16_t* MipsRegisterInfo::
83 getCalleeSavedRegs(const MachineFunction *MF) const {
84 if (Subtarget.isSingleFloat())
85 return CSR_SingleFloatOnly_SaveList;
87 if (Subtarget.isABI_N64())
88 return CSR_N64_SaveList;
90 if (Subtarget.isABI_N32())
91 return CSR_N32_SaveList;
93 if (Subtarget.isFP64bit())
94 return CSR_O32_FP64_SaveList;
96 return CSR_O32_SaveList;
100 MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
101 if (Subtarget.isSingleFloat())
102 return CSR_SingleFloatOnly_RegMask;
104 if (Subtarget.isABI_N64())
105 return CSR_N64_RegMask;
107 if (Subtarget.isABI_N32())
108 return CSR_N32_RegMask;
110 if (Subtarget.isFP64bit())
111 return CSR_O32_FP64_RegMask;
113 return CSR_O32_RegMask;
116 const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
117 return CSR_Mips16RetHelper_RegMask;
120 BitVector MipsRegisterInfo::
121 getReservedRegs(const MachineFunction &MF) const {
122 static const uint16_t ReservedGPR32[] = {
123 Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
126 static const uint16_t ReservedGPR64[] = {
127 Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
130 BitVector Reserved(getNumRegs());
131 typedef TargetRegisterClass::const_iterator RegIter;
133 for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
134 Reserved.set(ReservedGPR32[I]);
136 for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
137 Reserved.set(ReservedGPR64[I]);
139 if (Subtarget.isFP64bit()) {
140 // Reserve all registers in AFGR64.
141 for (RegIter Reg = Mips::AFGR64RegClass.begin(),
142 EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
145 // Reserve all registers in FGR64.
146 for (RegIter Reg = Mips::FGR64RegClass.begin(),
147 EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
150 // Reserve FP if this function should have a dedicated frame pointer register.
151 if (MF.getTarget().getFrameLowering()->hasFP(MF)) {
152 if (Subtarget.inMips16Mode())
153 Reserved.set(Mips::S0);
155 Reserved.set(Mips::FP);
156 Reserved.set(Mips::FP_64);
160 // Reserve hardware registers.
161 Reserved.set(Mips::HWR29);
163 // Reserve DSP control register.
164 Reserved.set(Mips::DSPPos);
165 Reserved.set(Mips::DSPSCount);
166 Reserved.set(Mips::DSPCarry);
167 Reserved.set(Mips::DSPEFI);
168 Reserved.set(Mips::DSPOutFlag);
170 // Reserve RA if in mips16 mode.
171 if (Subtarget.inMips16Mode()) {
172 Reserved.set(Mips::RA);
173 Reserved.set(Mips::RA_64);
174 Reserved.set(Mips::T0);
175 Reserved.set(Mips::T1);
178 // Reserve GP if small section is used.
179 if (Subtarget.useSmallSection()) {
180 Reserved.set(Mips::GP);
181 Reserved.set(Mips::GP_64);
188 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
193 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
197 // FrameIndex represent objects inside a abstract stack.
198 // We must replace FrameIndex with an stack/frame pointer
200 void MipsRegisterInfo::
201 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
202 unsigned FIOperandNum, RegScavenger *RS) const {
203 MachineInstr &MI = *II;
204 MachineFunction &MF = *MI.getParent()->getParent();
206 DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
207 errs() << "<--------->\n" << MI);
209 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
210 uint64_t stackSize = MF.getFrameInfo()->getStackSize();
211 int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
213 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
214 << "spOffset : " << spOffset << "\n"
215 << "stackSize : " << stackSize << "\n");
217 eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
220 unsigned MipsRegisterInfo::
221 getFrameRegister(const MachineFunction &MF) const {
222 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
223 bool IsN64 = Subtarget.isABI_N64();
225 if (Subtarget.inMips16Mode())
226 return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
228 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
229 (IsN64 ? Mips::SP_64 : Mips::SP);
233 unsigned MipsRegisterInfo::
234 getEHExceptionRegister() const {
235 llvm_unreachable("What is the exception register");
238 unsigned MipsRegisterInfo::
239 getEHHandlerRegister() const {
240 llvm_unreachable("What is the exception handler register");