1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsRegisterInfo.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsInstrInfo.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/IR/Constants.h"
27 #include "llvm/IR/DebugInfo.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
41 #define DEBUG_TYPE "mips-reg-info"
43 #define GET_REGINFO_TARGET_DESC
44 #include "MipsGenRegisterInfo.inc"
46 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST)
47 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {}
49 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
51 const TargetRegisterClass *
52 MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
53 unsigned Kind) const {
54 return Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
58 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
59 MachineFunction &MF) const {
60 switch (RC->getID()) {
63 case Mips::GPR32RegClassID:
64 case Mips::GPR64RegClassID:
65 case Mips::DSPRRegClassID: {
66 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
67 return 28 - TFI->hasFP(MF);
69 case Mips::FGR32RegClassID:
71 case Mips::AFGR64RegClassID:
73 case Mips::FGR64RegClassID:
78 //===----------------------------------------------------------------------===//
79 // Callee Saved Registers methods
80 //===----------------------------------------------------------------------===//
82 /// Mips Callee Saved Registers
84 MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
85 if (Subtarget.isSingleFloat())
86 return CSR_SingleFloatOnly_SaveList;
88 if (Subtarget.isABI_N64())
89 return CSR_N64_SaveList;
91 if (Subtarget.isABI_N32())
92 return CSR_N32_SaveList;
94 if (Subtarget.isFP64bit())
95 return CSR_O32_FP64_SaveList;
97 if (Subtarget.isFPXX())
98 return CSR_O32_FPXX_SaveList;
100 return CSR_O32_SaveList;
104 MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
105 if (Subtarget.isSingleFloat())
106 return CSR_SingleFloatOnly_RegMask;
108 if (Subtarget.isABI_N64())
109 return CSR_N64_RegMask;
111 if (Subtarget.isABI_N32())
112 return CSR_N32_RegMask;
114 if (Subtarget.isFP64bit())
115 return CSR_O32_FP64_RegMask;
117 if (Subtarget.isFPXX())
118 return CSR_O32_FPXX_RegMask;
120 return CSR_O32_RegMask;
123 const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
124 return CSR_Mips16RetHelper_RegMask;
127 BitVector MipsRegisterInfo::
128 getReservedRegs(const MachineFunction &MF) const {
129 static const MCPhysReg ReservedGPR32[] = {
130 Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
133 static const MCPhysReg ReservedGPR64[] = {
134 Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
137 BitVector Reserved(getNumRegs());
138 typedef TargetRegisterClass::const_iterator RegIter;
140 for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
141 Reserved.set(ReservedGPR32[I]);
143 // Reserve registers for the NaCl sandbox.
144 if (Subtarget.isTargetNaCl()) {
145 Reserved.set(Mips::T6); // Reserved for control flow mask.
146 Reserved.set(Mips::T7); // Reserved for memory access mask.
147 Reserved.set(Mips::T8); // Reserved for thread pointer.
150 for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
151 Reserved.set(ReservedGPR64[I]);
153 // For mno-abicalls, GP is a program invariant!
154 if (!Subtarget.isABICalls()) {
155 Reserved.set(Mips::GP);
156 Reserved.set(Mips::GP_64);
159 if (Subtarget.isFP64bit()) {
160 // Reserve all registers in AFGR64.
161 for (RegIter Reg = Mips::AFGR64RegClass.begin(),
162 EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
165 // Reserve all registers in FGR64.
166 for (RegIter Reg = Mips::FGR64RegClass.begin(),
167 EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
170 // Reserve FP if this function should have a dedicated frame pointer register.
171 if (Subtarget.getFrameLowering()->hasFP(MF)) {
172 if (Subtarget.inMips16Mode())
173 Reserved.set(Mips::S0);
175 Reserved.set(Mips::FP);
176 Reserved.set(Mips::FP_64);
180 // Reserve hardware registers.
181 Reserved.set(Mips::HWR29);
183 // Reserve DSP control register.
184 Reserved.set(Mips::DSPPos);
185 Reserved.set(Mips::DSPSCount);
186 Reserved.set(Mips::DSPCarry);
187 Reserved.set(Mips::DSPEFI);
188 Reserved.set(Mips::DSPOutFlag);
190 // Reserve MSA control registers.
191 Reserved.set(Mips::MSAIR);
192 Reserved.set(Mips::MSACSR);
193 Reserved.set(Mips::MSAAccess);
194 Reserved.set(Mips::MSASave);
195 Reserved.set(Mips::MSAModify);
196 Reserved.set(Mips::MSARequest);
197 Reserved.set(Mips::MSAMap);
198 Reserved.set(Mips::MSAUnmap);
200 // Reserve RA if in mips16 mode.
201 if (Subtarget.inMips16Mode()) {
202 const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
203 Reserved.set(Mips::RA);
204 Reserved.set(Mips::RA_64);
205 Reserved.set(Mips::T0);
206 Reserved.set(Mips::T1);
207 if (MF.getFunction()->hasFnAttribute("saveS2") || MipsFI->hasSaveS2())
208 Reserved.set(Mips::S2);
211 // Reserve GP if small section is used.
212 if (Subtarget.useSmallSection()) {
213 Reserved.set(Mips::GP);
214 Reserved.set(Mips::GP_64);
217 if (Subtarget.isABI_O32() && !Subtarget.useOddSPReg()) {
218 for (const auto &Reg : Mips::OddSPRegClass)
226 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
231 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
235 // FrameIndex represent objects inside a abstract stack.
236 // We must replace FrameIndex with an stack/frame pointer
238 void MipsRegisterInfo::
239 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
240 unsigned FIOperandNum, RegScavenger *RS) const {
241 MachineInstr &MI = *II;
242 MachineFunction &MF = *MI.getParent()->getParent();
244 DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
245 errs() << "<--------->\n" << MI);
247 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
248 uint64_t stackSize = MF.getFrameInfo()->getStackSize();
249 int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
251 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
252 << "spOffset : " << spOffset << "\n"
253 << "stackSize : " << stackSize << "\n");
255 eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
258 unsigned MipsRegisterInfo::
259 getFrameRegister(const MachineFunction &MF) const {
260 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
262 static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64();
264 if (Subtarget.inMips16Mode())
265 return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
267 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
268 (IsN64 ? Mips::SP_64 : Mips::SP);