1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-reg-info"
16 #include "MipsRegisterInfo.h"
18 #include "MipsAnalyzeImmediate.h"
19 #include "MipsSubtarget.h"
20 #include "MipsMachineFunction.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Type.h"
23 #include "llvm/Function.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/Target/TargetFrameLowering.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/ADT/BitVector.h"
37 #include "llvm/ADT/STLExtras.h"
38 #include "llvm/Analysis/DebugInfo.h"
40 #define GET_REGINFO_TARGET_DESC
41 #include "MipsGenRegisterInfo.inc"
45 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
46 const TargetInstrInfo &tii)
47 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {}
49 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
51 //===----------------------------------------------------------------------===//
52 // Callee Saved Registers methods
53 //===----------------------------------------------------------------------===//
55 /// Mips Callee Saved Registers
56 const uint16_t* MipsRegisterInfo::
57 getCalleeSavedRegs(const MachineFunction *MF) const
59 if (Subtarget.isSingleFloat())
60 return CSR_SingleFloatOnly_SaveList;
61 else if (!Subtarget.hasMips64())
62 return CSR_O32_SaveList;
63 else if (Subtarget.isABI_N32())
64 return CSR_N32_SaveList;
66 assert(Subtarget.isABI_N64());
67 return CSR_N64_SaveList;
71 MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const
73 if (Subtarget.isSingleFloat())
74 return CSR_SingleFloatOnly_RegMask;
75 else if (!Subtarget.hasMips64())
76 return CSR_O32_RegMask;
77 else if (Subtarget.isABI_N32())
78 return CSR_N32_RegMask;
80 assert(Subtarget.isABI_N64());
81 return CSR_N64_RegMask;
84 BitVector MipsRegisterInfo::
85 getReservedRegs(const MachineFunction &MF) const {
86 static const uint16_t ReservedCPURegs[] = {
87 Mips::ZERO, Mips::AT, Mips::K0, Mips::K1,
91 static const uint16_t ReservedCPU64Regs[] = {
92 Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64,
93 Mips::SP_64, Mips::RA_64
96 BitVector Reserved(getNumRegs());
97 typedef TargetRegisterClass::const_iterator RegIter;
99 for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I)
100 Reserved.set(ReservedCPURegs[I]);
102 if (Subtarget.hasMips64()) {
103 for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I)
104 Reserved.set(ReservedCPU64Regs[I]);
106 // Reserve all registers in AFGR64.
107 for (RegIter Reg = Mips::AFGR64RegClass.begin(),
108 EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
111 // Reserve all registers in CPU64Regs & FGR64.
112 for (RegIter Reg = Mips::CPU64RegsRegClass.begin(),
113 EReg = Mips::CPU64RegsRegClass.end(); Reg != EReg; ++Reg)
116 for (RegIter Reg = Mips::FGR64RegClass.begin(),
117 EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
121 // Reserve FP if this function should have a dedicated frame pointer register.
122 if (MF.getTarget().getFrameLowering()->hasFP(MF)) {
123 Reserved.set(Mips::FP);
124 Reserved.set(Mips::FP_64);
127 // Reserve hardware registers.
128 Reserved.set(Mips::HWR29);
129 Reserved.set(Mips::HWR29_64);
135 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
140 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
144 // This function eliminate ADJCALLSTACKDOWN,
145 // ADJCALLSTACKUP pseudo instructions
146 void MipsRegisterInfo::
147 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
148 MachineBasicBlock::iterator I) const {
149 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
153 // FrameIndex represent objects inside a abstract stack.
154 // We must replace FrameIndex with an stack/frame pointer
156 void MipsRegisterInfo::
157 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
158 RegScavenger *RS) const {
159 MachineInstr &MI = *II;
160 MachineFunction &MF = *MI.getParent()->getParent();
161 MachineFrameInfo *MFI = MF.getFrameInfo();
162 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
165 while (!MI.getOperand(i).isFI()) {
167 assert(i < MI.getNumOperands() &&
168 "Instr doesn't have FrameIndex operand!");
171 DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n";
172 errs() << "<--------->\n" << MI);
174 int FrameIndex = MI.getOperand(i).getIndex();
175 uint64_t stackSize = MF.getFrameInfo()->getStackSize();
176 int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
178 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
179 << "spOffset : " << spOffset << "\n"
180 << "stackSize : " << stackSize << "\n");
182 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
187 MinCSFI = CSI[0].getFrameIdx();
188 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
191 // The following stack frame objects are always referenced relative to $sp:
192 // 1. Outgoing arguments.
193 // 2. Pointer to dynamically allocated stack space.
194 // 3. Locations for callee-saved registers.
195 // Everything else is referenced relative to whatever register
196 // getFrameRegister() returns.
199 if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) ||
200 (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI))
201 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
203 FrameReg = getFrameRegister(MF);
205 // Calculate final offset.
206 // - There is no need to change the offset if the frame object is one of the
207 // following: an outgoing argument, pointer to a dynamically allocated
208 // stack space or a $gp restore location,
209 // - If the frame object is any of the following, its offset must be adjusted
210 // by adding the size of the stack:
211 // incoming argument, callee-saved register location or local variable.
214 if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex))
217 Offset = spOffset + (int64_t)stackSize;
219 Offset += MI.getOperand(i+1).getImm();
221 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
223 // If MI is not a debug value, make sure Offset fits in the 16-bit immediate
225 if (!MI.isDebugValue() && !isInt<16>(Offset)) {
226 MachineBasicBlock &MBB = *MI.getParent();
227 DebugLoc DL = II->getDebugLoc();
228 MipsAnalyzeImmediate AnalyzeImm;
229 unsigned Size = Subtarget.isABI_N64() ? 64 : 32;
230 unsigned LUi = Subtarget.isABI_N64() ? Mips::LUi64 : Mips::LUi;
231 unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
232 unsigned ZEROReg = Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
233 unsigned ATReg = Subtarget.isABI_N64() ? Mips::AT_64 : Mips::AT;
234 const MipsAnalyzeImmediate::InstSeq &Seq =
235 AnalyzeImm.Analyze(Offset, Size, true /* LastInstrIsADDiu */);
236 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
238 MipsFI->setEmitNOAT();
240 // The first instruction can be a LUi, which is different from other
241 // instructions (ADDiu, ORI and SLL) in that it does not have a register
243 if (Inst->Opc == LUi)
244 BuildMI(MBB, II, DL, TII.get(LUi), ATReg)
245 .addImm(SignExtend64<16>(Inst->ImmOpnd));
247 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg)
248 .addImm(SignExtend64<16>(Inst->ImmOpnd));
250 // Build the remaining instructions in Seq except for the last one.
251 for (++Inst; Inst != Seq.end() - 1; ++Inst)
252 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg)
253 .addImm(SignExtend64<16>(Inst->ImmOpnd));
255 BuildMI(MBB, II, DL, TII.get(ADDu), ATReg).addReg(FrameReg).addReg(ATReg);
258 Offset = SignExtend64<16>(Inst->ImmOpnd);
261 MI.getOperand(i).ChangeToRegister(FrameReg, false);
262 MI.getOperand(i+1).ChangeToImmediate(Offset);
265 unsigned MipsRegisterInfo::
266 getFrameRegister(const MachineFunction &MF) const {
267 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
268 bool IsN64 = Subtarget.isABI_N64();
270 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
271 (IsN64 ? Mips::SP_64 : Mips::SP);
274 unsigned MipsRegisterInfo::
275 getEHExceptionRegister() const {
276 llvm_unreachable("What is the exception register");
279 unsigned MipsRegisterInfo::
280 getEHHandlerRegister() const {
281 llvm_unreachable("What is the exception handler register");