1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-reg-info"
16 #include "MipsRegisterInfo.h"
18 #include "MipsAnalyzeImmediate.h"
19 #include "MipsInstrInfo.h"
20 #include "MipsMachineFunction.h"
21 #include "MipsSubtarget.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/ValueTypes.h"
28 #include "llvm/DebugInfo.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/Type.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
41 #define GET_REGINFO_TARGET_DESC
42 #include "MipsGenRegisterInfo.inc"
46 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST)
47 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {}
49 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
51 const TargetRegisterClass *
52 MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
53 unsigned Kind) const {
54 return Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
58 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
59 MachineFunction &MF) const {
60 switch (RC->getID()) {
63 case Mips::GPR32RegClassID:
64 case Mips::GPR64RegClassID:
65 case Mips::DSPRRegClassID: {
66 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
67 return 28 - TFI->hasFP(MF);
69 case Mips::FGR32RegClassID:
71 case Mips::AFGR64RegClassID:
73 case Mips::FGR64RegClassID:
78 //===----------------------------------------------------------------------===//
79 // Callee Saved Registers methods
80 //===----------------------------------------------------------------------===//
82 /// Mips Callee Saved Registers
83 const uint16_t* MipsRegisterInfo::
84 getCalleeSavedRegs(const MachineFunction *MF) const {
85 if (Subtarget.isSingleFloat())
86 return CSR_SingleFloatOnly_SaveList;
88 if (Subtarget.isABI_N64())
89 return CSR_N64_SaveList;
91 if (Subtarget.isABI_N32())
92 return CSR_N32_SaveList;
94 if (Subtarget.isFP64bit())
95 return CSR_O32_FP64_SaveList;
97 return CSR_O32_SaveList;
101 MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
102 if (Subtarget.isSingleFloat())
103 return CSR_SingleFloatOnly_RegMask;
105 if (Subtarget.isABI_N64())
106 return CSR_N64_RegMask;
108 if (Subtarget.isABI_N32())
109 return CSR_N32_RegMask;
111 if (Subtarget.isFP64bit())
112 return CSR_O32_FP64_RegMask;
114 return CSR_O32_RegMask;
117 const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
118 return CSR_Mips16RetHelper_RegMask;
121 BitVector MipsRegisterInfo::
122 getReservedRegs(const MachineFunction &MF) const {
123 static const uint16_t ReservedGPR32[] = {
124 Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
127 static const uint16_t ReservedGPR64[] = {
128 Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
131 BitVector Reserved(getNumRegs());
132 typedef TargetRegisterClass::const_iterator RegIter;
134 for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
135 Reserved.set(ReservedGPR32[I]);
137 for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
138 Reserved.set(ReservedGPR64[I]);
140 if (Subtarget.isFP64bit()) {
141 // Reserve all registers in AFGR64.
142 for (RegIter Reg = Mips::AFGR64RegClass.begin(),
143 EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
146 // Reserve all registers in FGR64.
147 for (RegIter Reg = Mips::FGR64RegClass.begin(),
148 EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
151 // Reserve FP if this function should have a dedicated frame pointer register.
152 if (MF.getTarget().getFrameLowering()->hasFP(MF)) {
153 if (Subtarget.inMips16Mode())
154 Reserved.set(Mips::S0);
156 Reserved.set(Mips::FP);
157 Reserved.set(Mips::FP_64);
161 // Reserve hardware registers.
162 Reserved.set(Mips::HWR29);
164 // Reserve DSP control register.
165 Reserved.set(Mips::DSPPos);
166 Reserved.set(Mips::DSPSCount);
167 Reserved.set(Mips::DSPCarry);
168 Reserved.set(Mips::DSPEFI);
169 Reserved.set(Mips::DSPOutFlag);
171 // Reserve MSA control registers.
172 Reserved.set(Mips::MSAIR);
173 Reserved.set(Mips::MSACSR);
174 Reserved.set(Mips::MSAAccess);
175 Reserved.set(Mips::MSASave);
176 Reserved.set(Mips::MSAModify);
177 Reserved.set(Mips::MSARequest);
178 Reserved.set(Mips::MSAMap);
179 Reserved.set(Mips::MSAUnmap);
181 // Reserve RA if in mips16 mode.
182 if (Subtarget.inMips16Mode()) {
183 Reserved.set(Mips::RA);
184 Reserved.set(Mips::RA_64);
185 Reserved.set(Mips::T0);
186 Reserved.set(Mips::T1);
187 if (MF.getFunction()->hasFnAttribute("saveS2"))
188 Reserved.set(Mips::S2);
191 // Reserve GP if small section is used.
192 if (Subtarget.useSmallSection()) {
193 Reserved.set(Mips::GP);
194 Reserved.set(Mips::GP_64);
201 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
206 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
210 // FrameIndex represent objects inside a abstract stack.
211 // We must replace FrameIndex with an stack/frame pointer
213 void MipsRegisterInfo::
214 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
215 unsigned FIOperandNum, RegScavenger *RS) const {
216 MachineInstr &MI = *II;
217 MachineFunction &MF = *MI.getParent()->getParent();
219 DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
220 errs() << "<--------->\n" << MI);
222 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
223 uint64_t stackSize = MF.getFrameInfo()->getStackSize();
224 int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
226 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
227 << "spOffset : " << spOffset << "\n"
228 << "stackSize : " << stackSize << "\n");
230 eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
233 unsigned MipsRegisterInfo::
234 getFrameRegister(const MachineFunction &MF) const {
235 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
236 bool IsN64 = Subtarget.isABI_N64();
238 if (Subtarget.inMips16Mode())
239 return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
241 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
242 (IsN64 ? Mips::SP_64 : Mips::SP);