1 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Bruno Cardoso Lopes and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-reg-info"
17 #include "MipsRegisterInfo.h"
18 #include "MipsMachineFunction.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Type.h"
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/ValueTypes.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineLocation.h"
27 #include "llvm/Target/TargetFrameInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/STLExtras.h"
35 //#include "MipsSubtarget.h"
39 // TODO: add subtarget support
40 MipsRegisterInfo::MipsRegisterInfo(const TargetInstrInfo &tii)
41 : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
44 /// getRegisterNumbering - Given the enum value for some register, e.g.
45 /// Mips::RA, return the number that it corresponds to (e.g. 31).
46 unsigned MipsRegisterInfo::
47 getRegisterNumbering(unsigned RegEnum)
50 case Mips::ZERO : return 0;
51 case Mips::AT : return 1;
52 case Mips::V0 : return 2;
53 case Mips::V1 : return 3;
54 case Mips::A0 : return 4;
55 case Mips::A1 : return 5;
56 case Mips::A2 : return 6;
57 case Mips::A3 : return 7;
58 case Mips::T0 : return 8;
59 case Mips::T1 : return 9;
60 case Mips::T2 : return 10;
61 case Mips::T3 : return 11;
62 case Mips::T4 : return 12;
63 case Mips::T5 : return 13;
64 case Mips::T6 : return 14;
65 case Mips::T7 : return 15;
66 case Mips::T8 : return 16;
67 case Mips::T9 : return 17;
68 case Mips::S0 : return 18;
69 case Mips::S1 : return 19;
70 case Mips::S2 : return 20;
71 case Mips::S3 : return 21;
72 case Mips::S4 : return 22;
73 case Mips::S5 : return 23;
74 case Mips::S6 : return 24;
75 case Mips::S7 : return 25;
76 case Mips::K0 : return 26;
77 case Mips::K1 : return 27;
78 case Mips::GP : return 28;
79 case Mips::SP : return 29;
80 case Mips::FP : return 30;
81 case Mips::RA : return 31;
82 default: assert(0 && "Unknown register number!");
86 void MipsRegisterInfo::
87 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
88 unsigned SrcReg, int FI,
89 const TargetRegisterClass *RC) const
91 if (RC == Mips::CPURegsRegisterClass)
92 BuildMI(MBB, I, TII.get(Mips::SW)).addReg(SrcReg, false, false, true)
93 .addImm(0).addFrameIndex(FI);
95 assert(0 && "Can't store this register to stack slot");
98 void MipsRegisterInfo::
99 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
100 unsigned DestReg, int FI,
101 const TargetRegisterClass *RC) const
103 if (RC == Mips::CPURegsRegisterClass)
104 BuildMI(MBB, I, TII.get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
106 assert(0 && "Can't load this register from stack slot");
109 void MipsRegisterInfo::
110 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
111 unsigned DestReg, unsigned SrcReg,
112 const TargetRegisterClass *DestRC,
113 const TargetRegisterClass *SrcRC) const
115 if (DestRC != SrcRC) {
116 cerr << "Not yet supported!";
120 if (DestRC == Mips::CPURegsRegisterClass)
121 BuildMI(MBB, I, TII.get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
124 assert (0 && "Can't copy this register");
127 void MipsRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
128 MachineBasicBlock::iterator I,
130 const MachineInstr *Orig) const
132 MachineInstr *MI = Orig->clone();
133 MI->getOperand(0).setReg(DestReg);
137 MachineInstr *MipsRegisterInfo::
138 foldMemoryOperand(MachineInstr* MI, unsigned OpNum, int FI) const
140 MachineInstr *NewMI = NULL;
142 switch (MI->getOpcode())
145 if ((MI->getOperand(0).isRegister()) &&
146 (MI->getOperand(1).isRegister()) &&
147 (MI->getOperand(1).getReg() == Mips::ZERO) &&
148 (MI->getOperand(2).isRegister()))
150 if (OpNum == 0) // COPY -> STORE
151 NewMI = BuildMI(TII.get(Mips::SW)).addFrameIndex(FI)
152 .addImm(0).addReg(MI->getOperand(2).getReg());
154 NewMI = BuildMI(TII.get(Mips::LW), MI->getOperand(0)
155 .getReg()).addImm(0).addFrameIndex(FI);
161 NewMI->copyKillDeadInfo(MI);
165 //===----------------------------------------------------------------------===//
167 // Callee Saved Registers methods
169 //===----------------------------------------------------------------------===//
171 /// Mips Callee Saved Registers
172 const unsigned* MipsRegisterInfo::
173 getCalleeSavedRegs(const MachineFunction *MF) const
175 // Mips calle-save register range is $16-$26(s0-s7)
176 static const unsigned CalleeSavedRegs[] = {
177 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
178 Mips::S4, Mips::S5, Mips::S6, Mips::S7, 0
180 return CalleeSavedRegs;
183 /// Mips Callee Saved Register Classes
184 const TargetRegisterClass* const*
185 MipsRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
187 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
188 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
189 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
190 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
191 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, 0
193 return CalleeSavedRegClasses;
196 BitVector MipsRegisterInfo::
197 getReservedRegs(const MachineFunction &MF) const
199 BitVector Reserved(getNumRegs());
200 Reserved.set(Mips::ZERO);
201 Reserved.set(Mips::AT);
202 Reserved.set(Mips::K0);
203 Reserved.set(Mips::K1);
204 Reserved.set(Mips::GP);
205 Reserved.set(Mips::SP);
206 Reserved.set(Mips::FP);
207 Reserved.set(Mips::RA);
211 //===----------------------------------------------------------------------===//
213 // Stack Frame Processing methods
214 // +----------------------------+
216 // The stack is allocated decrementing the stack pointer on
217 // the first instruction of a function prologue. Once decremented,
218 // all stack referencesare are done thought a positive offset
219 // from the stack/frame pointer, so the stack is considering
220 // to grow up! Otherwise terrible hacks would have to be made
221 // to get this stack ABI compliant :)
223 // The stack frame required by the ABI:
228 // . saved $GP (used in PIC - not supported yet)
230 // . saved "Callee Saved" Registers
233 // StackSize -----------
235 // Offset - offset from sp after stack allocation on function prologue
237 // The sp is the stack pointer subtracted/added from the stack size
238 // at the Prologue/Epilogue
240 // References to the previous stack (to obtain arguments) are done
241 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
244 // - reference to the actual stack frame
245 // for any local area var there is smt like : FI >= 0, StackOffset: 4
248 // - reference to previous stack frame
249 // suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
250 // The emitted instruction will be something like:
251 // lw REGX, 16+StackSize(SP)
253 // Since the total stack size is unknown on LowerFORMAL_ARGUMENTS, all
254 // stack references (ObjectOffset) created to reference the function
255 // arguments, are negative numbers. This way, on eliminateFrameIndex it's
256 // possible to detect those references and the offsets are adjusted to
257 // their real location.
261 //===----------------------------------------------------------------------===//
263 // hasFP - Return true if the specified function should have a dedicated frame
264 // pointer register. This is true if the function has variable sized allocas or
265 // if frame pointer elimination is disabled.
266 bool MipsRegisterInfo::
267 hasFP(const MachineFunction &MF) const {
268 return (NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects());
271 // This function eliminate ADJCALLSTACKDOWN,
272 // ADJCALLSTACKUP pseudo instructions
273 void MipsRegisterInfo::
274 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
275 MachineBasicBlock::iterator I) const {
276 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
280 // FrameIndex represent objects inside a abstract stack.
281 // We must replace FrameIndex with an stack/frame pointer
283 void MipsRegisterInfo::
284 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
285 RegScavenger *RS) const
287 MachineInstr &MI = *II;
288 MachineFunction &MF = *MI.getParent()->getParent();
291 while (!MI.getOperand(i).isFrameIndex()) {
293 assert(i < MI.getNumOperands() &&
294 "Instr doesn't have FrameIndex operand!");
297 int FrameIndex = MI.getOperand(i).getFrameIndex();
298 int stackSize = MF.getFrameInfo()->getStackSize();
299 int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
302 DOUT << "\nFunction : " << MF.getFunction()->getName() << "\n";
303 DOUT << "<--------->\n";
305 DOUT << "FrameIndex : " << FrameIndex << "\n";
306 DOUT << "spOffset : " << spOffset << "\n";
307 DOUT << "stackSize : " << stackSize << "\n";
310 // as explained on LowerFORMAL_ARGUMENTS, detect negative offsets
311 // and adjust SPOffsets considering the final stack size.
312 int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
313 Offset += MI.getOperand(i-1).getImm();
316 DOUT << "Offset : " << Offset << "\n";
317 DOUT << "<--------->\n";
320 MI.getOperand(i-1).ChangeToImmediate(Offset);
321 MI.getOperand(i).ChangeToRegister(getFrameRegister(MF),false);
324 void MipsRegisterInfo::
325 emitPrologue(MachineFunction &MF) const
327 MachineBasicBlock &MBB = MF.front();
328 MachineFrameInfo *MFI = MF.getFrameInfo();
329 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
330 MachineBasicBlock::iterator MBBI = MBB.begin();
332 // Replace the dummy '0' SPOffset by the negative offsets, as
333 // explained on LowerFORMAL_ARGUMENTS
334 MipsFI->adjustLoadArgsFI(MFI);
335 MipsFI->adjustStoreVarArgsFI(MFI);
337 // Get the number of bytes to allocate from the FrameInfo.
338 int NumBytes = (int) MFI->getStackSize();
341 DOUT << "\n<--- EMIT PROLOGUE --->\n";
342 DOUT << "Actual Stack size :" << NumBytes << "\n";
345 // No need to allocate space on the stack.
346 if (NumBytes == 0) return;
348 int FPOffset, RAOffset;
350 // Allocate space for saved RA and FP when needed
351 if ((hasFP(MF)) && (MFI->hasCalls())) {
353 RAOffset = (NumBytes+4);
355 } else if ((!hasFP(MF)) && (MFI->hasCalls())) {
359 } else if ((hasFP(MF)) && (!MFI->hasCalls())) {
365 MFI->setObjectOffset(MFI->CreateStackObject(4,4), FPOffset);
366 MFI->setObjectOffset(MFI->CreateStackObject(4,4), RAOffset);
367 MipsFI->setFPStackOffset(FPOffset);
368 MipsFI->setRAStackOffset(RAOffset);
371 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
372 NumBytes = ((NumBytes+Align-1)/Align*Align);
375 DOUT << "FPOffset :" << FPOffset << "\n";
376 DOUT << "RAOffset :" << RAOffset << "\n";
377 DOUT << "New stack size :" << NumBytes << "\n\n";
381 MFI->setStackSize(NumBytes);
383 // Adjust stack : addi sp, sp, (-imm)
384 BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
385 .addReg(Mips::SP).addImm(-NumBytes);
387 // Save the return address only if the function isnt a leaf one.
388 // sw $ra, stack_loc($sp)
389 if (MFI->hasCalls()) {
390 BuildMI(MBB, MBBI, TII.get(Mips::SW))
391 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
394 // if framepointer enabled, save it and set it
395 // to point to the stack pointer
397 // sw $fp,stack_loc($sp)
398 BuildMI(MBB, MBBI, TII.get(Mips::SW))
399 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
402 BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::FP)
403 .addReg(Mips::SP).addReg(Mips::ZERO);
407 void MipsRegisterInfo::
408 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
410 MachineBasicBlock::iterator MBBI = prior(MBB.end());
411 MachineFrameInfo *MFI = MF.getFrameInfo();
412 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
414 // Get the number of bytes from FrameInfo
415 int NumBytes = (int) MFI->getStackSize();
417 // Get the FI's where RA and FP are saved.
418 int FPOffset = MipsFI->getFPStackOffset();
419 int RAOffset = MipsFI->getRAStackOffset();
421 // if framepointer enabled, restore it and restore the
425 BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::SP)
426 .addReg(Mips::FP).addReg(Mips::ZERO);
428 // lw $fp,stack_loc($sp)
429 BuildMI(MBB, MBBI, TII.get(Mips::LW))
430 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
433 // Restore the return address only if the function isnt a leaf one.
434 // lw $ra, stack_loc($sp)
435 if (MFI->hasCalls()) {
436 BuildMI(MBB, MBBI, TII.get(Mips::LW))
437 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
440 // adjust stack : insert addi sp, sp, (imm)
442 BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
443 .addReg(Mips::SP).addImm(NumBytes);
447 void MipsRegisterInfo::
448 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
451 unsigned MipsRegisterInfo::
452 getRARegister() const {
456 unsigned MipsRegisterInfo::
457 getFrameRegister(MachineFunction &MF) const {
458 return hasFP(MF) ? Mips::FP : Mips::SP;
461 unsigned MipsRegisterInfo::
462 getEHExceptionRegister() const {
463 assert(0 && "What is the exception register");
467 unsigned MipsRegisterInfo::
468 getEHHandlerRegister() const {
469 assert(0 && "What is the exception handler register");
473 #include "MipsGenRegisterInfo.inc"