1 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-reg-info"
17 #include "MipsRegisterInfo.h"
18 #include "MipsMachineFunction.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Type.h"
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/ValueTypes.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineLocation.h"
27 #include "llvm/Target/TargetFrameInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/STLExtras.h"
38 MipsRegisterInfo::MipsRegisterInfo(const TargetInstrInfo &tii)
39 : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
42 /// getRegisterNumbering - Given the enum value for some register, e.g.
43 /// Mips::RA, return the number that it corresponds to (e.g. 31).
44 unsigned MipsRegisterInfo::
45 getRegisterNumbering(unsigned RegEnum)
48 case Mips::ZERO : case Mips::F0 : return 0;
49 case Mips::AT : case Mips::F1 : return 1;
50 case Mips::V0 : case Mips::F2 : return 2;
51 case Mips::V1 : case Mips::F3 : return 3;
52 case Mips::A0 : case Mips::F4 : return 4;
53 case Mips::A1 : case Mips::F5 : return 5;
54 case Mips::A2 : case Mips::F6 : return 6;
55 case Mips::A3 : case Mips::F7 : return 7;
56 case Mips::T0 : case Mips::F8 : return 8;
57 case Mips::T1 : case Mips::F9 : return 9;
58 case Mips::T2 : case Mips::F10: return 10;
59 case Mips::T3 : case Mips::F11: return 11;
60 case Mips::T4 : case Mips::F12: return 12;
61 case Mips::T5 : case Mips::F13: return 13;
62 case Mips::T6 : case Mips::F14: return 14;
63 case Mips::T7 : case Mips::F15: return 15;
64 case Mips::T8 : case Mips::F16: return 16;
65 case Mips::T9 : case Mips::F17: return 17;
66 case Mips::S0 : case Mips::F18: return 18;
67 case Mips::S1 : case Mips::F19: return 19;
68 case Mips::S2 : case Mips::F20: return 20;
69 case Mips::S3 : case Mips::F21: return 21;
70 case Mips::S4 : case Mips::F22: return 22;
71 case Mips::S5 : case Mips::F23: return 23;
72 case Mips::S6 : case Mips::F24: return 24;
73 case Mips::S7 : case Mips::F25: return 25;
74 case Mips::K0 : case Mips::F26: return 26;
75 case Mips::K1 : case Mips::F27: return 27;
76 case Mips::GP : case Mips::F28: return 28;
77 case Mips::SP : case Mips::F29: return 29;
78 case Mips::FP : case Mips::F30: return 30;
79 case Mips::RA : case Mips::F31: return 31;
80 default: assert(0 && "Unknown register number!");
82 return 0; // Not reached
85 //===----------------------------------------------------------------------===//
87 // Callee Saved Registers methods
89 //===----------------------------------------------------------------------===//
91 /// Mips Callee Saved Registers
92 const unsigned* MipsRegisterInfo::
93 getCalleeSavedRegs(const MachineFunction *MF) const
95 // Mips callee-save register range is $16-$23(s0-s7)
96 static const unsigned CalleeSavedRegs[] = {
97 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
98 Mips::S4, Mips::S5, Mips::S6, Mips::S7, 0
101 return CalleeSavedRegs;
104 /// Mips Callee Saved Register Classes
105 const TargetRegisterClass* const*
106 MipsRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
108 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
109 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
110 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
111 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
112 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, 0
114 return CalleeSavedRegClasses;
117 BitVector MipsRegisterInfo::
118 getReservedRegs(const MachineFunction &MF) const
120 BitVector Reserved(getNumRegs());
121 Reserved.set(Mips::ZERO);
122 Reserved.set(Mips::AT);
123 Reserved.set(Mips::K0);
124 Reserved.set(Mips::K1);
125 Reserved.set(Mips::GP);
126 Reserved.set(Mips::SP);
127 Reserved.set(Mips::FP);
128 Reserved.set(Mips::RA);
132 //===----------------------------------------------------------------------===//
134 // Stack Frame Processing methods
135 // +----------------------------+
137 // The stack is allocated decrementing the stack pointer on
138 // the first instruction of a function prologue. Once decremented,
139 // all stack referencesare are done thought a positive offset
140 // from the stack/frame pointer, so the stack is considering
141 // to grow up! Otherwise terrible hacks would have to be made
142 // to get this stack ABI compliant :)
144 // The stack frame required by the ABI:
149 // . saved $GP (used in PIC)
151 // . saved "Callee Saved" Registers
154 // StackSize -----------
156 // Offset - offset from sp after stack allocation on function prologue
158 // The sp is the stack pointer subtracted/added from the stack size
159 // at the Prologue/Epilogue
161 // References to the previous stack (to obtain arguments) are done
162 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
165 // - reference to the actual stack frame
166 // for any local area var there is smt like : FI >= 0, StackOffset: 4
169 // - reference to previous stack frame
170 // suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
171 // The emitted instruction will be something like:
172 // lw REGX, 16+StackSize(SP)
174 // Since the total stack size is unknown on LowerFORMAL_ARGUMENTS, all
175 // stack references (ObjectOffset) created to reference the function
176 // arguments, are negative numbers. This way, on eliminateFrameIndex it's
177 // possible to detect those references and the offsets are adjusted to
178 // their real location.
182 //===----------------------------------------------------------------------===//
184 // hasFP - Return true if the specified function should have a dedicated frame
185 // pointer register. This is true if the function has variable sized allocas or
186 // if frame pointer elimination is disabled.
187 bool MipsRegisterInfo::
188 hasFP(const MachineFunction &MF) const {
189 return (NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects());
192 // This function eliminate ADJCALLSTACKDOWN,
193 // ADJCALLSTACKUP pseudo instructions
194 void MipsRegisterInfo::
195 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
196 MachineBasicBlock::iterator I) const {
197 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
201 // FrameIndex represent objects inside a abstract stack.
202 // We must replace FrameIndex with an stack/frame pointer
204 void MipsRegisterInfo::
205 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
206 RegScavenger *RS) const
208 MachineInstr &MI = *II;
209 MachineFunction &MF = *MI.getParent()->getParent();
212 while (!MI.getOperand(i).isFrameIndex()) {
214 assert(i < MI.getNumOperands() &&
215 "Instr doesn't have FrameIndex operand!");
218 int FrameIndex = MI.getOperand(i).getIndex();
219 int stackSize = MF.getFrameInfo()->getStackSize();
220 int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
223 DOUT << "\nFunction : " << MF.getFunction()->getName() << "\n";
224 DOUT << "<--------->\n";
226 DOUT << "FrameIndex : " << FrameIndex << "\n";
227 DOUT << "spOffset : " << spOffset << "\n";
228 DOUT << "stackSize : " << stackSize << "\n";
231 // as explained on LowerFORMAL_ARGUMENTS, detect negative offsets
232 // and adjust SPOffsets considering the final stack size.
233 int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
234 Offset += MI.getOperand(i-1).getImm();
237 DOUT << "Offset : " << Offset << "\n";
238 DOUT << "<--------->\n";
241 MI.getOperand(i-1).ChangeToImmediate(Offset);
242 MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
245 void MipsRegisterInfo::
246 emitPrologue(MachineFunction &MF) const
248 MachineBasicBlock &MBB = MF.front();
249 MachineFrameInfo *MFI = MF.getFrameInfo();
250 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
251 MachineBasicBlock::iterator MBBI = MBB.begin();
252 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
254 // Replace the dummy '0' SPOffset by the negative
255 // offsets, as explained on LowerFORMAL_ARGUMENTS
256 MipsFI->adjustLoadArgsFI(MFI);
257 MipsFI->adjustStoreVarArgsFI(MFI);
259 // Get the number of bytes to allocate from the FrameInfo.
260 int NumBytes = (int) MFI->getStackSize();
263 DOUT << "\n<--- EMIT PROLOGUE --->\n";
264 DOUT << "Actual Stack size :" << NumBytes << "\n";
267 // No need to allocate space on the stack.
268 if (NumBytes == 0) return;
270 int FPOffset, RAOffset;
272 // Allocate space for saved RA and FP when needed
273 // FIXME: within 64-bit registers, change hardcoded
274 // sizes for RA and FP offsets.
275 if ((hasFP(MF)) && (MFI->hasCalls())) {
277 RAOffset = (NumBytes+4);
279 } else if ((!hasFP(MF)) && (MFI->hasCalls())) {
283 } else if ((hasFP(MF)) && (!MFI->hasCalls())) {
287 } else { // No calls and no fp.
288 RAOffset = FPOffset = 0;
291 MFI->setObjectOffset(MFI->CreateStackObject(4,4), FPOffset);
292 MFI->setObjectOffset(MFI->CreateStackObject(4,4), RAOffset);
293 MipsFI->setFPStackOffset(FPOffset);
294 MipsFI->setRAStackOffset(RAOffset);
297 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
298 NumBytes = ((NumBytes+Align-1)/Align*Align);
301 DOUT << "FPOffset :" << FPOffset << "\n";
302 DOUT << "RAOffset :" << RAOffset << "\n";
303 DOUT << "New stack size :" << NumBytes << "\n\n";
307 MFI->setStackSize(NumBytes);
309 // PIC speficic function prologue
311 BuildMI(MBB, MBBI, TII.get(Mips::CPLOAD)).addReg(Mips::T9);
313 // Adjust stack : addi sp, sp, (-imm)
314 BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
315 .addReg(Mips::SP).addImm(-NumBytes);
317 // Save the return address only if the function isnt a leaf one.
318 // sw $ra, stack_loc($sp)
319 if (MFI->hasCalls()) {
320 BuildMI(MBB, MBBI, TII.get(Mips::SW))
321 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
324 // if framepointer enabled, save it and set it
325 // to point to the stack pointer
327 // sw $fp,stack_loc($sp)
328 BuildMI(MBB, MBBI, TII.get(Mips::SW))
329 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
332 BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::FP)
333 .addReg(Mips::SP).addReg(Mips::ZERO);
336 // PIC speficic function prologue
337 if ((isPIC) && (MFI->hasCalls()))
338 BuildMI(MBB, MBBI, TII.get(Mips::CPRESTORE))
339 .addImm(MipsFI->getGPStackOffset());
342 void MipsRegisterInfo::
343 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
345 MachineBasicBlock::iterator MBBI = prior(MBB.end());
346 MachineFrameInfo *MFI = MF.getFrameInfo();
347 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
349 // Get the number of bytes from FrameInfo
350 int NumBytes = (int) MFI->getStackSize();
352 // Get the FI's where RA and FP are saved.
353 int FPOffset = MipsFI->getFPStackOffset();
354 int RAOffset = MipsFI->getRAStackOffset();
356 // if framepointer enabled, restore it and restore the
360 BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::SP)
361 .addReg(Mips::FP).addReg(Mips::ZERO);
363 // lw $fp,stack_loc($sp)
364 BuildMI(MBB, MBBI, TII.get(Mips::LW))
365 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
368 // Restore the return address only if the function isnt a leaf one.
369 // lw $ra, stack_loc($sp)
370 if (MFI->hasCalls()) {
371 BuildMI(MBB, MBBI, TII.get(Mips::LW))
372 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
375 // adjust stack : insert addi sp, sp, (imm)
377 BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
378 .addReg(Mips::SP).addImm(NumBytes);
382 void MipsRegisterInfo::
383 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
384 // Set the SPOffset on the FI where GP must be saved/loaded.
385 MachineFrameInfo *MFI = MF.getFrameInfo();
386 if (MFI->hasCalls()) {
387 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
389 DOUT << "processFunctionBeforeFrameFinalized\n";
390 DOUT << "GPOffset :" << MipsFI->getGPStackOffset() << "\n";
391 DOUT << "FI :" << MipsFI->getGPFI() << "\n";
393 MFI->setObjectOffset(MipsFI->getGPFI(), MipsFI->getGPStackOffset());
397 unsigned MipsRegisterInfo::
398 getRARegister() const {
402 unsigned MipsRegisterInfo::
403 getFrameRegister(MachineFunction &MF) const {
404 return hasFP(MF) ? Mips::FP : Mips::SP;
407 unsigned MipsRegisterInfo::
408 getEHExceptionRegister() const {
409 assert(0 && "What is the exception register");
413 unsigned MipsRegisterInfo::
414 getEHHandlerRegister() const {
415 assert(0 && "What is the exception handler register");
419 int MipsRegisterInfo::
420 getDwarfRegNum(unsigned RegNum, bool isEH) const {
421 assert(0 && "What is the dwarf register number");
425 #include "MipsGenRegisterInfo.inc"