1 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-reg-info"
17 #include "MipsSubtarget.h"
18 #include "MipsRegisterInfo.h"
19 #include "MipsMachineFunction.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Type.h"
22 #include "llvm/Function.h"
23 #include "llvm/CodeGen/ValueTypes.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineLocation.h"
28 #include "llvm/Target/TargetFrameInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/ADT/BitVector.h"
35 #include "llvm/ADT/STLExtras.h"
39 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
40 const TargetInstrInfo &tii)
41 : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
42 Subtarget(ST), TII(tii) {}
44 /// getRegisterNumbering - Given the enum value for some register, e.g.
45 /// Mips::RA, return the number that it corresponds to (e.g. 31).
46 unsigned MipsRegisterInfo::
47 getRegisterNumbering(unsigned RegEnum)
50 case Mips::ZERO : case Mips::F0 : case Mips::D0 : return 0;
51 case Mips::AT : case Mips::F1 : return 1;
52 case Mips::V0 : case Mips::F2 : case Mips::D1 : return 2;
53 case Mips::V1 : case Mips::F3 : return 3;
54 case Mips::A0 : case Mips::F4 : case Mips::D2 : return 4;
55 case Mips::A1 : case Mips::F5 : return 5;
56 case Mips::A2 : case Mips::F6 : case Mips::D3 : return 6;
57 case Mips::A3 : case Mips::F7 : return 7;
58 case Mips::T0 : case Mips::F8 : case Mips::D4 : return 8;
59 case Mips::T1 : case Mips::F9 : return 9;
60 case Mips::T2 : case Mips::F10: case Mips::D5: return 10;
61 case Mips::T3 : case Mips::F11: return 11;
62 case Mips::T4 : case Mips::F12: case Mips::D6: return 12;
63 case Mips::T5 : case Mips::F13: return 13;
64 case Mips::T6 : case Mips::F14: case Mips::D7: return 14;
65 case Mips::T7 : case Mips::F15: return 15;
66 case Mips::T8 : case Mips::F16: case Mips::D8: return 16;
67 case Mips::T9 : case Mips::F17: return 17;
68 case Mips::S0 : case Mips::F18: case Mips::D9: return 18;
69 case Mips::S1 : case Mips::F19: return 19;
70 case Mips::S2 : case Mips::F20: case Mips::D10: return 20;
71 case Mips::S3 : case Mips::F21: return 21;
72 case Mips::S4 : case Mips::F22: case Mips::D11: return 22;
73 case Mips::S5 : case Mips::F23: return 23;
74 case Mips::S6 : case Mips::F24: case Mips::D12: return 24;
75 case Mips::S7 : case Mips::F25: return 25;
76 case Mips::K0 : case Mips::F26: case Mips::D13: return 26;
77 case Mips::K1 : case Mips::F27: return 27;
78 case Mips::GP : case Mips::F28: case Mips::D14: return 28;
79 case Mips::SP : case Mips::F29: return 29;
80 case Mips::FP : case Mips::F30: case Mips::D15: return 30;
81 case Mips::RA : case Mips::F31: return 31;
82 default: assert(0 && "Unknown register number!");
84 return 0; // Not reached
87 unsigned MipsRegisterInfo::getPICCallReg(void) { return Mips::T9; }
89 //===----------------------------------------------------------------------===//
90 // Callee Saved Registers methods
91 //===----------------------------------------------------------------------===//
93 /// Mips Callee Saved Registers
94 const unsigned* MipsRegisterInfo::
95 getCalleeSavedRegs(const MachineFunction *MF) const
97 // Mips callee-save register range is $16-$23, $f20-$f30
98 static const unsigned SingleFloatOnlyCalleeSavedRegs[] = {
99 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
100 Mips::S4, Mips::S5, Mips::S6, Mips::S7,
101 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25,
102 Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, 0
105 static const unsigned BitMode32CalleeSavedRegs[] = {
106 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
107 Mips::S4, Mips::S5, Mips::S6, Mips::S7,
108 Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30,
109 Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15,0
112 if (Subtarget.isSingleFloat())
113 return SingleFloatOnlyCalleeSavedRegs;
115 return BitMode32CalleeSavedRegs;
118 /// Mips Callee Saved Register Classes
119 const TargetRegisterClass* const*
120 MipsRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
122 static const TargetRegisterClass * const SingleFloatOnlyCalleeSavedRC[] = {
123 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
124 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
125 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
126 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
127 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
128 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
129 &Mips::FGR32RegClass, &Mips::FGR32RegClass, 0
132 static const TargetRegisterClass * const BitMode32CalleeSavedRC[] = {
133 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
134 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
135 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
136 &Mips::AFGR32RegClass, &Mips::AFGR32RegClass, &Mips::AFGR32RegClass,
137 &Mips::AFGR32RegClass, &Mips::AFGR32RegClass, &Mips::AFGR32RegClass,
138 &Mips::AFGR64RegClass, &Mips::AFGR64RegClass, &Mips::AFGR64RegClass,
139 &Mips::AFGR64RegClass, &Mips::AFGR64RegClass, &Mips::AFGR64RegClass, 0
142 if (Subtarget.isSingleFloat())
143 return SingleFloatOnlyCalleeSavedRC;
145 return BitMode32CalleeSavedRC;
148 BitVector MipsRegisterInfo::
149 getReservedRegs(const MachineFunction &MF) const
151 BitVector Reserved(getNumRegs());
152 Reserved.set(Mips::ZERO);
153 Reserved.set(Mips::AT);
154 Reserved.set(Mips::K0);
155 Reserved.set(Mips::K1);
156 Reserved.set(Mips::GP);
157 Reserved.set(Mips::SP);
158 Reserved.set(Mips::FP);
159 Reserved.set(Mips::RA);
163 //===----------------------------------------------------------------------===//
165 // Stack Frame Processing methods
166 // +----------------------------+
168 // The stack is allocated decrementing the stack pointer on
169 // the first instruction of a function prologue. Once decremented,
170 // all stack referencesare are done thought a positive offset
171 // from the stack/frame pointer, so the stack is considering
172 // to grow up! Otherwise terrible hacks would have to be made
173 // to get this stack ABI compliant :)
175 // The stack frame required by the ABI (after call):
180 // . saved $GP (used in PIC)
181 // . Alloca allocations
183 // . CPU "Callee Saved" Registers
186 // . FPU "Callee Saved" Registers
187 // StackSize -----------
189 // Offset - offset from sp after stack allocation on function prologue
191 // The sp is the stack pointer subtracted/added from the stack size
192 // at the Prologue/Epilogue
194 // References to the previous stack (to obtain arguments) are done
195 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
198 // - reference to the actual stack frame
199 // for any local area var there is smt like : FI >= 0, StackOffset: 4
202 // - reference to previous stack frame
203 // suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
204 // The emitted instruction will be something like:
205 // lw REGX, 16+StackSize(SP)
207 // Since the total stack size is unknown on LowerFORMAL_ARGUMENTS, all
208 // stack references (ObjectOffset) created to reference the function
209 // arguments, are negative numbers. This way, on eliminateFrameIndex it's
210 // possible to detect those references and the offsets are adjusted to
211 // their real location.
213 //===----------------------------------------------------------------------===//
215 void MipsRegisterInfo::adjustMipsStackFrame(MachineFunction &MF) const
217 MachineFrameInfo *MFI = MF.getFrameInfo();
218 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
219 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
220 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
222 // Min and Max CSI FrameIndex.
223 int MinCSFI = -1, MaxCSFI = -1;
225 // See the description at MipsMachineFunction.h
226 int TopCPUSavedRegOff = -1, TopFPUSavedRegOff = -1;
228 // Replace the dummy '0' SPOffset by the negative offsets, as explained on
229 // LowerFORMAL_ARGUMENTS. Leaving '0' for while is necessary to avoid
230 // the approach done by calculateFrameObjectOffsets to the stack frame.
231 MipsFI->adjustLoadArgsFI(MFI);
232 MipsFI->adjustStoreVarArgsFI(MFI);
234 // It happens that the default stack frame allocation order does not directly
235 // map to the convention used for mips. So we must fix it. We move the callee
236 // save register slots after the local variables area, as described in the
237 // stack frame above.
238 unsigned CalleeSavedAreaSize = 0;
240 MinCSFI = CSI[0].getFrameIdx();
241 MaxCSFI = CSI[CSI.size()-1].getFrameIdx();
243 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
244 CalleeSavedAreaSize += MFI->getObjectAlignment(CSI[i].getFrameIdx());
246 // Adjust local variables. They should come on the stack right
247 // after the arguments.
248 int LastOffsetFI = -1;
249 for (int i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) {
250 if (i >= MinCSFI && i <= MaxCSFI)
252 if (MFI->isDeadObjectIndex(i))
254 unsigned Offset = MFI->getObjectOffset(i) - CalleeSavedAreaSize;
255 if (LastOffsetFI == -1)
257 if (Offset > MFI->getObjectOffset(LastOffsetFI))
259 MFI->setObjectOffset(i, Offset);
262 // Adjust CPU Callee Saved Registers Area. Registers RA and FP must
263 // be saved in this CPU Area there is the need. This whole Area must
264 // be aligned to the default Stack Alignment requirements.
265 unsigned StackOffset = 0;
266 unsigned RegSize = Subtarget.isGP32bit() ? 4 : 8;
268 if (LastOffsetFI >= 0)
269 StackOffset = MFI->getObjectOffset(LastOffsetFI)+
270 MFI->getObjectAlignment(LastOffsetFI);
271 StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
273 for (unsigned i = 0, e = CSI.size(); i != e ; ++i) {
274 if (CSI[i].getRegClass() != Mips::CPURegsRegisterClass)
276 MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
277 TopCPUSavedRegOff = StackOffset;
278 StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
282 MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize),
284 MipsFI->setFPStackOffset(StackOffset);
285 TopCPUSavedRegOff = StackOffset;
286 StackOffset += RegSize;
289 if (MFI->hasCalls()) {
290 MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize),
292 MipsFI->setRAStackOffset(StackOffset);
293 TopCPUSavedRegOff = StackOffset;
294 StackOffset += RegSize;
296 StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
298 // Adjust FPU Callee Saved Registers Area. This Area must be
299 // aligned to the default Stack Alignment requirements.
300 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
301 if (CSI[i].getRegClass() == Mips::CPURegsRegisterClass)
303 MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
304 TopFPUSavedRegOff = StackOffset;
305 StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
307 StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
310 MFI->setStackSize(StackOffset);
312 // Recalculate the final tops offset. The final values must be '0'
313 // if there isn't a callee saved register for CPU or FPU, otherwise
314 // a negative offset is needed.
315 if (TopCPUSavedRegOff >= 0)
316 MipsFI->setCPUTopSavedRegOff(TopCPUSavedRegOff-StackOffset);
318 if (TopFPUSavedRegOff >= 0)
319 MipsFI->setFPUTopSavedRegOff(TopFPUSavedRegOff-StackOffset);
322 // hasFP - Return true if the specified function should have a dedicated frame
323 // pointer register. This is true if the function has variable sized allocas or
324 // if frame pointer elimination is disabled.
325 bool MipsRegisterInfo::
326 hasFP(const MachineFunction &MF) const {
327 const MachineFrameInfo *MFI = MF.getFrameInfo();
328 return NoFramePointerElim || MFI->hasVarSizedObjects();
331 // This function eliminate ADJCALLSTACKDOWN,
332 // ADJCALLSTACKUP pseudo instructions
333 void MipsRegisterInfo::
334 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
335 MachineBasicBlock::iterator I) const {
336 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
340 // FrameIndex represent objects inside a abstract stack.
341 // We must replace FrameIndex with an stack/frame pointer
343 void MipsRegisterInfo::
344 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
345 RegScavenger *RS) const
347 MachineInstr &MI = *II;
348 MachineFunction &MF = *MI.getParent()->getParent();
351 while (!MI.getOperand(i).isFI()) {
353 assert(i < MI.getNumOperands() &&
354 "Instr doesn't have FrameIndex operand!");
358 DOUT << "\nFunction : " << MF.getFunction()->getName() << "\n";
359 DOUT << "<--------->\n";
363 int FrameIndex = MI.getOperand(i).getIndex();
364 int stackSize = MF.getFrameInfo()->getStackSize();
365 int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
368 DOUT << "FrameIndex : " << FrameIndex << "\n";
369 DOUT << "spOffset : " << spOffset << "\n";
370 DOUT << "stackSize : " << stackSize << "\n";
373 // as explained on LowerFORMAL_ARGUMENTS, detect negative offsets
374 // and adjust SPOffsets considering the final stack size.
375 int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
376 Offset += MI.getOperand(i-1).getImm();
379 DOUT << "Offset : " << Offset << "\n";
380 DOUT << "<--------->\n";
383 MI.getOperand(i-1).ChangeToImmediate(Offset);
384 MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
387 void MipsRegisterInfo::
388 emitPrologue(MachineFunction &MF) const
390 MachineBasicBlock &MBB = MF.front();
391 MachineFrameInfo *MFI = MF.getFrameInfo();
392 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
393 MachineBasicBlock::iterator MBBI = MBB.begin();
394 DebugLoc dl = (MBBI != MBB.end() ?
395 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
396 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
398 // Get the right frame order for Mips.
399 adjustMipsStackFrame(MF);
401 // Get the number of bytes to allocate from the FrameInfo.
402 unsigned StackSize = MFI->getStackSize();
404 // No need to allocate space on the stack.
405 if (StackSize == 0 && !MFI->hasCalls()) return;
407 int FPOffset = MipsFI->getFPStackOffset();
408 int RAOffset = MipsFI->getRAStackOffset();
410 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER));
412 // TODO: check need from GP here.
413 if (isPIC && Subtarget.isABI_O32())
414 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD)).addReg(getPICCallReg());
415 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
417 // Adjust stack : addi sp, sp, (-imm)
418 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
419 .addReg(Mips::SP).addImm(-StackSize);
421 // Save the return address only if the function isnt a leaf one.
422 // sw $ra, stack_loc($sp)
423 if (MFI->hasCalls()) {
424 BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
425 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
428 // if framepointer enabled, save it and set it
429 // to point to the stack pointer
431 // sw $fp,stack_loc($sp)
432 BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
433 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
436 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::FP)
437 .addReg(Mips::SP).addReg(Mips::ZERO);
440 // PIC speficic function prologue
441 if ((isPIC) && (MFI->hasCalls())) {
442 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE))
443 .addImm(MipsFI->getGPStackOffset());
447 void MipsRegisterInfo::
448 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
450 MachineBasicBlock::iterator MBBI = prior(MBB.end());
451 MachineFrameInfo *MFI = MF.getFrameInfo();
452 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
453 DebugLoc dl = MBBI->getDebugLoc();
455 // Get the number of bytes from FrameInfo
456 int NumBytes = (int) MFI->getStackSize();
458 // Get the FI's where RA and FP are saved.
459 int FPOffset = MipsFI->getFPStackOffset();
460 int RAOffset = MipsFI->getRAStackOffset();
462 // if framepointer enabled, restore it and restore the
466 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::SP)
467 .addReg(Mips::FP).addReg(Mips::ZERO);
469 // lw $fp,stack_loc($sp)
470 BuildMI(MBB, MBBI, dl, TII.get(Mips::LW))
471 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
474 // Restore the return address only if the function isnt a leaf one.
475 // lw $ra, stack_loc($sp)
476 if (MFI->hasCalls()) {
477 BuildMI(MBB, MBBI, dl, TII.get(Mips::LW))
478 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
481 // adjust stack : insert addi sp, sp, (imm)
483 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
484 .addReg(Mips::SP).addImm(NumBytes);
489 void MipsRegisterInfo::
490 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
491 // Set the SPOffset on the FI where GP must be saved/loaded.
492 MachineFrameInfo *MFI = MF.getFrameInfo();
493 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
494 if (MFI->hasCalls() && isPIC) {
495 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
496 MFI->setObjectOffset(MipsFI->getGPFI(), MipsFI->getGPStackOffset());
500 unsigned MipsRegisterInfo::
501 getRARegister() const {
505 unsigned MipsRegisterInfo::
506 getFrameRegister(MachineFunction &MF) const {
507 return hasFP(MF) ? Mips::FP : Mips::SP;
510 unsigned MipsRegisterInfo::
511 getEHExceptionRegister() const {
512 assert(0 && "What is the exception register");
516 unsigned MipsRegisterInfo::
517 getEHHandlerRegister() const {
518 assert(0 && "What is the exception handler register");
522 int MipsRegisterInfo::
523 getDwarfRegNum(unsigned RegNum, bool isEH) const {
524 assert(0 && "What is the dwarf register number");
528 #include "MipsGenRegisterInfo.inc"