1 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-reg-info"
17 #include "MipsRegisterInfo.h"
18 #include "MipsMachineFunction.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Type.h"
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/ValueTypes.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineLocation.h"
27 #include "llvm/Target/TargetFrameInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/STLExtras.h"
35 //#include "MipsSubtarget.h"
39 // TODO: add subtarget support
40 MipsRegisterInfo::MipsRegisterInfo(const TargetInstrInfo &tii)
41 : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
44 /// getRegisterNumbering - Given the enum value for some register, e.g.
45 /// Mips::RA, return the number that it corresponds to (e.g. 31).
46 unsigned MipsRegisterInfo::
47 getRegisterNumbering(unsigned RegEnum)
50 case Mips::ZERO : return 0;
51 case Mips::AT : return 1;
52 case Mips::V0 : return 2;
53 case Mips::V1 : return 3;
54 case Mips::A0 : return 4;
55 case Mips::A1 : return 5;
56 case Mips::A2 : return 6;
57 case Mips::A3 : return 7;
58 case Mips::T0 : return 8;
59 case Mips::T1 : return 9;
60 case Mips::T2 : return 10;
61 case Mips::T3 : return 11;
62 case Mips::T4 : return 12;
63 case Mips::T5 : return 13;
64 case Mips::T6 : return 14;
65 case Mips::T7 : return 15;
66 case Mips::T8 : return 16;
67 case Mips::T9 : return 17;
68 case Mips::S0 : return 18;
69 case Mips::S1 : return 19;
70 case Mips::S2 : return 20;
71 case Mips::S3 : return 21;
72 case Mips::S4 : return 22;
73 case Mips::S5 : return 23;
74 case Mips::S6 : return 24;
75 case Mips::S7 : return 25;
76 case Mips::K0 : return 26;
77 case Mips::K1 : return 27;
78 case Mips::GP : return 28;
79 case Mips::SP : return 29;
80 case Mips::FP : return 30;
81 case Mips::RA : return 31;
82 default: assert(0 && "Unknown register number!");
84 return 0; // Not reached
87 //===----------------------------------------------------------------------===//
89 // Callee Saved Registers methods
91 //===----------------------------------------------------------------------===//
93 /// Mips Callee Saved Registers
94 const unsigned* MipsRegisterInfo::
95 getCalleeSavedRegs(const MachineFunction *MF) const
97 // Mips calle-save register range is $16-$26(s0-s7)
98 static const unsigned CalleeSavedRegs[] = {
99 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
100 Mips::S4, Mips::S5, Mips::S6, Mips::S7, 0
102 return CalleeSavedRegs;
105 /// Mips Callee Saved Register Classes
106 const TargetRegisterClass* const*
107 MipsRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
109 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
110 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
111 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
112 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
113 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, 0
115 return CalleeSavedRegClasses;
118 BitVector MipsRegisterInfo::
119 getReservedRegs(const MachineFunction &MF) const
121 BitVector Reserved(getNumRegs());
122 Reserved.set(Mips::ZERO);
123 Reserved.set(Mips::AT);
124 Reserved.set(Mips::K0);
125 Reserved.set(Mips::K1);
126 Reserved.set(Mips::GP);
127 Reserved.set(Mips::SP);
128 Reserved.set(Mips::FP);
129 Reserved.set(Mips::RA);
133 //===----------------------------------------------------------------------===//
135 // Stack Frame Processing methods
136 // +----------------------------+
138 // The stack is allocated decrementing the stack pointer on
139 // the first instruction of a function prologue. Once decremented,
140 // all stack referencesare are done thought a positive offset
141 // from the stack/frame pointer, so the stack is considering
142 // to grow up! Otherwise terrible hacks would have to be made
143 // to get this stack ABI compliant :)
145 // The stack frame required by the ABI:
150 // . saved $GP (used in PIC - not supported yet)
152 // . saved "Callee Saved" Registers
155 // StackSize -----------
157 // Offset - offset from sp after stack allocation on function prologue
159 // The sp is the stack pointer subtracted/added from the stack size
160 // at the Prologue/Epilogue
162 // References to the previous stack (to obtain arguments) are done
163 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
166 // - reference to the actual stack frame
167 // for any local area var there is smt like : FI >= 0, StackOffset: 4
170 // - reference to previous stack frame
171 // suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
172 // The emitted instruction will be something like:
173 // lw REGX, 16+StackSize(SP)
175 // Since the total stack size is unknown on LowerFORMAL_ARGUMENTS, all
176 // stack references (ObjectOffset) created to reference the function
177 // arguments, are negative numbers. This way, on eliminateFrameIndex it's
178 // possible to detect those references and the offsets are adjusted to
179 // their real location.
183 //===----------------------------------------------------------------------===//
185 // hasFP - Return true if the specified function should have a dedicated frame
186 // pointer register. This is true if the function has variable sized allocas or
187 // if frame pointer elimination is disabled.
188 bool MipsRegisterInfo::
189 hasFP(const MachineFunction &MF) const {
190 return (NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects());
193 // This function eliminate ADJCALLSTACKDOWN,
194 // ADJCALLSTACKUP pseudo instructions
195 void MipsRegisterInfo::
196 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
197 MachineBasicBlock::iterator I) const {
198 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
202 // FrameIndex represent objects inside a abstract stack.
203 // We must replace FrameIndex with an stack/frame pointer
205 void MipsRegisterInfo::
206 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
207 RegScavenger *RS) const
209 MachineInstr &MI = *II;
210 MachineFunction &MF = *MI.getParent()->getParent();
213 while (!MI.getOperand(i).isFrameIndex()) {
215 assert(i < MI.getNumOperands() &&
216 "Instr doesn't have FrameIndex operand!");
219 int FrameIndex = MI.getOperand(i).getIndex();
220 int stackSize = MF.getFrameInfo()->getStackSize();
221 int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
224 DOUT << "\nFunction : " << MF.getFunction()->getName() << "\n";
225 DOUT << "<--------->\n";
227 DOUT << "FrameIndex : " << FrameIndex << "\n";
228 DOUT << "spOffset : " << spOffset << "\n";
229 DOUT << "stackSize : " << stackSize << "\n";
232 // as explained on LowerFORMAL_ARGUMENTS, detect negative offsets
233 // and adjust SPOffsets considering the final stack size.
234 int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
235 Offset += MI.getOperand(i-1).getImm();
238 DOUT << "Offset : " << Offset << "\n";
239 DOUT << "<--------->\n";
242 MI.getOperand(i-1).ChangeToImmediate(Offset);
243 MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
246 void MipsRegisterInfo::
247 emitPrologue(MachineFunction &MF) const
249 MachineBasicBlock &MBB = MF.front();
250 MachineFrameInfo *MFI = MF.getFrameInfo();
251 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
252 MachineBasicBlock::iterator MBBI = MBB.begin();
253 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
255 // Replace the dummy '0' SPOffset by the negative
256 // offsets, as explained on LowerFORMAL_ARGUMENTS
257 MipsFI->adjustLoadArgsFI(MFI);
258 MipsFI->adjustStoreVarArgsFI(MFI);
260 // Get the number of bytes to allocate from the FrameInfo.
261 int NumBytes = (int) MFI->getStackSize();
264 DOUT << "\n<--- EMIT PROLOGUE --->\n";
265 DOUT << "Actual Stack size :" << NumBytes << "\n";
268 // No need to allocate space on the stack.
269 if (NumBytes == 0) return;
271 int FPOffset, RAOffset;
273 // Allocate space for saved RA and FP when needed
274 if ((hasFP(MF)) && (MFI->hasCalls())) {
276 RAOffset = (NumBytes+4);
278 } else if ((!hasFP(MF)) && (MFI->hasCalls())) {
282 } else if ((hasFP(MF)) && (!MFI->hasCalls())) {
287 // No calls and no fp.
288 RAOffset = FPOffset = 0;
291 MFI->setObjectOffset(MFI->CreateStackObject(4,4), FPOffset);
292 MFI->setObjectOffset(MFI->CreateStackObject(4,4), RAOffset);
293 MipsFI->setFPStackOffset(FPOffset);
294 MipsFI->setRAStackOffset(RAOffset);
297 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
298 NumBytes = ((NumBytes+Align-1)/Align*Align);
301 DOUT << "FPOffset :" << FPOffset << "\n";
302 DOUT << "RAOffset :" << RAOffset << "\n";
303 DOUT << "New stack size :" << NumBytes << "\n\n";
307 MFI->setStackSize(NumBytes);
309 // PIC speficic function prologue
311 BuildMI(MBB, MBBI, TII.get(Mips::CPLOAD)).addReg(Mips::T9);
313 // Adjust stack : addi sp, sp, (-imm)
314 BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
315 .addReg(Mips::SP).addImm(-NumBytes);
317 // Save the return address only if the function isnt a leaf one.
318 // sw $ra, stack_loc($sp)
319 if (MFI->hasCalls()) {
320 BuildMI(MBB, MBBI, TII.get(Mips::SW))
321 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
324 // if framepointer enabled, save it and set it
325 // to point to the stack pointer
327 // sw $fp,stack_loc($sp)
328 BuildMI(MBB, MBBI, TII.get(Mips::SW))
329 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
332 BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::FP)
333 .addReg(Mips::SP).addReg(Mips::ZERO);
336 // PIC speficic function prologue
337 if ((isPIC) && (MFI->hasCalls()))
338 BuildMI(MBB, MBBI, TII.get(Mips::CPRESTORE))
339 .addImm(MipsFI->getGPStackOffset());
342 void MipsRegisterInfo::
343 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
345 MachineBasicBlock::iterator MBBI = prior(MBB.end());
346 MachineFrameInfo *MFI = MF.getFrameInfo();
347 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
349 // Get the number of bytes from FrameInfo
350 int NumBytes = (int) MFI->getStackSize();
352 // Get the FI's where RA and FP are saved.
353 int FPOffset = MipsFI->getFPStackOffset();
354 int RAOffset = MipsFI->getRAStackOffset();
356 // if framepointer enabled, restore it and restore the
360 BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::SP)
361 .addReg(Mips::FP).addReg(Mips::ZERO);
363 // lw $fp,stack_loc($sp)
364 BuildMI(MBB, MBBI, TII.get(Mips::LW))
365 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
368 // Restore the return address only if the function isnt a leaf one.
369 // lw $ra, stack_loc($sp)
370 if (MFI->hasCalls()) {
371 BuildMI(MBB, MBBI, TII.get(Mips::LW))
372 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
375 // adjust stack : insert addi sp, sp, (imm)
377 BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
378 .addReg(Mips::SP).addImm(NumBytes);
382 void MipsRegisterInfo::
383 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
384 // Set the SPOffset on the FI where GP must be saved/loaded.
385 MachineFrameInfo *MFI = MF.getFrameInfo();
386 if (MFI->hasCalls()) {
387 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
389 DOUT << "processFunctionBeforeFrameFinalized\n";
390 DOUT << "GPOffset :" << MipsFI->getGPStackOffset() << "\n";
391 DOUT << "FI :" << MipsFI->getGPFI() << "\n";
393 MFI->setObjectOffset(MipsFI->getGPFI(), MipsFI->getGPStackOffset());
397 unsigned MipsRegisterInfo::
398 getRARegister() const {
402 unsigned MipsRegisterInfo::
403 getFrameRegister(MachineFunction &MF) const {
404 return hasFP(MF) ? Mips::FP : Mips::SP;
407 unsigned MipsRegisterInfo::
408 getEHExceptionRegister() const {
409 assert(0 && "What is the exception register");
413 unsigned MipsRegisterInfo::
414 getEHHandlerRegister() const {
415 assert(0 && "What is the exception handler register");
419 int MipsRegisterInfo::
420 getDwarfRegNum(unsigned RegNum, bool isEH) const {
421 assert(0 && "What is the dwarf register number");
425 #include "MipsGenRegisterInfo.inc"