1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-reg-info"
16 #include "MipsRegisterInfo.h"
18 #include "MipsAnalyzeImmediate.h"
19 #include "MipsInstrInfo.h"
20 #include "MipsMachineFunction.h"
21 #include "MipsSubtarget.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/ValueTypes.h"
28 #include "llvm/Constants.h"
29 #include "llvm/DebugInfo.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Type.h"
40 #define GET_REGINFO_TARGET_DESC
41 #include "MipsGenRegisterInfo.inc"
45 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST)
46 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {}
48 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
50 //===----------------------------------------------------------------------===//
51 // Callee Saved Registers methods
52 //===----------------------------------------------------------------------===//
54 /// Mips Callee Saved Registers
55 const uint16_t* MipsRegisterInfo::
56 getCalleeSavedRegs(const MachineFunction *MF) const {
57 if (Subtarget.isSingleFloat())
58 return CSR_SingleFloatOnly_SaveList;
59 else if (!Subtarget.hasMips64())
60 return CSR_O32_SaveList;
61 else if (Subtarget.isABI_N32())
62 return CSR_N32_SaveList;
64 assert(Subtarget.isABI_N64());
65 return CSR_N64_SaveList;
69 MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
70 if (Subtarget.isSingleFloat())
71 return CSR_SingleFloatOnly_RegMask;
72 else if (!Subtarget.hasMips64())
73 return CSR_O32_RegMask;
74 else if (Subtarget.isABI_N32())
75 return CSR_N32_RegMask;
77 assert(Subtarget.isABI_N64());
78 return CSR_N64_RegMask;
81 BitVector MipsRegisterInfo::
82 getReservedRegs(const MachineFunction &MF) const {
83 static const uint16_t ReservedCPURegs[] = {
84 Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
87 static const uint16_t ReservedCPU64Regs[] = {
88 Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
91 BitVector Reserved(getNumRegs());
92 typedef TargetRegisterClass::const_iterator RegIter;
94 for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I)
95 Reserved.set(ReservedCPURegs[I]);
97 for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I)
98 Reserved.set(ReservedCPU64Regs[I]);
100 if (Subtarget.hasMips64()) {
101 // Reserve all registers in AFGR64.
102 for (RegIter Reg = Mips::AFGR64RegClass.begin(),
103 EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
106 // Reserve all registers in FGR64.
107 for (RegIter Reg = Mips::FGR64RegClass.begin(),
108 EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
111 // Reserve FP if this function should have a dedicated frame pointer register.
112 if (MF.getTarget().getFrameLowering()->hasFP(MF)) {
113 if (Subtarget.inMips16Mode())
114 Reserved.set(Mips::S0);
116 Reserved.set(Mips::FP);
117 Reserved.set(Mips::FP_64);
121 // Reserve hardware registers.
122 Reserved.set(Mips::HWR29);
123 Reserved.set(Mips::HWR29_64);
125 // Reserve DSP control register.
126 Reserved.set(Mips::DSPCtrl);
128 // Reserve RA if in mips16 mode.
129 if (Subtarget.inMips16Mode()) {
130 Reserved.set(Mips::RA);
131 Reserved.set(Mips::RA_64);
134 // Reserve GP if small section is used.
135 if (Subtarget.useSmallSection()) {
136 Reserved.set(Mips::GP);
137 Reserved.set(Mips::GP_64);
144 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
149 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
153 // FrameIndex represent objects inside a abstract stack.
154 // We must replace FrameIndex with an stack/frame pointer
156 void MipsRegisterInfo::
157 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
158 RegScavenger *RS) const {
159 MachineInstr &MI = *II;
160 MachineFunction &MF = *MI.getParent()->getParent();
163 while (!MI.getOperand(i).isFI()) {
165 assert(i < MI.getNumOperands() &&
166 "Instr doesn't have FrameIndex operand!");
169 DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
170 errs() << "<--------->\n" << MI);
172 int FrameIndex = MI.getOperand(i).getIndex();
173 uint64_t stackSize = MF.getFrameInfo()->getStackSize();
174 int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
176 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
177 << "spOffset : " << spOffset << "\n"
178 << "stackSize : " << stackSize << "\n");
180 eliminateFI(MI, i, FrameIndex, stackSize, spOffset);
183 unsigned MipsRegisterInfo::
184 getFrameRegister(const MachineFunction &MF) const {
185 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
186 bool IsN64 = Subtarget.isABI_N64();
188 if (Subtarget.inMips16Mode())
189 return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
191 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
192 (IsN64 ? Mips::SP_64 : Mips::SP);
196 unsigned MipsRegisterInfo::
197 getEHExceptionRegister() const {
198 llvm_unreachable("What is the exception register");
201 unsigned MipsRegisterInfo::
202 getEHHandlerRegister() const {
203 llvm_unreachable("What is the exception handler register");