1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-reg-info"
16 #include "MipsRegisterInfo.h"
18 #include "MipsAnalyzeImmediate.h"
19 #include "MipsInstrInfo.h"
20 #include "MipsSubtarget.h"
21 #include "MipsMachineFunction.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DebugInfo.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/Target/TargetFrameLowering.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
40 #define GET_REGINFO_TARGET_DESC
41 #include "MipsGenRegisterInfo.inc"
45 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
46 const TargetInstrInfo &tii)
47 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {}
49 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
51 //===----------------------------------------------------------------------===//
52 // Callee Saved Registers methods
53 //===----------------------------------------------------------------------===//
55 /// Mips Callee Saved Registers
56 const uint16_t* MipsRegisterInfo::
57 getCalleeSavedRegs(const MachineFunction *MF) const {
58 if (Subtarget.isSingleFloat())
59 return CSR_SingleFloatOnly_SaveList;
60 else if (!Subtarget.hasMips64())
61 return CSR_O32_SaveList;
62 else if (Subtarget.isABI_N32())
63 return CSR_N32_SaveList;
65 assert(Subtarget.isABI_N64());
66 return CSR_N64_SaveList;
70 MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
71 if (Subtarget.isSingleFloat())
72 return CSR_SingleFloatOnly_RegMask;
73 else if (!Subtarget.hasMips64())
74 return CSR_O32_RegMask;
75 else if (Subtarget.isABI_N32())
76 return CSR_N32_RegMask;
78 assert(Subtarget.isABI_N64());
79 return CSR_N64_RegMask;
82 BitVector MipsRegisterInfo::
83 getReservedRegs(const MachineFunction &MF) const {
84 static const uint16_t ReservedCPURegs[] = {
85 Mips::ZERO, Mips::AT, Mips::K0, Mips::K1, Mips::SP
88 static const uint16_t ReservedCPU64Regs[] = {
89 Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
92 BitVector Reserved(getNumRegs());
93 typedef TargetRegisterClass::const_iterator RegIter;
95 for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I)
96 Reserved.set(ReservedCPURegs[I]);
98 if (Subtarget.hasMips64()) {
99 for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I)
100 Reserved.set(ReservedCPU64Regs[I]);
102 // Reserve all registers in AFGR64.
103 for (RegIter Reg = Mips::AFGR64RegClass.begin(),
104 EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
107 // Reserve all registers in CPU64Regs & FGR64.
108 for (RegIter Reg = Mips::CPU64RegsRegClass.begin(),
109 EReg = Mips::CPU64RegsRegClass.end(); Reg != EReg; ++Reg)
112 for (RegIter Reg = Mips::FGR64RegClass.begin(),
113 EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
117 // Reserve FP if this function should have a dedicated frame pointer register.
118 if (MF.getTarget().getFrameLowering()->hasFP(MF)) {
119 Reserved.set(Mips::FP);
120 Reserved.set(Mips::FP_64);
123 // Reserve hardware registers.
124 Reserved.set(Mips::HWR29);
125 Reserved.set(Mips::HWR29_64);
127 // Reserve RA if in mips16 mode.
128 if (Subtarget.inMips16Mode()) {
129 Reserved.set(Mips::RA);
130 Reserved.set(Mips::RA_64);
133 // Reserve GP if small section is used.
134 if (Subtarget.useSmallSection()) {
135 Reserved.set(Mips::GP);
136 Reserved.set(Mips::GP_64);
143 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
148 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
152 // FrameIndex represent objects inside a abstract stack.
153 // We must replace FrameIndex with an stack/frame pointer
155 void MipsRegisterInfo::
156 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
157 RegScavenger *RS) const {
158 MachineInstr &MI = *II;
159 MachineFunction &MF = *MI.getParent()->getParent();
162 while (!MI.getOperand(i).isFI()) {
164 assert(i < MI.getNumOperands() &&
165 "Instr doesn't have FrameIndex operand!");
168 DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
169 errs() << "<--------->\n" << MI);
171 int FrameIndex = MI.getOperand(i).getIndex();
172 uint64_t stackSize = MF.getFrameInfo()->getStackSize();
173 int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
175 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
176 << "spOffset : " << spOffset << "\n"
177 << "stackSize : " << stackSize << "\n");
179 eliminateFI(MI, i, FrameIndex, stackSize, spOffset);
182 unsigned MipsRegisterInfo::
183 getFrameRegister(const MachineFunction &MF) const {
184 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
185 bool IsN64 = Subtarget.isABI_N64();
187 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
188 (IsN64 ? Mips::SP_64 : Mips::SP);
191 unsigned MipsRegisterInfo::
192 getEHExceptionRegister() const {
193 llvm_unreachable("What is the exception register");
196 unsigned MipsRegisterInfo::
197 getEHHandlerRegister() const {
198 llvm_unreachable("What is the exception handler register");