1 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-reg-info"
17 #include "MipsSubtarget.h"
18 #include "MipsRegisterInfo.h"
19 #include "MipsMachineFunction.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Type.h"
22 #include "llvm/Function.h"
23 #include "llvm/CodeGen/ValueTypes.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/Target/TargetFrameLowering.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/ADT/BitVector.h"
36 #include "llvm/ADT/STLExtras.h"
37 #include "llvm/Analysis/DebugInfo.h"
39 #define GET_REGINFO_TARGET_DESC
40 #include "MipsGenRegisterInfo.inc"
44 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
45 const TargetInstrInfo &tii)
46 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {}
48 /// getRegisterNumbering - Given the enum value for some register, e.g.
49 /// Mips::RA, return the number that it corresponds to (e.g. 31).
50 unsigned MipsRegisterInfo::
51 getRegisterNumbering(unsigned RegEnum)
54 case Mips::ZERO: case Mips::ZERO_64: case Mips::F0: case Mips::D0_64:
57 case Mips::AT: case Mips::AT_64: case Mips::F1: case Mips::D1_64:
59 case Mips::V0: case Mips::V0_64: case Mips::F2: case Mips::D2_64:
62 case Mips::V1: case Mips::V1_64: case Mips::F3: case Mips::D3_64:
64 case Mips::A0: case Mips::A0_64: case Mips::F4: case Mips::D4_64:
67 case Mips::A1: case Mips::A1_64: case Mips::F5: case Mips::D5_64:
69 case Mips::A2: case Mips::A2_64: case Mips::F6: case Mips::D6_64:
72 case Mips::A3: case Mips::A3_64: case Mips::F7: case Mips::D7_64:
74 case Mips::T0: case Mips::T0_64: case Mips::F8: case Mips::D8_64:
77 case Mips::T1: case Mips::T1_64: case Mips::F9: case Mips::D9_64:
79 case Mips::T2: case Mips::T2_64: case Mips::F10: case Mips::D10_64:
82 case Mips::T3: case Mips::T3_64: case Mips::F11: case Mips::D11_64:
84 case Mips::T4: case Mips::T4_64: case Mips::F12: case Mips::D12_64:
87 case Mips::T5: case Mips::T5_64: case Mips::F13: case Mips::D13_64:
89 case Mips::T6: case Mips::T6_64: case Mips::F14: case Mips::D14_64:
92 case Mips::T7: case Mips::T7_64: case Mips::F15: case Mips::D15_64:
94 case Mips::S0: case Mips::S0_64: case Mips::F16: case Mips::D16_64:
97 case Mips::S1: case Mips::S1_64: case Mips::F17: case Mips::D17_64:
99 case Mips::S2: case Mips::S2_64: case Mips::F18: case Mips::D18_64:
102 case Mips::S3: case Mips::S3_64: case Mips::F19: case Mips::D19_64:
104 case Mips::S4: case Mips::S4_64: case Mips::F20: case Mips::D20_64:
107 case Mips::S5: case Mips::S5_64: case Mips::F21: case Mips::D21_64:
109 case Mips::S6: case Mips::S6_64: case Mips::F22: case Mips::D22_64:
112 case Mips::S7: case Mips::S7_64: case Mips::F23: case Mips::D23_64:
114 case Mips::T8: case Mips::T8_64: case Mips::F24: case Mips::D24_64:
117 case Mips::T9: case Mips::T9_64: case Mips::F25: case Mips::D25_64:
119 case Mips::K0: case Mips::K0_64: case Mips::F26: case Mips::D26_64:
122 case Mips::K1: case Mips::K1_64: case Mips::F27: case Mips::D27_64:
124 case Mips::GP: case Mips::GP_64: case Mips::F28: case Mips::D28_64:
127 case Mips::SP: case Mips::SP_64: case Mips::F29: case Mips::D29_64:
130 case Mips::FP: case Mips::FP_64: case Mips::F30: case Mips::D30_64:
133 case Mips::RA: case Mips::RA_64: case Mips::F31: case Mips::D31_64:
135 default: llvm_unreachable("Unknown register number!");
137 return 0; // Not reached
140 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
142 //===----------------------------------------------------------------------===//
143 // Callee Saved Registers methods
144 //===----------------------------------------------------------------------===//
146 /// Mips Callee Saved Registers
147 const unsigned* MipsRegisterInfo::
148 getCalleeSavedRegs(const MachineFunction *MF) const
150 // Mips callee-save register range is $16-$23, $f20-$f30
151 static const unsigned SingleFloatOnlyCalleeSavedRegs[] = {
152 Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26,
153 Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20,
154 Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4,
155 Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0
158 static const unsigned Mips32CalleeSavedRegs[] = {
159 Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10,
160 Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4,
161 Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0
164 static const unsigned N32CalleeSavedRegs[] = {
165 Mips::D31_64, Mips::D29_64, Mips::D27_64, Mips::D25_64, Mips::D23_64,
167 Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64,
168 Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64,
172 static const unsigned N64CalleeSavedRegs[] = {
173 Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64,
174 Mips::D26_64, Mips::D25_64, Mips::D24_64,
175 Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64,
176 Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64,
180 if (Subtarget.isSingleFloat())
181 return SingleFloatOnlyCalleeSavedRegs;
182 else if (!Subtarget.hasMips64())
183 return Mips32CalleeSavedRegs;
184 else if (Subtarget.isABI_N32())
185 return N32CalleeSavedRegs;
187 assert(Subtarget.isABI_N64());
188 return N64CalleeSavedRegs;
191 BitVector MipsRegisterInfo::
192 getReservedRegs(const MachineFunction &MF) const {
193 static const unsigned ReservedCPURegs[] = {
194 Mips::ZERO, Mips::AT, Mips::K0, Mips::K1,
195 Mips::GP, Mips::SP, Mips::FP, Mips::RA
198 static const unsigned ReservedCPU64Regs[] = {
199 Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64,
200 Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64
203 BitVector Reserved(getNumRegs());
204 typedef TargetRegisterClass::iterator RegIter;
206 for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I)
207 Reserved.set(ReservedCPURegs[I]);
209 if (Subtarget.hasMips64()) {
210 for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I)
211 Reserved.set(ReservedCPU64Regs[I]);
213 // Reserve all registers in AFGR64.
214 for (RegIter Reg = Mips::AFGR64RegisterClass->begin();
215 Reg != Mips::AFGR64RegisterClass->end(); ++Reg)
219 // Reserve all registers in CPU64Regs & FGR64.
220 for (RegIter Reg = Mips::CPU64RegsRegisterClass->begin();
221 Reg != Mips::CPU64RegsRegisterClass->end(); ++Reg)
224 for (RegIter Reg = Mips::FGR64RegisterClass->begin();
225 Reg != Mips::FGR64RegisterClass->end(); ++Reg)
232 // This function eliminate ADJCALLSTACKDOWN,
233 // ADJCALLSTACKUP pseudo instructions
234 void MipsRegisterInfo::
235 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
236 MachineBasicBlock::iterator I) const {
237 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
241 // FrameIndex represent objects inside a abstract stack.
242 // We must replace FrameIndex with an stack/frame pointer
244 void MipsRegisterInfo::
245 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
246 RegScavenger *RS) const {
247 MachineInstr &MI = *II;
248 MachineFunction &MF = *MI.getParent()->getParent();
249 MachineFrameInfo *MFI = MF.getFrameInfo();
250 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
253 while (!MI.getOperand(i).isFI()) {
255 assert(i < MI.getNumOperands() &&
256 "Instr doesn't have FrameIndex operand!");
259 DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n";
260 errs() << "<--------->\n" << MI);
262 int FrameIndex = MI.getOperand(i).getIndex();
263 int stackSize = MF.getFrameInfo()->getStackSize();
264 int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
266 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
267 << "spOffset : " << spOffset << "\n"
268 << "stackSize : " << stackSize << "\n");
270 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
275 MinCSFI = CSI[0].getFrameIdx();
276 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
279 // The following stack frame objects are always referenced relative to $sp:
280 // 1. Outgoing arguments.
281 // 2. Pointer to dynamically allocated stack space.
282 // 3. Locations for callee-saved registers.
283 // Everything else is referenced relative to whatever register
284 // getFrameRegister() returns.
287 if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) ||
288 (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI))
289 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
291 FrameReg = getFrameRegister(MF);
293 // Calculate final offset.
294 // - There is no need to change the offset if the frame object is one of the
295 // following: an outgoing argument, pointer to a dynamically allocated
296 // stack space or a $gp restore location,
297 // - If the frame object is any of the following, its offset must be adjusted
298 // by adding the size of the stack:
299 // incoming argument, callee-saved register location or local variable.
302 if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex) ||
303 MipsFI->isDynAllocFI(FrameIndex))
306 Offset = spOffset + stackSize;
308 Offset += MI.getOperand(i+1).getImm();
310 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
312 // If MI is not a debug value, make sure Offset fits in the 16-bit immediate
314 if (!MI.isDebugValue() && (Offset >= 0x8000 || Offset < -0x8000)) {
315 MachineBasicBlock &MBB = *MI.getParent();
316 DebugLoc DL = II->getDebugLoc();
317 int ImmHi = (((unsigned)Offset & 0xffff0000) >> 16) +
318 ((Offset & 0x8000) != 0);
320 // FIXME: change this when mips goes MC".
321 BuildMI(MBB, II, DL, TII.get(Mips::NOAT));
322 BuildMI(MBB, II, DL, TII.get(Mips::LUi), Mips::AT).addImm(ImmHi);
323 BuildMI(MBB, II, DL, TII.get(Mips::ADDu), Mips::AT).addReg(FrameReg)
326 Offset = (short)(Offset & 0xffff);
328 BuildMI(MBB, ++II, MI.getDebugLoc(), TII.get(Mips::ATMACRO));
331 MI.getOperand(i).ChangeToRegister(FrameReg, false);
332 MI.getOperand(i+1).ChangeToImmediate(Offset);
335 unsigned MipsRegisterInfo::
336 getFrameRegister(const MachineFunction &MF) const {
337 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
338 bool IsN64 = Subtarget.isABI_N64();
340 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
341 (IsN64 ? Mips::SP_64 : Mips::SP);
344 unsigned MipsRegisterInfo::
345 getEHExceptionRegister() const {
346 llvm_unreachable("What is the exception register");
350 unsigned MipsRegisterInfo::
351 getEHHandlerRegister() const {
352 llvm_unreachable("What is the exception handler register");