1 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-reg-info"
17 #include "MipsSubtarget.h"
18 #include "MipsRegisterInfo.h"
19 #include "MipsMachineFunction.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Type.h"
22 #include "llvm/Function.h"
23 #include "llvm/CodeGen/ValueTypes.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineLocation.h"
28 #include "llvm/Target/TargetFrameInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/ADT/BitVector.h"
37 #include "llvm/ADT/STLExtras.h"
41 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
42 const TargetInstrInfo &tii)
43 : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
44 Subtarget(ST), TII(tii) {}
46 /// getRegisterNumbering - Given the enum value for some register, e.g.
47 /// Mips::RA, return the number that it corresponds to (e.g. 31).
48 unsigned MipsRegisterInfo::
49 getRegisterNumbering(unsigned RegEnum)
52 case Mips::ZERO : case Mips::F0 : case Mips::D0 : return 0;
53 case Mips::AT : case Mips::F1 : return 1;
54 case Mips::V0 : case Mips::F2 : case Mips::D1 : return 2;
55 case Mips::V1 : case Mips::F3 : return 3;
56 case Mips::A0 : case Mips::F4 : case Mips::D2 : return 4;
57 case Mips::A1 : case Mips::F5 : return 5;
58 case Mips::A2 : case Mips::F6 : case Mips::D3 : return 6;
59 case Mips::A3 : case Mips::F7 : return 7;
60 case Mips::T0 : case Mips::F8 : case Mips::D4 : return 8;
61 case Mips::T1 : case Mips::F9 : return 9;
62 case Mips::T2 : case Mips::F10: case Mips::D5: return 10;
63 case Mips::T3 : case Mips::F11: return 11;
64 case Mips::T4 : case Mips::F12: case Mips::D6: return 12;
65 case Mips::T5 : case Mips::F13: return 13;
66 case Mips::T6 : case Mips::F14: case Mips::D7: return 14;
67 case Mips::T7 : case Mips::F15: return 15;
68 case Mips::T8 : case Mips::F16: case Mips::D8: return 16;
69 case Mips::T9 : case Mips::F17: return 17;
70 case Mips::S0 : case Mips::F18: case Mips::D9: return 18;
71 case Mips::S1 : case Mips::F19: return 19;
72 case Mips::S2 : case Mips::F20: case Mips::D10: return 20;
73 case Mips::S3 : case Mips::F21: return 21;
74 case Mips::S4 : case Mips::F22: case Mips::D11: return 22;
75 case Mips::S5 : case Mips::F23: return 23;
76 case Mips::S6 : case Mips::F24: case Mips::D12: return 24;
77 case Mips::S7 : case Mips::F25: return 25;
78 case Mips::K0 : case Mips::F26: case Mips::D13: return 26;
79 case Mips::K1 : case Mips::F27: return 27;
80 case Mips::GP : case Mips::F28: case Mips::D14: return 28;
81 case Mips::SP : case Mips::F29: return 29;
82 case Mips::FP : case Mips::F30: case Mips::D15: return 30;
83 case Mips::RA : case Mips::F31: return 31;
84 default: llvm_unreachable("Unknown register number!");
86 return 0; // Not reached
89 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
91 //===----------------------------------------------------------------------===//
92 // Callee Saved Registers methods
93 //===----------------------------------------------------------------------===//
95 /// Mips Callee Saved Registers
96 const unsigned* MipsRegisterInfo::
97 getCalleeSavedRegs(const MachineFunction *MF) const
99 // Mips callee-save register range is $16-$23, $f20-$f30
100 static const unsigned SingleFloatOnlyCalleeSavedRegs[] = {
101 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
102 Mips::S4, Mips::S5, Mips::S6, Mips::S7,
103 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25,
104 Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, 0
107 static const unsigned BitMode32CalleeSavedRegs[] = {
108 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
109 Mips::S4, Mips::S5, Mips::S6, Mips::S7,
110 Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30, 0
113 if (Subtarget.isSingleFloat())
114 return SingleFloatOnlyCalleeSavedRegs;
116 return BitMode32CalleeSavedRegs;
119 /// Mips Callee Saved Register Classes
120 const TargetRegisterClass* const*
121 MipsRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
123 static const TargetRegisterClass * const SingleFloatOnlyCalleeSavedRC[] = {
124 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
125 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
126 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
127 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
128 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
129 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
130 &Mips::FGR32RegClass, &Mips::FGR32RegClass, 0
133 static const TargetRegisterClass * const BitMode32CalleeSavedRC[] = {
134 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
135 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
136 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
137 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
138 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass, 0
141 if (Subtarget.isSingleFloat())
142 return SingleFloatOnlyCalleeSavedRC;
144 return BitMode32CalleeSavedRC;
147 BitVector MipsRegisterInfo::
148 getReservedRegs(const MachineFunction &MF) const
150 BitVector Reserved(getNumRegs());
151 Reserved.set(Mips::ZERO);
152 Reserved.set(Mips::AT);
153 Reserved.set(Mips::K0);
154 Reserved.set(Mips::K1);
155 Reserved.set(Mips::GP);
156 Reserved.set(Mips::SP);
157 Reserved.set(Mips::FP);
158 Reserved.set(Mips::RA);
160 // SRV4 requires that odd register can't be used.
161 if (!Subtarget.isSingleFloat())
162 for (unsigned FReg=(Mips::F0)+1; FReg < Mips::F30; FReg+=2)
168 //===----------------------------------------------------------------------===//
170 // Stack Frame Processing methods
171 // +----------------------------+
173 // The stack is allocated decrementing the stack pointer on
174 // the first instruction of a function prologue. Once decremented,
175 // all stack references are done thought a positive offset
176 // from the stack/frame pointer, so the stack is considering
177 // to grow up! Otherwise terrible hacks would have to be made
178 // to get this stack ABI compliant :)
180 // The stack frame required by the ABI (after call):
185 // . saved $GP (used in PIC)
186 // . Alloca allocations
188 // . CPU "Callee Saved" Registers
191 // . FPU "Callee Saved" Registers
192 // StackSize -----------
194 // Offset - offset from sp after stack allocation on function prologue
196 // The sp is the stack pointer subtracted/added from the stack size
197 // at the Prologue/Epilogue
199 // References to the previous stack (to obtain arguments) are done
200 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
203 // - reference to the actual stack frame
204 // for any local area var there is smt like : FI >= 0, StackOffset: 4
207 // - reference to previous stack frame
208 // suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
209 // The emitted instruction will be something like:
210 // lw REGX, 16+StackSize(SP)
212 // Since the total stack size is unknown on LowerFormalArguments, all
213 // stack references (ObjectOffset) created to reference the function
214 // arguments, are negative numbers. This way, on eliminateFrameIndex it's
215 // possible to detect those references and the offsets are adjusted to
216 // their real location.
218 //===----------------------------------------------------------------------===//
220 void MipsRegisterInfo::adjustMipsStackFrame(MachineFunction &MF) const
222 MachineFrameInfo *MFI = MF.getFrameInfo();
223 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
224 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
225 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
226 unsigned RegSize = Subtarget.isGP32bit() ? 4 : 8;
227 bool HasGP = MipsFI->needGPSaveRestore();
229 // Min and Max CSI FrameIndex.
230 int MinCSFI = -1, MaxCSFI = -1;
232 // See the description at MipsMachineFunction.h
233 int TopCPUSavedRegOff = -1, TopFPUSavedRegOff = -1;
235 // Replace the dummy '0' SPOffset by the negative offsets, as explained on
236 // LowerFormalArguments. Leaving '0' for while is necessary to avoid
237 // the approach done by calculateFrameObjectOffsets to the stack frame.
238 MipsFI->adjustLoadArgsFI(MFI);
239 MipsFI->adjustStoreVarArgsFI(MFI);
241 // It happens that the default stack frame allocation order does not directly
242 // map to the convention used for mips. So we must fix it. We move the callee
243 // save register slots after the local variables area, as described in the
244 // stack frame above.
245 unsigned CalleeSavedAreaSize = 0;
247 MinCSFI = CSI[0].getFrameIdx();
248 MaxCSFI = CSI[CSI.size()-1].getFrameIdx();
250 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
251 CalleeSavedAreaSize += MFI->getObjectAlignment(CSI[i].getFrameIdx());
253 unsigned StackOffset = HasGP ? (MipsFI->getGPStackOffset()+RegSize)
254 : (Subtarget.isABI_O32() ? 16 : 0);
256 // Adjust local variables. They should come on the stack right
257 // after the arguments.
258 int LastOffsetFI = -1;
259 for (int i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) {
260 if (i >= MinCSFI && i <= MaxCSFI)
262 if (MFI->isDeadObjectIndex(i))
265 StackOffset + MFI->getObjectOffset(i) - CalleeSavedAreaSize;
266 if (LastOffsetFI == -1)
268 if (Offset > MFI->getObjectOffset(LastOffsetFI))
270 MFI->setObjectOffset(i, Offset);
273 // Adjust CPU Callee Saved Registers Area. Registers RA and FP must
274 // be saved in this CPU Area. This whole area must be aligned to the
275 // default Stack Alignment requirements.
276 if (LastOffsetFI >= 0)
277 StackOffset = MFI->getObjectOffset(LastOffsetFI)+
278 MFI->getObjectSize(LastOffsetFI);
279 StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
281 for (unsigned i = 0, e = CSI.size(); i != e ; ++i) {
282 if (CSI[i].getRegClass() != Mips::CPURegsRegisterClass)
284 MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
285 TopCPUSavedRegOff = StackOffset;
286 StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
289 // Stack locations for FP and RA. If only one of them is used,
290 // the space must be allocated for both, otherwise no space at all.
291 if (hasFP(MF) || MFI->hasCalls()) {
293 MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true),
295 MipsFI->setFPStackOffset(StackOffset);
296 TopCPUSavedRegOff = StackOffset;
297 StackOffset += RegSize;
300 MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true),
302 MipsFI->setRAStackOffset(StackOffset);
303 StackOffset += RegSize;
306 TopCPUSavedRegOff += RegSize;
309 StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
311 // Adjust FPU Callee Saved Registers Area. This Area must be
312 // aligned to the default Stack Alignment requirements.
313 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
314 if (CSI[i].getRegClass() == Mips::CPURegsRegisterClass)
316 MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
317 TopFPUSavedRegOff = StackOffset;
318 StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
320 StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
323 MFI->setStackSize(StackOffset);
325 // Recalculate the final tops offset. The final values must be '0'
326 // if there isn't a callee saved register for CPU or FPU, otherwise
327 // a negative offset is needed.
328 if (TopCPUSavedRegOff >= 0)
329 MipsFI->setCPUTopSavedRegOff(TopCPUSavedRegOff-StackOffset);
331 if (TopFPUSavedRegOff >= 0)
332 MipsFI->setFPUTopSavedRegOff(TopFPUSavedRegOff-StackOffset);
335 // hasFP - Return true if the specified function should have a dedicated frame
336 // pointer register. This is true if the function has variable sized allocas or
337 // if frame pointer elimination is disabled.
338 bool MipsRegisterInfo::
339 hasFP(const MachineFunction &MF) const {
340 const MachineFrameInfo *MFI = MF.getFrameInfo();
341 return NoFramePointerElim || MFI->hasVarSizedObjects();
344 // This function eliminate ADJCALLSTACKDOWN,
345 // ADJCALLSTACKUP pseudo instructions
346 void MipsRegisterInfo::
347 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
348 MachineBasicBlock::iterator I) const {
349 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
353 // FrameIndex represent objects inside a abstract stack.
354 // We must replace FrameIndex with an stack/frame pointer
356 unsigned MipsRegisterInfo::
357 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
358 FrameIndexValue *Value, RegScavenger *RS) const
360 MachineInstr &MI = *II;
361 MachineFunction &MF = *MI.getParent()->getParent();
364 while (!MI.getOperand(i).isFI()) {
366 assert(i < MI.getNumOperands() &&
367 "Instr doesn't have FrameIndex operand!");
370 DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n";
371 errs() << "<--------->\n" << MI);
373 int FrameIndex = MI.getOperand(i).getIndex();
374 int stackSize = MF.getFrameInfo()->getStackSize();
375 int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
377 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
378 << "spOffset : " << spOffset << "\n"
379 << "stackSize : " << stackSize << "\n");
381 // as explained on LowerFormalArguments, detect negative offsets
382 // and adjust SPOffsets considering the final stack size.
383 int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
384 Offset += MI.getOperand(i-1).getImm();
386 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
388 MI.getOperand(i-1).ChangeToImmediate(Offset);
389 MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
393 void MipsRegisterInfo::
394 emitPrologue(MachineFunction &MF) const
396 MachineBasicBlock &MBB = MF.front();
397 MachineFrameInfo *MFI = MF.getFrameInfo();
398 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
399 MachineBasicBlock::iterator MBBI = MBB.begin();
400 DebugLoc dl = (MBBI != MBB.end() ?
401 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
402 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
404 // Get the right frame order for Mips.
405 adjustMipsStackFrame(MF);
407 // Get the number of bytes to allocate from the FrameInfo.
408 unsigned StackSize = MFI->getStackSize();
410 // No need to allocate space on the stack.
411 if (StackSize == 0 && !MFI->hasCalls()) return;
413 int FPOffset = MipsFI->getFPStackOffset();
414 int RAOffset = MipsFI->getRAStackOffset();
416 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER));
418 // TODO: check need from GP here.
419 if (isPIC && Subtarget.isABI_O32())
420 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD)).addReg(getPICCallReg());
421 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
423 // Adjust stack : addi sp, sp, (-imm)
424 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
425 .addReg(Mips::SP).addImm(-StackSize);
427 // Save the return address only if the function isnt a leaf one.
428 // sw $ra, stack_loc($sp)
429 if (MFI->hasCalls()) {
430 BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
431 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
434 // if framepointer enabled, save it and set it
435 // to point to the stack pointer
437 // sw $fp,stack_loc($sp)
438 BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
439 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
442 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::FP)
443 .addReg(Mips::SP).addReg(Mips::ZERO);
446 // Restore GP from the saved stack location
447 if (MipsFI->needGPSaveRestore())
448 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE))
449 .addImm(MipsFI->getGPStackOffset());
452 void MipsRegisterInfo::
453 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
455 MachineBasicBlock::iterator MBBI = prior(MBB.end());
456 MachineFrameInfo *MFI = MF.getFrameInfo();
457 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
458 DebugLoc dl = MBBI->getDebugLoc();
460 // Get the number of bytes from FrameInfo
461 int NumBytes = (int) MFI->getStackSize();
463 // Get the FI's where RA and FP are saved.
464 int FPOffset = MipsFI->getFPStackOffset();
465 int RAOffset = MipsFI->getRAStackOffset();
467 // if framepointer enabled, restore it and restore the
471 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::SP)
472 .addReg(Mips::FP).addReg(Mips::ZERO);
474 // lw $fp,stack_loc($sp)
475 BuildMI(MBB, MBBI, dl, TII.get(Mips::LW), Mips::FP)
476 .addImm(FPOffset).addReg(Mips::SP);
479 // Restore the return address only if the function isnt a leaf one.
480 // lw $ra, stack_loc($sp)
481 if (MFI->hasCalls()) {
482 BuildMI(MBB, MBBI, dl, TII.get(Mips::LW), Mips::RA)
483 .addImm(RAOffset).addReg(Mips::SP);
486 // adjust stack : insert addi sp, sp, (imm)
488 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
489 .addReg(Mips::SP).addImm(NumBytes);
494 void MipsRegisterInfo::
495 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
496 // Set the stack offset where GP must be saved/loaded from.
497 MachineFrameInfo *MFI = MF.getFrameInfo();
498 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
499 if (MipsFI->needGPSaveRestore())
500 MFI->setObjectOffset(MipsFI->getGPFI(), MipsFI->getGPStackOffset());
503 unsigned MipsRegisterInfo::
504 getRARegister() const {
508 unsigned MipsRegisterInfo::
509 getFrameRegister(const MachineFunction &MF) const {
510 return hasFP(MF) ? Mips::FP : Mips::SP;
513 unsigned MipsRegisterInfo::
514 getEHExceptionRegister() const {
515 llvm_unreachable("What is the exception register");
519 unsigned MipsRegisterInfo::
520 getEHHandlerRegister() const {
521 llvm_unreachable("What is the exception handler register");
525 int MipsRegisterInfo::
526 getDwarfRegNum(unsigned RegNum, bool isEH) const {
527 llvm_unreachable("What is the dwarf register number");
531 #include "MipsGenRegisterInfo.inc"