1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsRegisterInfo.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsInstrInfo.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/IR/Constants.h"
28 #include "llvm/IR/DebugInfo.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameLowering.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
42 #define DEBUG_TYPE "mips-reg-info"
44 #define GET_REGINFO_TARGET_DESC
45 #include "MipsGenRegisterInfo.inc"
47 MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {}
49 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
51 const TargetRegisterClass *
52 MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
53 unsigned Kind) const {
54 MipsABIInfo ABI = MF.getSubtarget<MipsSubtarget>().getABI();
55 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
59 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
60 MachineFunction &MF) const {
61 switch (RC->getID()) {
64 case Mips::GPR32RegClassID:
65 case Mips::GPR64RegClassID:
66 case Mips::DSPRRegClassID: {
67 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
68 return 28 - TFI->hasFP(MF);
70 case Mips::FGR32RegClassID:
72 case Mips::AFGR64RegClassID:
74 case Mips::FGR64RegClassID:
79 //===----------------------------------------------------------------------===//
80 // Callee Saved Registers methods
81 //===----------------------------------------------------------------------===//
83 /// Mips Callee Saved Registers
85 MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
86 const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
87 if (Subtarget.isSingleFloat())
88 return CSR_SingleFloatOnly_SaveList;
90 if (Subtarget.isABI_N64())
91 return CSR_N64_SaveList;
93 if (Subtarget.isABI_N32())
94 return CSR_N32_SaveList;
96 if (Subtarget.isFP64bit())
97 return CSR_O32_FP64_SaveList;
99 if (Subtarget.isFPXX())
100 return CSR_O32_FPXX_SaveList;
102 return CSR_O32_SaveList;
106 MipsRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
107 CallingConv::ID) const {
108 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
109 if (Subtarget.isSingleFloat())
110 return CSR_SingleFloatOnly_RegMask;
112 if (Subtarget.isABI_N64())
113 return CSR_N64_RegMask;
115 if (Subtarget.isABI_N32())
116 return CSR_N32_RegMask;
118 if (Subtarget.isFP64bit())
119 return CSR_O32_FP64_RegMask;
121 if (Subtarget.isFPXX())
122 return CSR_O32_FPXX_RegMask;
124 return CSR_O32_RegMask;
127 const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
128 return CSR_Mips16RetHelper_RegMask;
131 BitVector MipsRegisterInfo::
132 getReservedRegs(const MachineFunction &MF) const {
133 static const MCPhysReg ReservedGPR32[] = {
134 Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
137 static const MCPhysReg ReservedGPR64[] = {
138 Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
141 BitVector Reserved(getNumRegs());
142 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
143 typedef TargetRegisterClass::const_iterator RegIter;
145 for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
146 Reserved.set(ReservedGPR32[I]);
148 // Reserve registers for the NaCl sandbox.
149 if (Subtarget.isTargetNaCl()) {
150 Reserved.set(Mips::T6); // Reserved for control flow mask.
151 Reserved.set(Mips::T7); // Reserved for memory access mask.
152 Reserved.set(Mips::T8); // Reserved for thread pointer.
155 for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
156 Reserved.set(ReservedGPR64[I]);
158 // For mno-abicalls, GP is a program invariant!
159 if (!Subtarget.isABICalls()) {
160 Reserved.set(Mips::GP);
161 Reserved.set(Mips::GP_64);
164 if (Subtarget.isFP64bit()) {
165 // Reserve all registers in AFGR64.
166 for (RegIter Reg = Mips::AFGR64RegClass.begin(),
167 EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
170 // Reserve all registers in FGR64.
171 for (RegIter Reg = Mips::FGR64RegClass.begin(),
172 EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
175 // Reserve FP if this function should have a dedicated frame pointer register.
176 if (Subtarget.getFrameLowering()->hasFP(MF)) {
177 if (Subtarget.inMips16Mode())
178 Reserved.set(Mips::S0);
180 Reserved.set(Mips::FP);
181 Reserved.set(Mips::FP_64);
183 // Reserve the base register if we need to both realign the stack and
184 // allocate variable-sized objects at runtime. This should test the
185 // same conditions as MipsFrameLowering::hasBP().
186 if (needsStackRealignment(MF) &&
187 MF.getFrameInfo()->hasVarSizedObjects()) {
188 Reserved.set(Mips::S7);
189 Reserved.set(Mips::S7_64);
194 // Reserve hardware registers.
195 Reserved.set(Mips::HWR29);
197 // Reserve DSP control register.
198 Reserved.set(Mips::DSPPos);
199 Reserved.set(Mips::DSPSCount);
200 Reserved.set(Mips::DSPCarry);
201 Reserved.set(Mips::DSPEFI);
202 Reserved.set(Mips::DSPOutFlag);
204 // Reserve MSA control registers.
205 Reserved.set(Mips::MSAIR);
206 Reserved.set(Mips::MSACSR);
207 Reserved.set(Mips::MSAAccess);
208 Reserved.set(Mips::MSASave);
209 Reserved.set(Mips::MSAModify);
210 Reserved.set(Mips::MSARequest);
211 Reserved.set(Mips::MSAMap);
212 Reserved.set(Mips::MSAUnmap);
214 // Reserve RA if in mips16 mode.
215 if (Subtarget.inMips16Mode()) {
216 const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
217 Reserved.set(Mips::RA);
218 Reserved.set(Mips::RA_64);
219 Reserved.set(Mips::T0);
220 Reserved.set(Mips::T1);
221 if (MF.getFunction()->hasFnAttribute("saveS2") || MipsFI->hasSaveS2())
222 Reserved.set(Mips::S2);
225 // Reserve GP if small section is used.
226 if (Subtarget.useSmallSection()) {
227 Reserved.set(Mips::GP);
228 Reserved.set(Mips::GP_64);
231 if (Subtarget.isABI_O32() && !Subtarget.useOddSPReg()) {
232 for (const auto &Reg : Mips::OddSPRegClass)
240 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
245 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
249 // FrameIndex represent objects inside a abstract stack.
250 // We must replace FrameIndex with an stack/frame pointer
252 void MipsRegisterInfo::
253 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
254 unsigned FIOperandNum, RegScavenger *RS) const {
255 MachineInstr &MI = *II;
256 MachineFunction &MF = *MI.getParent()->getParent();
258 DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
259 errs() << "<--------->\n" << MI);
261 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
262 uint64_t stackSize = MF.getFrameInfo()->getStackSize();
263 int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
265 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
266 << "spOffset : " << spOffset << "\n"
267 << "stackSize : " << stackSize << "\n");
269 eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
272 unsigned MipsRegisterInfo::
273 getFrameRegister(const MachineFunction &MF) const {
274 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
275 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
277 static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64();
279 if (Subtarget.inMips16Mode())
280 return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
282 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
283 (IsN64 ? Mips::SP_64 : Mips::SP);
286 bool MipsRegisterInfo::canRealignStack(const MachineFunction &MF) const {
287 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
288 unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64;
289 unsigned BP = Subtarget.isGP32bit() ? Mips::S7 : Mips::S7_64;
291 // Support dynamic stack realignment only for targets with standard encoding.
292 if (!Subtarget.hasStandardEncoding())
295 // We can't perform dynamic stack realignment if we can't reserve the
296 // frame pointer register.
297 if (!MF.getRegInfo().canReserveReg(FP))
300 // We can realign the stack if we know the maximum call frame size and we
301 // don't have variable sized objects.
302 if (Subtarget.getFrameLowering()->hasReservedCallFrame(MF))
305 // We have to reserve the base pointer register in the presence of variable
307 return MF.getRegInfo().canReserveReg(BP);
310 bool MipsRegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
311 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
312 const MachineFrameInfo *MFI = MF.getFrameInfo();
314 bool CanRealign = canRealignStack(MF);
316 // Avoid realigning functions that explicitly do not want to be realigned.
317 // Normally, we should report an error when a function should be dynamically
318 // realigned but also has the attribute no-realign-stack. Unfortunately,
319 // with this attribute, MachineFrameInfo clamps each new object's alignment
320 // to that of the stack's alignment as specified by the ABI. As a result,
321 // the information of whether we have objects with larger alignment
322 // requirement than the stack's alignment is already lost at this point.
323 if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
326 const Function *F = MF.getFunction();
327 if (F->hasFnAttribute(Attribute::StackAlignment)) {
330 DEBUG(dbgs() << "It's not possible to realign the stack of the function: "
331 << F->getName() << "\n");
336 unsigned StackAlignment = Subtarget.getFrameLowering()->getStackAlignment();
337 if (MFI->getMaxAlignment() > StackAlignment) {
340 DEBUG(dbgs() << "It's not possible to realign the stack of the function: "
341 << F->getName() << "\n");