1 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-reg-info"
17 #include "MipsRegisterInfo.h"
18 #include "MipsMachineFunction.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Type.h"
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/ValueTypes.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineLocation.h"
27 #include "llvm/Target/TargetFrameInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/STLExtras.h"
35 //#include "MipsSubtarget.h"
39 // TODO: add subtarget support
40 MipsRegisterInfo::MipsRegisterInfo(const TargetInstrInfo &tii)
41 : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
44 /// getRegisterNumbering - Given the enum value for some register, e.g.
45 /// Mips::RA, return the number that it corresponds to (e.g. 31).
46 unsigned MipsRegisterInfo::
47 getRegisterNumbering(unsigned RegEnum)
50 case Mips::ZERO : return 0;
51 case Mips::AT : return 1;
52 case Mips::V0 : return 2;
53 case Mips::V1 : return 3;
54 case Mips::A0 : return 4;
55 case Mips::A1 : return 5;
56 case Mips::A2 : return 6;
57 case Mips::A3 : return 7;
58 case Mips::T0 : return 8;
59 case Mips::T1 : return 9;
60 case Mips::T2 : return 10;
61 case Mips::T3 : return 11;
62 case Mips::T4 : return 12;
63 case Mips::T5 : return 13;
64 case Mips::T6 : return 14;
65 case Mips::T7 : return 15;
66 case Mips::T8 : return 16;
67 case Mips::T9 : return 17;
68 case Mips::S0 : return 18;
69 case Mips::S1 : return 19;
70 case Mips::S2 : return 20;
71 case Mips::S3 : return 21;
72 case Mips::S4 : return 22;
73 case Mips::S5 : return 23;
74 case Mips::S6 : return 24;
75 case Mips::S7 : return 25;
76 case Mips::K0 : return 26;
77 case Mips::K1 : return 27;
78 case Mips::GP : return 28;
79 case Mips::SP : return 29;
80 case Mips::FP : return 30;
81 case Mips::RA : return 31;
82 default: assert(0 && "Unknown register number!");
84 return 0; // Not reached
87 void MipsRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
88 MachineBasicBlock::iterator I,
90 const MachineInstr *Orig) const
92 MachineInstr *MI = Orig->clone();
93 MI->getOperand(0).setReg(DestReg);
97 //===----------------------------------------------------------------------===//
99 // Callee Saved Registers methods
101 //===----------------------------------------------------------------------===//
103 /// Mips Callee Saved Registers
104 const unsigned* MipsRegisterInfo::
105 getCalleeSavedRegs(const MachineFunction *MF) const
107 // Mips calle-save register range is $16-$26(s0-s7)
108 static const unsigned CalleeSavedRegs[] = {
109 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
110 Mips::S4, Mips::S5, Mips::S6, Mips::S7, 0
112 return CalleeSavedRegs;
115 /// Mips Callee Saved Register Classes
116 const TargetRegisterClass* const*
117 MipsRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
119 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
120 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
121 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
122 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
123 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, 0
125 return CalleeSavedRegClasses;
128 BitVector MipsRegisterInfo::
129 getReservedRegs(const MachineFunction &MF) const
131 BitVector Reserved(getNumRegs());
132 Reserved.set(Mips::ZERO);
133 Reserved.set(Mips::AT);
134 Reserved.set(Mips::K0);
135 Reserved.set(Mips::K1);
136 Reserved.set(Mips::GP);
137 Reserved.set(Mips::SP);
138 Reserved.set(Mips::FP);
139 Reserved.set(Mips::RA);
143 //===----------------------------------------------------------------------===//
145 // Stack Frame Processing methods
146 // +----------------------------+
148 // The stack is allocated decrementing the stack pointer on
149 // the first instruction of a function prologue. Once decremented,
150 // all stack referencesare are done thought a positive offset
151 // from the stack/frame pointer, so the stack is considering
152 // to grow up! Otherwise terrible hacks would have to be made
153 // to get this stack ABI compliant :)
155 // The stack frame required by the ABI:
160 // . saved $GP (used in PIC - not supported yet)
162 // . saved "Callee Saved" Registers
165 // StackSize -----------
167 // Offset - offset from sp after stack allocation on function prologue
169 // The sp is the stack pointer subtracted/added from the stack size
170 // at the Prologue/Epilogue
172 // References to the previous stack (to obtain arguments) are done
173 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
176 // - reference to the actual stack frame
177 // for any local area var there is smt like : FI >= 0, StackOffset: 4
180 // - reference to previous stack frame
181 // suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
182 // The emitted instruction will be something like:
183 // lw REGX, 16+StackSize(SP)
185 // Since the total stack size is unknown on LowerFORMAL_ARGUMENTS, all
186 // stack references (ObjectOffset) created to reference the function
187 // arguments, are negative numbers. This way, on eliminateFrameIndex it's
188 // possible to detect those references and the offsets are adjusted to
189 // their real location.
193 //===----------------------------------------------------------------------===//
195 // hasFP - Return true if the specified function should have a dedicated frame
196 // pointer register. This is true if the function has variable sized allocas or
197 // if frame pointer elimination is disabled.
198 bool MipsRegisterInfo::
199 hasFP(const MachineFunction &MF) const {
200 return (NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects());
203 // This function eliminate ADJCALLSTACKDOWN,
204 // ADJCALLSTACKUP pseudo instructions
205 void MipsRegisterInfo::
206 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
207 MachineBasicBlock::iterator I) const {
208 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
212 // FrameIndex represent objects inside a abstract stack.
213 // We must replace FrameIndex with an stack/frame pointer
215 void MipsRegisterInfo::
216 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
217 RegScavenger *RS) const
219 MachineInstr &MI = *II;
220 MachineFunction &MF = *MI.getParent()->getParent();
223 while (!MI.getOperand(i).isFrameIndex()) {
225 assert(i < MI.getNumOperands() &&
226 "Instr doesn't have FrameIndex operand!");
229 int FrameIndex = MI.getOperand(i).getIndex();
230 int stackSize = MF.getFrameInfo()->getStackSize();
231 int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
234 DOUT << "\nFunction : " << MF.getFunction()->getName() << "\n";
235 DOUT << "<--------->\n";
237 DOUT << "FrameIndex : " << FrameIndex << "\n";
238 DOUT << "spOffset : " << spOffset << "\n";
239 DOUT << "stackSize : " << stackSize << "\n";
242 // as explained on LowerFORMAL_ARGUMENTS, detect negative offsets
243 // and adjust SPOffsets considering the final stack size.
244 int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
245 Offset += MI.getOperand(i-1).getImm();
248 DOUT << "Offset : " << Offset << "\n";
249 DOUT << "<--------->\n";
252 MI.getOperand(i-1).ChangeToImmediate(Offset);
253 MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
256 void MipsRegisterInfo::
257 emitPrologue(MachineFunction &MF) const
259 MachineBasicBlock &MBB = MF.front();
260 MachineFrameInfo *MFI = MF.getFrameInfo();
261 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
262 MachineBasicBlock::iterator MBBI = MBB.begin();
263 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
265 // Replace the dummy '0' SPOffset by the negative
266 // offsets, as explained on LowerFORMAL_ARGUMENTS
267 MipsFI->adjustLoadArgsFI(MFI);
268 MipsFI->adjustStoreVarArgsFI(MFI);
270 // Get the number of bytes to allocate from the FrameInfo.
271 int NumBytes = (int) MFI->getStackSize();
274 DOUT << "\n<--- EMIT PROLOGUE --->\n";
275 DOUT << "Actual Stack size :" << NumBytes << "\n";
278 // No need to allocate space on the stack.
279 if (NumBytes == 0) return;
281 int FPOffset, RAOffset;
283 // Allocate space for saved RA and FP when needed
284 if ((hasFP(MF)) && (MFI->hasCalls())) {
286 RAOffset = (NumBytes+4);
288 } else if ((!hasFP(MF)) && (MFI->hasCalls())) {
292 } else if ((hasFP(MF)) && (!MFI->hasCalls())) {
297 // No calls and no fp.
298 RAOffset = FPOffset = 0;
301 MFI->setObjectOffset(MFI->CreateStackObject(4,4), FPOffset);
302 MFI->setObjectOffset(MFI->CreateStackObject(4,4), RAOffset);
303 MipsFI->setFPStackOffset(FPOffset);
304 MipsFI->setRAStackOffset(RAOffset);
307 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
308 NumBytes = ((NumBytes+Align-1)/Align*Align);
311 DOUT << "FPOffset :" << FPOffset << "\n";
312 DOUT << "RAOffset :" << RAOffset << "\n";
313 DOUT << "New stack size :" << NumBytes << "\n\n";
317 MFI->setStackSize(NumBytes);
319 // PIC speficic function prologue
321 BuildMI(MBB, MBBI, TII.get(Mips::CPLOAD)).addReg(Mips::T9);
323 // Adjust stack : addi sp, sp, (-imm)
324 BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
325 .addReg(Mips::SP).addImm(-NumBytes);
327 // Save the return address only if the function isnt a leaf one.
328 // sw $ra, stack_loc($sp)
329 if (MFI->hasCalls()) {
330 BuildMI(MBB, MBBI, TII.get(Mips::SW))
331 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
334 // if framepointer enabled, save it and set it
335 // to point to the stack pointer
337 // sw $fp,stack_loc($sp)
338 BuildMI(MBB, MBBI, TII.get(Mips::SW))
339 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
342 BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::FP)
343 .addReg(Mips::SP).addReg(Mips::ZERO);
346 // PIC speficic function prologue
347 if ((isPIC) && (MFI->hasCalls()))
348 BuildMI(MBB, MBBI, TII.get(Mips::CPRESTORE))
349 .addImm(MipsFI->getGPStackOffset());
352 void MipsRegisterInfo::
353 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
355 MachineBasicBlock::iterator MBBI = prior(MBB.end());
356 MachineFrameInfo *MFI = MF.getFrameInfo();
357 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
359 // Get the number of bytes from FrameInfo
360 int NumBytes = (int) MFI->getStackSize();
362 // Get the FI's where RA and FP are saved.
363 int FPOffset = MipsFI->getFPStackOffset();
364 int RAOffset = MipsFI->getRAStackOffset();
366 // if framepointer enabled, restore it and restore the
370 BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::SP)
371 .addReg(Mips::FP).addReg(Mips::ZERO);
373 // lw $fp,stack_loc($sp)
374 BuildMI(MBB, MBBI, TII.get(Mips::LW))
375 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
378 // Restore the return address only if the function isnt a leaf one.
379 // lw $ra, stack_loc($sp)
380 if (MFI->hasCalls()) {
381 BuildMI(MBB, MBBI, TII.get(Mips::LW))
382 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
385 // adjust stack : insert addi sp, sp, (imm)
387 BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
388 .addReg(Mips::SP).addImm(NumBytes);
392 void MipsRegisterInfo::
393 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
394 // Set the SPOffset on the FI where GP must be saved/loaded.
395 MachineFrameInfo *MFI = MF.getFrameInfo();
396 if (MFI->hasCalls()) {
397 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
399 DOUT << "processFunctionBeforeFrameFinalized\n";
400 DOUT << "GPOffset :" << MipsFI->getGPStackOffset() << "\n";
401 DOUT << "FI :" << MipsFI->getGPFI() << "\n";
403 MFI->setObjectOffset(MipsFI->getGPFI(), MipsFI->getGPStackOffset());
407 unsigned MipsRegisterInfo::
408 getRARegister() const {
412 unsigned MipsRegisterInfo::
413 getFrameRegister(MachineFunction &MF) const {
414 return hasFP(MF) ? Mips::FP : Mips::SP;
417 unsigned MipsRegisterInfo::
418 getEHExceptionRegister() const {
419 assert(0 && "What is the exception register");
423 unsigned MipsRegisterInfo::
424 getEHHandlerRegister() const {
425 assert(0 && "What is the exception handler register");
429 int MipsRegisterInfo::
430 getDwarfRegNum(unsigned RegNum, bool isEH) const {
431 assert(0 && "What is the dwarf register number");
435 #include "MipsGenRegisterInfo.inc"