1 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-reg-info"
17 #include "MipsRegisterInfo.h"
18 #include "MipsMachineFunction.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Type.h"
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/ValueTypes.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineLocation.h"
27 #include "llvm/Target/TargetFrameInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/STLExtras.h"
35 //#include "MipsSubtarget.h"
39 // TODO: add subtarget support
40 MipsRegisterInfo::MipsRegisterInfo(const TargetInstrInfo &tii)
41 : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
44 /// getRegisterNumbering - Given the enum value for some register, e.g.
45 /// Mips::RA, return the number that it corresponds to (e.g. 31).
46 unsigned MipsRegisterInfo::
47 getRegisterNumbering(unsigned RegEnum)
50 case Mips::ZERO : return 0;
51 case Mips::AT : return 1;
52 case Mips::V0 : return 2;
53 case Mips::V1 : return 3;
54 case Mips::A0 : return 4;
55 case Mips::A1 : return 5;
56 case Mips::A2 : return 6;
57 case Mips::A3 : return 7;
58 case Mips::T0 : return 8;
59 case Mips::T1 : return 9;
60 case Mips::T2 : return 10;
61 case Mips::T3 : return 11;
62 case Mips::T4 : return 12;
63 case Mips::T5 : return 13;
64 case Mips::T6 : return 14;
65 case Mips::T7 : return 15;
66 case Mips::T8 : return 16;
67 case Mips::T9 : return 17;
68 case Mips::S0 : return 18;
69 case Mips::S1 : return 19;
70 case Mips::S2 : return 20;
71 case Mips::S3 : return 21;
72 case Mips::S4 : return 22;
73 case Mips::S5 : return 23;
74 case Mips::S6 : return 24;
75 case Mips::S7 : return 25;
76 case Mips::K0 : return 26;
77 case Mips::K1 : return 27;
78 case Mips::GP : return 28;
79 case Mips::SP : return 29;
80 case Mips::FP : return 30;
81 case Mips::RA : return 31;
82 default: assert(0 && "Unknown register number!");
86 void MipsRegisterInfo::
87 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
88 unsigned SrcReg, bool isKill, int FI,
89 const TargetRegisterClass *RC) const
91 if (RC == Mips::CPURegsRegisterClass)
92 BuildMI(MBB, I, TII.get(Mips::SW)).addReg(SrcReg, false, false, isKill)
93 .addImm(0).addFrameIndex(FI);
95 assert(0 && "Can't store this register to stack slot");
98 void MipsRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
100 SmallVectorImpl<MachineOperand> &Addr,
101 const TargetRegisterClass *RC,
102 SmallVectorImpl<MachineInstr*> &NewMIs) const {
103 if (RC != Mips::CPURegsRegisterClass)
104 assert(0 && "Can't store this register");
105 MachineInstrBuilder MIB = BuildMI(TII.get(Mips::SW))
106 .addReg(SrcReg, false, false, isKill);
107 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
108 MachineOperand &MO = Addr[i];
110 MIB.addReg(MO.getReg());
111 else if (MO.isImmediate())
112 MIB.addImm(MO.getImmedValue());
114 MIB.addFrameIndex(MO.getFrameIndex());
116 NewMIs.push_back(MIB);
120 void MipsRegisterInfo::
121 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
122 unsigned DestReg, int FI,
123 const TargetRegisterClass *RC) const
125 if (RC == Mips::CPURegsRegisterClass)
126 BuildMI(MBB, I, TII.get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
128 assert(0 && "Can't load this register from stack slot");
131 void MipsRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
132 SmallVectorImpl<MachineOperand> &Addr,
133 const TargetRegisterClass *RC,
134 SmallVectorImpl<MachineInstr*> &NewMIs) const {
135 if (RC != Mips::CPURegsRegisterClass)
136 assert(0 && "Can't load this register");
137 MachineInstrBuilder MIB = BuildMI(TII.get(Mips::LW), DestReg);
138 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
139 MachineOperand &MO = Addr[i];
141 MIB.addReg(MO.getReg());
142 else if (MO.isImmediate())
143 MIB.addImm(MO.getImmedValue());
145 MIB.addFrameIndex(MO.getFrameIndex());
147 NewMIs.push_back(MIB);
151 void MipsRegisterInfo::
152 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
153 unsigned DestReg, unsigned SrcReg,
154 const TargetRegisterClass *DestRC,
155 const TargetRegisterClass *SrcRC) const
157 if (DestRC != SrcRC) {
158 cerr << "Not yet supported!";
162 if (DestRC == Mips::CPURegsRegisterClass)
163 BuildMI(MBB, I, TII.get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
166 assert (0 && "Can't copy this register");
169 void MipsRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
170 MachineBasicBlock::iterator I,
172 const MachineInstr *Orig) const
174 MachineInstr *MI = Orig->clone();
175 MI->getOperand(0).setReg(DestReg);
179 MachineInstr *MipsRegisterInfo::
180 foldMemoryOperand(MachineInstr* MI,
181 SmallVectorImpl<unsigned> &Ops, int FI) const
183 if (Ops.size() != 1) return NULL;
185 MachineInstr *NewMI = NULL;
187 switch (MI->getOpcode())
190 if ((MI->getOperand(0).isRegister()) &&
191 (MI->getOperand(1).isRegister()) &&
192 (MI->getOperand(1).getReg() == Mips::ZERO) &&
193 (MI->getOperand(2).isRegister()))
195 if (Ops[0] == 0) // COPY -> STORE
196 NewMI = BuildMI(TII.get(Mips::SW)).addFrameIndex(FI)
197 .addImm(0).addReg(MI->getOperand(2).getReg());
199 NewMI = BuildMI(TII.get(Mips::LW), MI->getOperand(0)
200 .getReg()).addImm(0).addFrameIndex(FI);
206 NewMI->copyKillDeadInfo(MI);
210 //===----------------------------------------------------------------------===//
212 // Callee Saved Registers methods
214 //===----------------------------------------------------------------------===//
216 /// Mips Callee Saved Registers
217 const unsigned* MipsRegisterInfo::
218 getCalleeSavedRegs(const MachineFunction *MF) const
220 // Mips calle-save register range is $16-$26(s0-s7)
221 static const unsigned CalleeSavedRegs[] = {
222 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
223 Mips::S4, Mips::S5, Mips::S6, Mips::S7, 0
225 return CalleeSavedRegs;
228 /// Mips Callee Saved Register Classes
229 const TargetRegisterClass* const*
230 MipsRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
232 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
233 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
234 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
235 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
236 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, 0
238 return CalleeSavedRegClasses;
241 BitVector MipsRegisterInfo::
242 getReservedRegs(const MachineFunction &MF) const
244 BitVector Reserved(getNumRegs());
245 Reserved.set(Mips::ZERO);
246 Reserved.set(Mips::AT);
247 Reserved.set(Mips::K0);
248 Reserved.set(Mips::K1);
249 Reserved.set(Mips::GP);
250 Reserved.set(Mips::SP);
251 Reserved.set(Mips::FP);
252 Reserved.set(Mips::RA);
256 //===----------------------------------------------------------------------===//
258 // Stack Frame Processing methods
259 // +----------------------------+
261 // The stack is allocated decrementing the stack pointer on
262 // the first instruction of a function prologue. Once decremented,
263 // all stack referencesare are done thought a positive offset
264 // from the stack/frame pointer, so the stack is considering
265 // to grow up! Otherwise terrible hacks would have to be made
266 // to get this stack ABI compliant :)
268 // The stack frame required by the ABI:
273 // . saved $GP (used in PIC - not supported yet)
275 // . saved "Callee Saved" Registers
278 // StackSize -----------
280 // Offset - offset from sp after stack allocation on function prologue
282 // The sp is the stack pointer subtracted/added from the stack size
283 // at the Prologue/Epilogue
285 // References to the previous stack (to obtain arguments) are done
286 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
289 // - reference to the actual stack frame
290 // for any local area var there is smt like : FI >= 0, StackOffset: 4
293 // - reference to previous stack frame
294 // suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
295 // The emitted instruction will be something like:
296 // lw REGX, 16+StackSize(SP)
298 // Since the total stack size is unknown on LowerFORMAL_ARGUMENTS, all
299 // stack references (ObjectOffset) created to reference the function
300 // arguments, are negative numbers. This way, on eliminateFrameIndex it's
301 // possible to detect those references and the offsets are adjusted to
302 // their real location.
306 //===----------------------------------------------------------------------===//
308 // hasFP - Return true if the specified function should have a dedicated frame
309 // pointer register. This is true if the function has variable sized allocas or
310 // if frame pointer elimination is disabled.
311 bool MipsRegisterInfo::
312 hasFP(const MachineFunction &MF) const {
313 return (NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects());
316 // This function eliminate ADJCALLSTACKDOWN,
317 // ADJCALLSTACKUP pseudo instructions
318 void MipsRegisterInfo::
319 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
320 MachineBasicBlock::iterator I) const {
321 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
325 // FrameIndex represent objects inside a abstract stack.
326 // We must replace FrameIndex with an stack/frame pointer
328 void MipsRegisterInfo::
329 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
330 RegScavenger *RS) const
332 MachineInstr &MI = *II;
333 MachineFunction &MF = *MI.getParent()->getParent();
336 while (!MI.getOperand(i).isFrameIndex()) {
338 assert(i < MI.getNumOperands() &&
339 "Instr doesn't have FrameIndex operand!");
342 int FrameIndex = MI.getOperand(i).getFrameIndex();
343 int stackSize = MF.getFrameInfo()->getStackSize();
344 int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
347 DOUT << "\nFunction : " << MF.getFunction()->getName() << "\n";
348 DOUT << "<--------->\n";
350 DOUT << "FrameIndex : " << FrameIndex << "\n";
351 DOUT << "spOffset : " << spOffset << "\n";
352 DOUT << "stackSize : " << stackSize << "\n";
355 // as explained on LowerFORMAL_ARGUMENTS, detect negative offsets
356 // and adjust SPOffsets considering the final stack size.
357 int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
358 Offset += MI.getOperand(i-1).getImm();
361 DOUT << "Offset : " << Offset << "\n";
362 DOUT << "<--------->\n";
365 MI.getOperand(i-1).ChangeToImmediate(Offset);
366 MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
369 void MipsRegisterInfo::
370 emitPrologue(MachineFunction &MF) const
372 MachineBasicBlock &MBB = MF.front();
373 MachineFrameInfo *MFI = MF.getFrameInfo();
374 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
375 MachineBasicBlock::iterator MBBI = MBB.begin();
376 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
378 // Replace the dummy '0' SPOffset by the negative
379 // offsets, as explained on LowerFORMAL_ARGUMENTS
380 MipsFI->adjustLoadArgsFI(MFI);
381 MipsFI->adjustStoreVarArgsFI(MFI);
383 // Get the number of bytes to allocate from the FrameInfo.
384 int NumBytes = (int) MFI->getStackSize();
387 DOUT << "\n<--- EMIT PROLOGUE --->\n";
388 DOUT << "Actual Stack size :" << NumBytes << "\n";
391 // No need to allocate space on the stack.
392 if (NumBytes == 0) return;
394 int FPOffset, RAOffset;
396 // Allocate space for saved RA and FP when needed
397 if ((hasFP(MF)) && (MFI->hasCalls())) {
399 RAOffset = (NumBytes+4);
401 } else if ((!hasFP(MF)) && (MFI->hasCalls())) {
405 } else if ((hasFP(MF)) && (!MFI->hasCalls())) {
411 MFI->setObjectOffset(MFI->CreateStackObject(4,4), FPOffset);
412 MFI->setObjectOffset(MFI->CreateStackObject(4,4), RAOffset);
413 MipsFI->setFPStackOffset(FPOffset);
414 MipsFI->setRAStackOffset(RAOffset);
417 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
418 NumBytes = ((NumBytes+Align-1)/Align*Align);
421 DOUT << "FPOffset :" << FPOffset << "\n";
422 DOUT << "RAOffset :" << RAOffset << "\n";
423 DOUT << "New stack size :" << NumBytes << "\n\n";
427 MFI->setStackSize(NumBytes);
429 // PIC speficic function prologue
431 BuildMI(MBB, MBBI, TII.get(Mips::CPLOAD)).addReg(Mips::T9);
433 // Adjust stack : addi sp, sp, (-imm)
434 BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
435 .addReg(Mips::SP).addImm(-NumBytes);
437 // Save the return address only if the function isnt a leaf one.
438 // sw $ra, stack_loc($sp)
439 if (MFI->hasCalls()) {
440 BuildMI(MBB, MBBI, TII.get(Mips::SW))
441 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
444 // if framepointer enabled, save it and set it
445 // to point to the stack pointer
447 // sw $fp,stack_loc($sp)
448 BuildMI(MBB, MBBI, TII.get(Mips::SW))
449 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
452 BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::FP)
453 .addReg(Mips::SP).addReg(Mips::ZERO);
456 // PIC speficic function prologue
457 if ((isPIC) && (MFI->hasCalls()))
458 BuildMI(MBB, MBBI, TII.get(Mips::CPRESTORE))
459 .addImm(MipsFI->getGPStackOffset());
462 void MipsRegisterInfo::
463 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
465 MachineBasicBlock::iterator MBBI = prior(MBB.end());
466 MachineFrameInfo *MFI = MF.getFrameInfo();
467 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
469 // Get the number of bytes from FrameInfo
470 int NumBytes = (int) MFI->getStackSize();
472 // Get the FI's where RA and FP are saved.
473 int FPOffset = MipsFI->getFPStackOffset();
474 int RAOffset = MipsFI->getRAStackOffset();
476 // if framepointer enabled, restore it and restore the
480 BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::SP)
481 .addReg(Mips::FP).addReg(Mips::ZERO);
483 // lw $fp,stack_loc($sp)
484 BuildMI(MBB, MBBI, TII.get(Mips::LW))
485 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
488 // Restore the return address only if the function isnt a leaf one.
489 // lw $ra, stack_loc($sp)
490 if (MFI->hasCalls()) {
491 BuildMI(MBB, MBBI, TII.get(Mips::LW))
492 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
495 // adjust stack : insert addi sp, sp, (imm)
497 BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
498 .addReg(Mips::SP).addImm(NumBytes);
502 void MipsRegisterInfo::
503 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
504 // Set the SPOffset on the FI where GP must be saved/loaded.
505 MachineFrameInfo *MFI = MF.getFrameInfo();
506 if (MFI->hasCalls()) {
507 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
509 DOUT << "processFunctionBeforeFrameFinalized\n";
510 DOUT << "GPOffset :" << MipsFI->getGPStackOffset() << "\n";
511 DOUT << "FI :" << MipsFI->getGPFI() << "\n";
513 MFI->setObjectOffset(MipsFI->getGPFI(), MipsFI->getGPStackOffset());
517 unsigned MipsRegisterInfo::
518 getRARegister() const {
522 unsigned MipsRegisterInfo::
523 getFrameRegister(MachineFunction &MF) const {
524 return hasFP(MF) ? Mips::FP : Mips::SP;
527 unsigned MipsRegisterInfo::
528 getEHExceptionRegister() const {
529 assert(0 && "What is the exception register");
533 unsigned MipsRegisterInfo::
534 getEHHandlerRegister() const {
535 assert(0 && "What is the exception handler register");
539 int MipsRegisterInfo::
540 getDwarfRegNum(unsigned RegNum, bool isEH) const {
541 assert(0 && "What is the dwarf register number");
545 #include "MipsGenRegisterInfo.inc"