1 //===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the MIPS register file
12 //===----------------------------------------------------------------------===//
13 let Namespace = "Mips" in {
14 def sub_32 : SubRegIndex<32>;
15 def sub_64 : SubRegIndex<64>;
16 def sub_lo : SubRegIndex<32>;
17 def sub_hi : SubRegIndex<32, 32>;
18 def sub_dsp16_19 : SubRegIndex<4, 16>;
19 def sub_dsp20 : SubRegIndex<1, 20>;
20 def sub_dsp21 : SubRegIndex<1, 21>;
21 def sub_dsp22 : SubRegIndex<1, 22>;
22 def sub_dsp23 : SubRegIndex<1, 23>;
26 bit isAllocatable = 0;
29 // We have banks of 32 registers each.
30 class MipsReg<bits<16> Enc, string n> : Register<n> {
32 let Namespace = "Mips";
35 class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
36 : RegisterWithSubRegs<n, subregs> {
38 let Namespace = "Mips";
42 class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>;
44 // Mips 64-bit CPU Registers
45 class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs>
46 : MipsRegWithSubRegs<Enc, n, subregs> {
47 let SubRegIndices = [sub_32];
50 // Mips 32-bit FPU Registers
51 class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>;
53 // Mips 64-bit (aliased) FPU Registers
54 class AFPR<bits<16> Enc, string n, list<Register> subregs>
55 : MipsRegWithSubRegs<Enc, n, subregs> {
56 let SubRegIndices = [sub_lo, sub_hi];
57 let CoveredBySubRegs = 1;
60 class AFPR64<bits<16> Enc, string n, list<Register> subregs>
61 : MipsRegWithSubRegs<Enc, n, subregs> {
62 let SubRegIndices = [sub_lo, sub_hi];
63 let CoveredBySubRegs = 1;
66 // Mips 128-bit (aliased) MSA Registers
67 class AFPR128<bits<16> Enc, string n, list<Register> subregs>
68 : MipsRegWithSubRegs<Enc, n, subregs> {
69 let SubRegIndices = [sub_64];
72 // Accumulator Registers
73 class ACCReg<bits<16> Enc, string n, list<Register> subregs>
74 : MipsRegWithSubRegs<Enc, n, subregs> {
75 let SubRegIndices = [sub_lo, sub_hi];
76 let CoveredBySubRegs = 1;
79 // Mips Hardware Registers
80 class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>;
82 //===----------------------------------------------------------------------===//
84 //===----------------------------------------------------------------------===//
86 let Namespace = "Mips" in {
87 // General Purpose Registers
88 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
89 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>;
90 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
91 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
92 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
93 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
94 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
95 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
96 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
97 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
98 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>;
99 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>;
100 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>;
101 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>;
102 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>;
103 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>;
104 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>;
105 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>;
106 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>;
107 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>;
108 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>;
109 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>;
110 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>;
111 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>;
112 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>;
113 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>;
114 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>;
115 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>;
116 def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>;
117 def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>;
118 def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>;
119 def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>;
121 // General Purpose 64-bit Registers
122 def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>;
123 def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>;
124 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>;
125 def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>;
126 def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>;
127 def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>;
128 def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>;
129 def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>;
130 def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>;
131 def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>;
132 def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>;
133 def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>;
134 def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>;
135 def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>;
136 def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>;
137 def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>;
138 def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>;
139 def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>;
140 def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>;
141 def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>;
142 def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>;
143 def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>;
144 def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>;
145 def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>;
146 def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>;
147 def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>;
148 def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>;
149 def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>;
150 def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>;
151 def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>;
152 def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>;
153 def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>;
155 /// Mips Single point precision FPU Registers
157 def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
159 // Higher half of 64-bit FP registers.
161 def F_HI#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
163 /// Mips Double point precision FPU Registers (aliased
164 /// with the single precision to hold 64 bit values)
166 def D#I : AFPR<!shl(I, 1), "f"#!shl(I, 1),
167 [!cast<FPR>("F"#!shl(I, 1)),
168 !cast<FPR>("F"#!add(!shl(I, 1), 1))]>;
170 /// Mips Double point precision FPU Registers in MFP64 mode.
172 def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I), !cast<FPR>("F_HI"#I)]>,
173 DwarfRegNum<[!add(I, 32)]>;
175 /// Mips MSA registers
176 /// MSA and FPU cannot both be present unless the FPU has 64-bit registers
178 def W#I : AFPR128<I, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>,
179 DwarfRegNum<[!add(I, 32)]>;
182 def HI0 : MipsReg<0, "ac0">, DwarfRegNum<[64]>;
183 def HI1 : MipsReg<1, "ac1">, DwarfRegNum<[176]>;
184 def HI2 : MipsReg<2, "ac2">, DwarfRegNum<[178]>;
185 def HI3 : MipsReg<3, "ac3">, DwarfRegNum<[180]>;
186 def LO0 : MipsReg<0, "ac0">, DwarfRegNum<[65]>;
187 def LO1 : MipsReg<1, "ac1">, DwarfRegNum<[177]>;
188 def LO2 : MipsReg<2, "ac2">, DwarfRegNum<[179]>;
189 def LO3 : MipsReg<3, "ac3">, DwarfRegNum<[181]>;
191 let SubRegIndices = [sub_32] in {
192 def HI0_64 : RegisterWithSubRegs<"hi", [HI0]>;
193 def LO0_64 : RegisterWithSubRegs<"lo", [LO0]>;
196 // FP control registers.
198 def FCR#I : MipsReg<#I, ""#I>;
200 // FP condition code registers.
202 def FCC#I : MipsReg<#I, "fcc"#I>;
206 def COP0#I : MipsReg<#I, ""#I>;
210 def COP2#I : MipsReg<#I, ""#I>;
214 def COP3#I : MipsReg<#I, ""#I>;
217 def PC : Register<"pc">;
219 // Hardware registers
220 def HWR0 : MipsReg<0, "hwr_cpunum">;
221 def HWR1 : MipsReg<1, "hwr_synci_step">;
222 def HWR2 : MipsReg<2, "hwr_cc">;
223 def HWR3 : MipsReg<3, "hwr_ccres">;
226 def HWR#I : MipsReg<#I, ""#I>;
230 def AC#I : ACCReg<#I, "ac"#I,
231 [!cast<Register>("LO"#I), !cast<Register>("HI"#I)]>;
233 def AC0_64 : ACCReg<0, "ac0", [LO0_64, HI0_64]>;
235 // DSP-ASE control register fields.
236 def DSPPos : Register<"">;
237 def DSPSCount : Register<"">;
238 def DSPCarry : Register<"">;
239 def DSPEFI : Register<"">;
240 def DSPOutFlag16_19 : Register<"">;
241 def DSPOutFlag20 : Register<"">;
242 def DSPOutFlag21 : Register<"">;
243 def DSPOutFlag22 : Register<"">;
244 def DSPOutFlag23 : Register<"">;
245 def DSPCCond : Register<"">;
247 let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22,
249 def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20,
250 DSPOutFlag21, DSPOutFlag22,
253 // MSA-ASE control registers.
254 def MSAIR : MipsReg<0, "0">;
255 def MSACSR : MipsReg<1, "1">;
256 def MSAAccess : MipsReg<2, "2">;
257 def MSASave : MipsReg<3, "3">;
258 def MSAModify : MipsReg<4, "4">;
259 def MSARequest : MipsReg<5, "5">;
260 def MSAMap : MipsReg<6, "6">;
261 def MSAUnmap : MipsReg<7, "7">;
263 // Octeon multiplier and product registers
264 def MPL0 : MipsReg<0, "mpl0">;
265 def MPL1 : MipsReg<1, "mpl1">;
266 def MPL2 : MipsReg<2, "mpl2">;
267 def P0 : MipsReg<0, "p0">;
268 def P1 : MipsReg<1, "p1">;
269 def P2 : MipsReg<2, "p2">;
273 //===----------------------------------------------------------------------===//
275 //===----------------------------------------------------------------------===//
277 class GPR32Class<list<ValueType> regTypes> :
278 RegisterClass<"Mips", regTypes, 32, (add
281 // Return Values and Arguments
282 V0, V1, A0, A1, A2, A3,
283 // Not preserved across procedure calls
284 T0, T1, T2, T3, T4, T5, T6, T7,
286 S0, S1, S2, S3, S4, S5, S6, S7,
287 // Not preserved across procedure calls
290 K0, K1, GP, SP, FP, RA)>;
292 def GPR32 : GPR32Class<[i32]>;
293 def DSPR : GPR32Class<[v4i8, v2i16]>;
295 def GPRMM16 : RegisterClass<"Mips", [i32], 32, (add
298 // Return Values and Arguments
299 V0, V1, A0, A1, A2, A3)>;
301 def GPRMM16Zero : RegisterClass<"Mips", [i32], 32, (add
306 // Return Values and Arguments
307 V0, V1, A0, A1, A2, A3)>;
309 def GPRMM16MoveP : RegisterClass<"Mips", [i32], 32, (add
314 // Return Values and Arguments
319 def GPR64 : RegisterClass<"Mips", [i64], 64, (add
322 // Return Values and Arguments
323 V0_64, V1_64, A0_64, A1_64, A2_64, A3_64,
324 // Not preserved across procedure calls
325 T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
327 S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64,
328 // Not preserved across procedure calls
331 K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>;
333 def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
334 // Return Values and Arguments
335 V0, V1, A0, A1, A2, A3,
339 def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add
340 // Return Values and Arguments
341 V0, V1, A0, A1, A2, A3,
346 def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable;
348 def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
351 // * FGR64 - 32 64-bit registers
352 // * AFGR64 - 16 32-bit even registers (32-bit FP Mode)
355 // * FGR32 - 16 32-bit even registers
356 // * FGR32 - 32 32-bit registers (single float only mode)
357 def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
359 def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>,
362 def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
363 // Return Values and Arguments
365 // Not preserved across procedure calls
367 // Return Values and Arguments
369 // Not preserved across procedure calls
372 D10, D11, D12, D13, D14, D15)>;
374 def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>;
376 // Used to reserve odd registers when given -mattr=+nooddspreg
377 // FIXME: Remove double precision registers from this set.
378 def OddSP : RegisterClass<"Mips", [f32], 32,
379 (add (decimate (sequence "F%u", 1, 31), 2),
380 (decimate (sequence "F_HI%u", 1, 31), 2),
381 (decimate (sequence "D%u", 1, 15), 2),
382 (decimate (sequence "D%u_64", 1, 31), 2))>,
385 // FP control registers.
386 def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
389 // FP condition code registers.
390 def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>,
393 // MIPS32r6/MIPS64r6 store FPU condition codes in normal FGR registers.
394 // This class allows us to represent this in codegen patterns.
395 def FGRCC : RegisterClass<"Mips", [i32], 32, (sequence "F%u", 0, 31)>;
397 def MSA128B: RegisterClass<"Mips", [v16i8], 128,
398 (sequence "W%u", 0, 31)>;
399 def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128,
400 (sequence "W%u", 0, 31)>;
401 def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128,
402 (sequence "W%u", 0, 31)>;
403 def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128,
404 (sequence "W%u", 0, 31)>;
405 def MSA128WEvens: RegisterClass<"Mips", [v4i32, v4f32], 128,
406 (decimate (sequence "W%u", 0, 31), 2)>;
408 def MSACtrl: RegisterClass<"Mips", [i32], 32, (add
409 MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap)>;
412 def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>;
413 def HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>;
414 def LO32DSP : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>;
415 def HI32DSP : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>;
416 def LO64 : RegisterClass<"Mips", [i64], 64, (add LO0_64)>;
417 def HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>;
419 // Hardware registers
420 def HWRegs : RegisterClass<"Mips", [i32], 32, (sequence "HWR%u", 0, 31)>,
423 // Accumulator Registers
424 def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> {
428 def ACC128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> {
432 def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> {
436 def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;
438 // Coprocessor 0 registers.
439 def COP0 : RegisterClass<"Mips", [i32], 32, (sequence "COP0%u", 0, 31)>,
442 // Coprocessor 2 registers.
443 def COP2 : RegisterClass<"Mips", [i32], 32, (sequence "COP2%u", 0, 31)>,
446 // Coprocessor 3 registers.
447 def COP3 : RegisterClass<"Mips", [i32], 32, (sequence "COP3%u", 0, 31)>,
450 // Octeon multiplier and product registers
451 def OCTEON_MPL : RegisterClass<"Mips", [i64], 64, (add MPL0, MPL1, MPL2)>,
453 def OCTEON_P : RegisterClass<"Mips", [i64], 64, (add P0, P1, P2)>,
456 // Register Operands.
458 class MipsAsmRegOperand : AsmOperandClass {
459 let ParserMethod = "parseAnyRegister";
462 def GPR64AsmOperand : MipsAsmRegOperand {
463 let Name = "GPR64AsmReg";
464 let PredicateMethod = "isGPRAsmReg";
467 def GPR32AsmOperand : MipsAsmRegOperand {
468 let Name = "GPR32AsmReg";
469 let PredicateMethod = "isGPRAsmReg";
472 def GPRMM16AsmOperand : MipsAsmRegOperand {
473 let Name = "GPRMM16AsmReg";
474 let PredicateMethod = "isMM16AsmReg";
477 def GPRMM16AsmOperandZero : MipsAsmRegOperand {
478 let Name = "GPRMM16AsmRegZero";
479 let PredicateMethod = "isMM16AsmRegZero";
482 def GPRMM16AsmOperandMoveP : MipsAsmRegOperand {
483 let Name = "GPRMM16AsmRegMoveP";
484 let PredicateMethod = "isMM16AsmRegMoveP";
487 def ACC64DSPAsmOperand : MipsAsmRegOperand {
488 let Name = "ACC64DSPAsmReg";
489 let PredicateMethod = "isACCAsmReg";
492 def HI32DSPAsmOperand : MipsAsmRegOperand {
493 let Name = "HI32DSPAsmReg";
494 let PredicateMethod = "isACCAsmReg";
497 def LO32DSPAsmOperand : MipsAsmRegOperand {
498 let Name = "LO32DSPAsmReg";
499 let PredicateMethod = "isACCAsmReg";
502 def CCRAsmOperand : MipsAsmRegOperand {
503 let Name = "CCRAsmReg";
506 def AFGR64AsmOperand : MipsAsmRegOperand {
507 let Name = "AFGR64AsmReg";
508 let PredicateMethod = "isFGRAsmReg";
511 def FGR64AsmOperand : MipsAsmRegOperand {
512 let Name = "FGR64AsmReg";
513 let PredicateMethod = "isFGRAsmReg";
516 def FGR32AsmOperand : MipsAsmRegOperand {
517 let Name = "FGR32AsmReg";
518 let PredicateMethod = "isFGRAsmReg";
521 def FGRH32AsmOperand : MipsAsmRegOperand {
522 let Name = "FGRH32AsmReg";
523 let PredicateMethod = "isFGRAsmReg";
526 def FCCRegsAsmOperand : MipsAsmRegOperand {
527 let Name = "FCCAsmReg";
530 def MSA128AsmOperand : MipsAsmRegOperand {
531 let Name = "MSA128AsmReg";
534 def MSACtrlAsmOperand : MipsAsmRegOperand {
535 let Name = "MSACtrlAsmReg";
538 def GPR32Opnd : RegisterOperand<GPR32> {
539 let ParserMatchClass = GPR32AsmOperand;
542 def GPRMM16Opnd : RegisterOperand<GPRMM16> {
543 let ParserMatchClass = GPRMM16AsmOperand;
546 def GPRMM16OpndZero : RegisterOperand<GPRMM16Zero> {
547 let ParserMatchClass = GPRMM16AsmOperandZero;
550 def GPRMM16OpndMoveP : RegisterOperand<GPRMM16MoveP> {
551 let ParserMatchClass = GPRMM16AsmOperandMoveP;
554 def GPR64Opnd : RegisterOperand<GPR64> {
555 let ParserMatchClass = GPR64AsmOperand;
558 def DSPROpnd : RegisterOperand<DSPR> {
559 let ParserMatchClass = GPR32AsmOperand;
562 def CCROpnd : RegisterOperand<CCR> {
563 let ParserMatchClass = CCRAsmOperand;
566 def HWRegsAsmOperand : MipsAsmRegOperand {
567 let Name = "HWRegsAsmReg";
570 def COP0AsmOperand : MipsAsmRegOperand {
571 let Name = "COP0AsmReg";
574 def COP2AsmOperand : MipsAsmRegOperand {
575 let Name = "COP2AsmReg";
578 def COP3AsmOperand : MipsAsmRegOperand {
579 let Name = "COP3AsmReg";
582 def HWRegsOpnd : RegisterOperand<HWRegs> {
583 let ParserMatchClass = HWRegsAsmOperand;
586 def AFGR64Opnd : RegisterOperand<AFGR64> {
587 let ParserMatchClass = AFGR64AsmOperand;
590 def FGR64Opnd : RegisterOperand<FGR64> {
591 let ParserMatchClass = FGR64AsmOperand;
594 def FGR32Opnd : RegisterOperand<FGR32> {
595 let ParserMatchClass = FGR32AsmOperand;
598 def FGRCCOpnd : RegisterOperand<FGRCC> {
599 // The assembler doesn't use register classes so we can re-use
601 let ParserMatchClass = FGR32AsmOperand;
604 def FGRH32Opnd : RegisterOperand<FGRH32> {
605 let ParserMatchClass = FGRH32AsmOperand;
608 def FCCRegsOpnd : RegisterOperand<FCC> {
609 let ParserMatchClass = FCCRegsAsmOperand;
612 def LO32DSPOpnd : RegisterOperand<LO32DSP> {
613 let ParserMatchClass = LO32DSPAsmOperand;
616 def HI32DSPOpnd : RegisterOperand<HI32DSP> {
617 let ParserMatchClass = HI32DSPAsmOperand;
620 def ACC64DSPOpnd : RegisterOperand<ACC64DSP> {
621 let ParserMatchClass = ACC64DSPAsmOperand;
624 def COP0Opnd : RegisterOperand<COP0> {
625 let ParserMatchClass = COP0AsmOperand;
628 def COP2Opnd : RegisterOperand<COP2> {
629 let ParserMatchClass = COP2AsmOperand;
632 def COP3Opnd : RegisterOperand<COP3> {
633 let ParserMatchClass = COP3AsmOperand;
636 def MSA128BOpnd : RegisterOperand<MSA128B> {
637 let ParserMatchClass = MSA128AsmOperand;
640 def MSA128HOpnd : RegisterOperand<MSA128H> {
641 let ParserMatchClass = MSA128AsmOperand;
644 def MSA128WOpnd : RegisterOperand<MSA128W> {
645 let ParserMatchClass = MSA128AsmOperand;
648 def MSA128DOpnd : RegisterOperand<MSA128D> {
649 let ParserMatchClass = MSA128AsmOperand;
652 def MSA128CROpnd : RegisterOperand<MSACtrl> {
653 let ParserMatchClass = MSACtrlAsmOperand;