1 //===- MipsRegisterInfo.td - Mips Register defs -----------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the MIPS register file
12 //===----------------------------------------------------------------------===//
14 // We have banks of 32 registers each.
15 class MipsReg<string n> : Register<n> {
17 let Namespace = "Mips";
20 //===----------------------------------------------------------------------===//
21 // General Purpose Registers
22 //===----------------------------------------------------------------------===//
25 class MipsGPRReg<bits<5> num, string n> : MipsReg<n> {
30 def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>;
31 def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;
32 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
33 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
34 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[5]>;
35 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
36 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
37 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
38 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
39 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
40 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>;
41 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>;
42 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>;
43 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>;
44 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>;
45 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>;
46 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>;
47 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>;
48 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>;
49 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>;
50 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>;
51 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>;
52 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>;
53 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>;
54 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>;
55 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>;
56 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>;
57 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>;
58 def GP : MipsGPRReg< 28, "GP">, DwarfRegNum<[28]>;
59 def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<[29]>;
60 def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<[30]>;
61 def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>;
63 // CPU Registers Class
64 def CPURegs : RegisterClass<"Mips", [i32], 32,
65 // Return Values and Arguments
66 [V0, V1, A0, A1, A2, A3,
67 // Not preserved across procedure calls
68 T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
70 S0, S1, S2, S3, S4, S5, S6, S7,
72 ZERO, AT, K0, K1, GP, SP, FP, RA]>
75 iterator allocation_order_end(const MachineFunction &MF) const;
78 CPURegsClass::iterator
79 CPURegsClass::allocation_order_end(const MachineFunction &MF) const {
80 // The last 8 registers on the list above are reserved
86 //===----------------------------------------------------------------------===//
87 // Floating Point Unit Registers (Single Precision)
88 //===----------------------------------------------------------------------===//
90 /// Mips Single point precision FPU Register Format
91 class MipsFPUReg<bits<5> num, string n> : MipsReg<n> {
95 /// Mips Single point precision FPU Registers
96 def F0 : MipsFPUReg< 0, "F0">, DwarfRegNum<[32]>;
97 def F1 : MipsFPUReg< 1, "F1">, DwarfRegNum<[33]>;
98 def F2 : MipsFPUReg< 2, "F2">, DwarfRegNum<[34]>;
99 def F3 : MipsFPUReg< 3, "F3">, DwarfRegNum<[35]>;
100 def F4 : MipsFPUReg< 4, "F4">, DwarfRegNum<[36]>;
101 def F5 : MipsFPUReg< 5, "F5">, DwarfRegNum<[37]>;
102 def F6 : MipsFPUReg< 6, "F6">, DwarfRegNum<[38]>;
103 def F7 : MipsFPUReg< 7, "F7">, DwarfRegNum<[39]>;
104 def F8 : MipsFPUReg< 8, "F8">, DwarfRegNum<[40]>;
105 def F9 : MipsFPUReg< 9, "F9">, DwarfRegNum<[41]>;
106 def F10 : MipsFPUReg<10, "F10">, DwarfRegNum<[42]>;
107 def F11 : MipsFPUReg<11, "F11">, DwarfRegNum<[43]>;
108 def F12 : MipsFPUReg<12, "F12">, DwarfRegNum<[44]>;
109 def F13 : MipsFPUReg<13, "F13">, DwarfRegNum<[45]>;
110 def F14 : MipsFPUReg<14, "F14">, DwarfRegNum<[46]>;
111 def F15 : MipsFPUReg<15, "F15">, DwarfRegNum<[47]>;
112 def F16 : MipsFPUReg<16, "F16">, DwarfRegNum<[48]>;
113 def F17 : MipsFPUReg<17, "F17">, DwarfRegNum<[49]>;
114 def F18 : MipsFPUReg<18, "F18">, DwarfRegNum<[50]>;
115 def F19 : MipsFPUReg<19, "F19">, DwarfRegNum<[51]>;
116 def F20 : MipsFPUReg<20, "F20">, DwarfRegNum<[52]>;
117 def F21 : MipsFPUReg<21, "F21">, DwarfRegNum<[53]>;
118 def F22 : MipsFPUReg<22, "F22">, DwarfRegNum<[54]>;
119 def F23 : MipsFPUReg<23, "F23">, DwarfRegNum<[55]>;
120 def F24 : MipsFPUReg<24, "F24">, DwarfRegNum<[56]>;
121 def F25 : MipsFPUReg<25, "F25">, DwarfRegNum<[57]>;
122 def F26 : MipsFPUReg<26, "F26">, DwarfRegNum<[58]>;
123 def F27 : MipsFPUReg<27, "F27">, DwarfRegNum<[59]>;
124 def F28 : MipsFPUReg<28, "F28">, DwarfRegNum<[60]>;
125 def F29 : MipsFPUReg<29, "F29">, DwarfRegNum<[61]>;
126 def F30 : MipsFPUReg<30, "F30">, DwarfRegNum<[62]>;
127 def F31 : MipsFPUReg<31, "F31">, DwarfRegNum<[63]>;
129 /// FPU Single Point Precision Registers Class
130 def FPUDRegs : RegisterClass<"Mips", [f32], 32,
131 // Return Values and Arguments
132 [F0, F1, F2, F3, F12, F13, F14, F15,
133 // Not preserved across procedure calls
134 F4, F5, F6, F7, F8, F9, F10, F11, F16, F17, F18, F19,
136 F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
140 let MethodProtos = [{
141 iterator allocation_order_end(const MachineFunction &MF) const;
143 let MethodBodies = [{
144 FPUDRegsClass::iterator
145 FPUDRegsClass::allocation_order_end(const MachineFunction &MF) const {
146 // The last register on the list above is reserved
152 //===----------------------------------------------------------------------===//
153 // Floating Point Unit Registers (Double Precision)
154 //===----------------------------------------------------------------------===//
156 /// Mips Double point precision FPU Register Format
157 class MipsFPUDReg<bits<5> num, string n, list<Register> aliases> : MipsReg<n> {
159 let Aliases = aliases;
162 /// Mips Double point precision FPU Registers (aliased
163 /// with the single precision to hold 64 bit values)
164 def D0 : MipsFPUDReg< 0, "F0", [F0, F1]>, DwarfRegNum<[32]>;
165 def D1 : MipsFPUDReg< 2, "F2", [F2, F3]>, DwarfRegNum<[34]>;
166 def D2 : MipsFPUDReg< 4, "F4", [F4, F5]>, DwarfRegNum<[36]>;
167 def D3 : MipsFPUDReg< 6, "F6", [F6, F7]>, DwarfRegNum<[38]>;
168 def D4 : MipsFPUDReg< 8, "F8", [F8, F9]>, DwarfRegNum<[40]>;
169 def D5 : MipsFPUDReg<10, "F10", [F10, F11]>, DwarfRegNum<[42]>;
170 def D6 : MipsFPUDReg<12, "F12", [F12, F13]>, DwarfRegNum<[44]>;
171 def D7 : MipsFPUDReg<14, "F14", [F14, F15]>, DwarfRegNum<[46]>;
172 def D8 : MipsFPUDReg<16, "F16", [F16, F17]>, DwarfRegNum<[48]>;
173 def D9 : MipsFPUDReg<18, "F18", [F18, F19]>, DwarfRegNum<[50]>;
174 def D10 : MipsFPUDReg<20, "F20", [F20, F21]>, DwarfRegNum<[52]>;
175 def D11 : MipsFPUDReg<22, "F22", [F22, F23]>, DwarfRegNum<[54]>;
176 def D12 : MipsFPUDReg<24, "F24", [F24, F25]>, DwarfRegNum<[56]>;
177 def D13 : MipsFPUDReg<26, "F26", [F26, F27]>, DwarfRegNum<[58]>;
178 def D14 : MipsFPUDReg<28, "F28", [F28, F29]>, DwarfRegNum<[60]>;
179 def D15 : MipsFPUDReg<30, "F30", [F30, F31]>, DwarfRegNum<[62]>;
181 /// FPU Single Point Precision Registers Class
182 def FPURegs : RegisterClass<"Mips", [f32], 32,
183 // Return Values and Arguments
185 // Not preserved across procedure calls
186 D2, D3, D4, D5, D8, D9,
188 D10, D11, D12, D13, D14,
192 let MethodProtos = [{
193 iterator allocation_order_end(const MachineFunction &MF) const;
195 let MethodBodies = [{
196 FPURegsClass::iterator
197 FPURegsClass::allocation_order_end(const MachineFunction &MF) const {
198 // The last register on the list above is reserved