1 //===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the MIPS register file
12 //===----------------------------------------------------------------------===//
13 let Namespace = "Mips" in {
14 def sub_fpeven : SubRegIndex;
15 def sub_fpodd : SubRegIndex;
16 def sub_32 : SubRegIndex;
17 def sub_lo : SubRegIndex;
18 def sub_hi : SubRegIndex;
22 bit isAllocatable = 0;
25 // We have banks of 32 registers each.
26 class MipsReg<bits<16> Enc, string n> : Register<n> {
28 let Namespace = "Mips";
31 class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
32 : RegisterWithSubRegs<n, subregs> {
34 let Namespace = "Mips";
38 class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>;
40 // Mips 64-bit CPU Registers
41 class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs>
42 : MipsRegWithSubRegs<Enc, n, subregs> {
43 let SubRegIndices = [sub_32];
46 // Mips 32-bit FPU Registers
47 class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>;
49 // Mips 64-bit (aliased) FPU Registers
50 class AFPR<bits<16> Enc, string n, list<Register> subregs>
51 : MipsRegWithSubRegs<Enc, n, subregs> {
52 let SubRegIndices = [sub_fpeven, sub_fpodd];
53 let CoveredBySubRegs = 1;
56 class AFPR64<bits<16> Enc, string n, list<Register> subregs>
57 : MipsRegWithSubRegs<Enc, n, subregs> {
58 let SubRegIndices = [sub_32];
61 // Accumulator Registers
62 class ACC<bits<16> Enc, string n, list<Register> subregs>
63 : MipsRegWithSubRegs<Enc, n, subregs> {
64 let SubRegIndices = [sub_lo, sub_hi];
65 let CoveredBySubRegs = 1;
68 // Mips Hardware Registers
69 class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>;
71 //===----------------------------------------------------------------------===//
73 //===----------------------------------------------------------------------===//
75 let Namespace = "Mips" in {
76 // General Purpose Registers
77 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
78 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>;
79 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
80 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
81 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
82 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
83 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
84 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
85 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
86 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
87 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>;
88 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>;
89 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>;
90 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>;
91 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>;
92 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>;
93 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>;
94 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>;
95 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>;
96 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>;
97 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>;
98 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>;
99 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>;
100 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>;
101 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>;
102 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>;
103 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>;
104 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>;
105 def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>;
106 def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>;
107 def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>;
108 def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>;
110 // General Purpose 64-bit Registers
111 def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>;
112 def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>;
113 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>;
114 def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>;
115 def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>;
116 def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>;
117 def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>;
118 def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>;
119 def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>;
120 def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>;
121 def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>;
122 def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>;
123 def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>;
124 def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>;
125 def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>;
126 def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>;
127 def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>;
128 def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>;
129 def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>;
130 def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>;
131 def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>;
132 def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>;
133 def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>;
134 def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>;
135 def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>;
136 def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>;
137 def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>;
138 def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>;
139 def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>;
140 def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>;
141 def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>;
142 def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>;
144 /// Mips Single point precision FPU Registers
145 def F0 : FPR< 0, "f0">, DwarfRegNum<[32]>;
146 def F1 : FPR< 1, "f1">, DwarfRegNum<[33]>;
147 def F2 : FPR< 2, "f2">, DwarfRegNum<[34]>;
148 def F3 : FPR< 3, "f3">, DwarfRegNum<[35]>;
149 def F4 : FPR< 4, "f4">, DwarfRegNum<[36]>;
150 def F5 : FPR< 5, "f5">, DwarfRegNum<[37]>;
151 def F6 : FPR< 6, "f6">, DwarfRegNum<[38]>;
152 def F7 : FPR< 7, "f7">, DwarfRegNum<[39]>;
153 def F8 : FPR< 8, "f8">, DwarfRegNum<[40]>;
154 def F9 : FPR< 9, "f9">, DwarfRegNum<[41]>;
155 def F10 : FPR<10, "f10">, DwarfRegNum<[42]>;
156 def F11 : FPR<11, "f11">, DwarfRegNum<[43]>;
157 def F12 : FPR<12, "f12">, DwarfRegNum<[44]>;
158 def F13 : FPR<13, "f13">, DwarfRegNum<[45]>;
159 def F14 : FPR<14, "f14">, DwarfRegNum<[46]>;
160 def F15 : FPR<15, "f15">, DwarfRegNum<[47]>;
161 def F16 : FPR<16, "f16">, DwarfRegNum<[48]>;
162 def F17 : FPR<17, "f17">, DwarfRegNum<[49]>;
163 def F18 : FPR<18, "f18">, DwarfRegNum<[50]>;
164 def F19 : FPR<19, "f19">, DwarfRegNum<[51]>;
165 def F20 : FPR<20, "f20">, DwarfRegNum<[52]>;
166 def F21 : FPR<21, "f21">, DwarfRegNum<[53]>;
167 def F22 : FPR<22, "f22">, DwarfRegNum<[54]>;
168 def F23 : FPR<23, "f23">, DwarfRegNum<[55]>;
169 def F24 : FPR<24, "f24">, DwarfRegNum<[56]>;
170 def F25 : FPR<25, "f25">, DwarfRegNum<[57]>;
171 def F26 : FPR<26, "f26">, DwarfRegNum<[58]>;
172 def F27 : FPR<27, "f27">, DwarfRegNum<[59]>;
173 def F28 : FPR<28, "f28">, DwarfRegNum<[60]>;
174 def F29 : FPR<29, "f29">, DwarfRegNum<[61]>;
175 def F30 : FPR<30, "f30">, DwarfRegNum<[62]>;
176 def F31 : FPR<31, "f31">, DwarfRegNum<[63]>;
178 /// Mips Double point precision FPU Registers (aliased
179 /// with the single precision to hold 64 bit values)
180 def D0 : AFPR< 0, "f0", [F0, F1]>;
181 def D1 : AFPR< 2, "f2", [F2, F3]>;
182 def D2 : AFPR< 4, "f4", [F4, F5]>;
183 def D3 : AFPR< 6, "f6", [F6, F7]>;
184 def D4 : AFPR< 8, "f8", [F8, F9]>;
185 def D5 : AFPR<10, "f10", [F10, F11]>;
186 def D6 : AFPR<12, "f12", [F12, F13]>;
187 def D7 : AFPR<14, "f14", [F14, F15]>;
188 def D8 : AFPR<16, "f16", [F16, F17]>;
189 def D9 : AFPR<18, "f18", [F18, F19]>;
190 def D10 : AFPR<20, "f20", [F20, F21]>;
191 def D11 : AFPR<22, "f22", [F22, F23]>;
192 def D12 : AFPR<24, "f24", [F24, F25]>;
193 def D13 : AFPR<26, "f26", [F26, F27]>;
194 def D14 : AFPR<28, "f28", [F28, F29]>;
195 def D15 : AFPR<30, "f30", [F30, F31]>;
197 /// Mips Double point precision FPU Registers in MFP64 mode.
198 def D0_64 : AFPR64<0, "f0", [F0]>, DwarfRegNum<[32]>;
199 def D1_64 : AFPR64<1, "f1", [F1]>, DwarfRegNum<[33]>;
200 def D2_64 : AFPR64<2, "f2", [F2]>, DwarfRegNum<[34]>;
201 def D3_64 : AFPR64<3, "f3", [F3]>, DwarfRegNum<[35]>;
202 def D4_64 : AFPR64<4, "f4", [F4]>, DwarfRegNum<[36]>;
203 def D5_64 : AFPR64<5, "f5", [F5]>, DwarfRegNum<[37]>;
204 def D6_64 : AFPR64<6, "f6", [F6]>, DwarfRegNum<[38]>;
205 def D7_64 : AFPR64<7, "f7", [F7]>, DwarfRegNum<[39]>;
206 def D8_64 : AFPR64<8, "f8", [F8]>, DwarfRegNum<[40]>;
207 def D9_64 : AFPR64<9, "f9", [F9]>, DwarfRegNum<[41]>;
208 def D10_64 : AFPR64<10, "f10", [F10]>, DwarfRegNum<[42]>;
209 def D11_64 : AFPR64<11, "f11", [F11]>, DwarfRegNum<[43]>;
210 def D12_64 : AFPR64<12, "f12", [F12]>, DwarfRegNum<[44]>;
211 def D13_64 : AFPR64<13, "f13", [F13]>, DwarfRegNum<[45]>;
212 def D14_64 : AFPR64<14, "f14", [F14]>, DwarfRegNum<[46]>;
213 def D15_64 : AFPR64<15, "f15", [F15]>, DwarfRegNum<[47]>;
214 def D16_64 : AFPR64<16, "f16", [F16]>, DwarfRegNum<[48]>;
215 def D17_64 : AFPR64<17, "f17", [F17]>, DwarfRegNum<[49]>;
216 def D18_64 : AFPR64<18, "f18", [F18]>, DwarfRegNum<[50]>;
217 def D19_64 : AFPR64<19, "f19", [F19]>, DwarfRegNum<[51]>;
218 def D20_64 : AFPR64<20, "f20", [F20]>, DwarfRegNum<[52]>;
219 def D21_64 : AFPR64<21, "f21", [F21]>, DwarfRegNum<[53]>;
220 def D22_64 : AFPR64<22, "f22", [F22]>, DwarfRegNum<[54]>;
221 def D23_64 : AFPR64<23, "f23", [F23]>, DwarfRegNum<[55]>;
222 def D24_64 : AFPR64<24, "f24", [F24]>, DwarfRegNum<[56]>;
223 def D25_64 : AFPR64<25, "f25", [F25]>, DwarfRegNum<[57]>;
224 def D26_64 : AFPR64<26, "f26", [F26]>, DwarfRegNum<[58]>;
225 def D27_64 : AFPR64<27, "f27", [F27]>, DwarfRegNum<[59]>;
226 def D28_64 : AFPR64<28, "f28", [F28]>, DwarfRegNum<[60]>;
227 def D29_64 : AFPR64<29, "f29", [F29]>, DwarfRegNum<[61]>;
228 def D30_64 : AFPR64<30, "f30", [F30]>, DwarfRegNum<[62]>;
229 def D31_64 : AFPR64<31, "f31", [F31]>, DwarfRegNum<[63]>;
232 def HI : Register<"hi">, DwarfRegNum<[64]>;
233 def HI1 : Register<"hi1">, DwarfRegNum<[176]>;
234 def HI2 : Register<"hi2">, DwarfRegNum<[178]>;
235 def HI3 : Register<"hi3">, DwarfRegNum<[180]>;
236 def LO : Register<"lo">, DwarfRegNum<[65]>;
237 def LO1 : Register<"lo1">, DwarfRegNum<[177]>;
238 def LO2 : Register<"lo2">, DwarfRegNum<[179]>;
239 def LO3 : Register<"lo3">, DwarfRegNum<[181]>;
241 let SubRegIndices = [sub_32] in {
242 def HI64 : RegisterWithSubRegs<"hi", [HI]>;
243 def LO64 : RegisterWithSubRegs<"lo", [LO]>;
246 // Status flags register
247 def FCR31 : Register<"31">;
250 def FCC0 : MipsReg<0, "fcc0">;
253 def PC : Register<"pc">;
255 // Hardware register $29
256 def HWR29 : MipsReg<29, "29">;
257 def HWR29_64 : MipsReg<29, "29">;
260 def AC0 : ACC<0, "ac0", [LO, HI]>;
261 def AC1 : ACC<1, "ac1", [LO1, HI1]>;
262 def AC2 : ACC<2, "ac2", [LO2, HI2]>;
263 def AC3 : ACC<3, "ac3", [LO3, HI3]>;
265 def AC0_64 : ACC<0, "ac0", [LO64, HI64]>;
267 def DSPCtrl : Register<"dspctrl">;
270 //===----------------------------------------------------------------------===//
272 //===----------------------------------------------------------------------===//
274 class CPURegsClass<list<ValueType> regTypes> :
275 RegisterClass<"Mips", regTypes, 32, (add
278 // Return Values and Arguments
279 V0, V1, A0, A1, A2, A3,
280 // Not preserved across procedure calls
281 T0, T1, T2, T3, T4, T5, T6, T7,
283 S0, S1, S2, S3, S4, S5, S6, S7,
284 // Not preserved across procedure calls
287 K0, K1, GP, SP, FP, RA)>;
289 def CPURegs : CPURegsClass<[i32]>;
290 def DSPRegs : CPURegsClass<[v4i8, v2i16]>;
292 def CPU64Regs : RegisterClass<"Mips", [i64], 64, (add
295 // Return Values and Arguments
296 V0_64, V1_64, A0_64, A1_64, A2_64, A3_64,
297 // Not preserved across procedure calls
298 T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
300 S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64,
301 // Not preserved across procedure calls
304 K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>;
306 def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
307 // Return Values and Arguments
308 V0, V1, A0, A1, A2, A3,
312 def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable;
314 def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
317 // * FGR64 - 32 64-bit registers
318 // * AFGR64 - 16 32-bit even registers (32-bit FP Mode)
321 // * FGR32 - 16 32-bit even registers
322 // * FGR32 - 32 32-bit registers (single float only mode)
323 def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
325 def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
326 // Return Values and Arguments
328 // Not preserved across procedure calls
330 // Return Values and Arguments
332 // Not preserved across procedure calls
335 D10, D11, D12, D13, D14, D15)>;
337 def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>;
339 // Condition Register for floating point operations
340 def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31,FCC0)>, Unallocatable;
343 def HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>, Unallocatable;
344 def HILO64 : RegisterClass<"Mips", [i64], 64, (add HI64, LO64)>, Unallocatable;
346 // Hardware registers
347 def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable;
348 def HWRegs64 : RegisterClass<"Mips", [i64], 64, (add HWR29_64)>, Unallocatable;
350 // Accumulator Registers
351 def ACRegs : RegisterClass<"Mips", [untyped], 64, (add AC0)> {
355 def ACRegs128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> {
359 def ACRegsDSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> {
363 def CPURegsAsmOperand : AsmOperandClass {
364 let Name = "CPURegsAsm";
365 let ParserMethod = "parseCPURegs";
368 def CPU64RegsAsmOperand : AsmOperandClass {
369 let Name = "CPU64RegsAsm";
370 let ParserMethod = "parseCPU64Regs";
373 def CCRAsmOperand : AsmOperandClass {
375 let ParserMethod = "parseCCRRegs";
378 def CPURegsOpnd : RegisterOperand<CPURegs, "printCPURegs"> {
379 let ParserMatchClass = CPURegsAsmOperand;
382 def CPU64RegsOpnd : RegisterOperand<CPU64Regs, "printCPURegs"> {
383 let ParserMatchClass = CPU64RegsAsmOperand;
386 def CCROpnd : RegisterOperand<CCR, "printCPURegs"> {
387 let ParserMatchClass = CCRAsmOperand;
390 def HWRegsAsmOperand : AsmOperandClass {
391 let Name = "HWRegsAsm";
392 let ParserMethod = "parseHWRegs";
395 def HW64RegsAsmOperand : AsmOperandClass {
396 let Name = "HW64RegsAsm";
397 let ParserMethod = "parseHW64Regs";
400 def HWRegsOpnd : RegisterOperand<HWRegs, "printCPURegs"> {
401 let ParserMatchClass = HWRegsAsmOperand;
404 def HW64RegsOpnd : RegisterOperand<HWRegs64, "printCPURegs"> {
405 let ParserMatchClass = HW64RegsAsmOperand;