1 //===- MipsRegisterInfo.td - Mips Register defs -----------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the MIPS register file
12 //===----------------------------------------------------------------------===//
14 // We have banks of 32 registers each.
15 class MipsReg<string n> : Register<n> {
17 let Namespace = "Mips";
21 class MipsGPRReg<bits<5> num, string n> : MipsReg<n> {
26 def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>;
27 def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;
28 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
29 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
30 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[5]>;
31 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
32 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
33 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
34 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
35 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
36 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>;
37 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>;
38 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>;
39 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>;
40 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>;
41 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>;
42 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>;
43 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>;
44 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>;
45 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>;
46 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>;
47 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>;
48 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>;
49 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>;
50 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>;
51 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>;
52 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>;
53 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>;
54 def GP : MipsGPRReg< 28, "GP">, DwarfRegNum<[28]>;
55 def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<[29]>;
56 def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<[30]>;
57 def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>;
59 // CPU Registers Class
60 def CPURegs : RegisterClass<"Mips", [i32], 32,
61 // Return Values and Arguments
62 [V0, V1, A0, A1, A2, A3,
63 // Not preserved across procedure calls
64 T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
66 S0, S1, S2, S3, S4, S5, S6, S7,
68 ZERO, AT, K0, K1, GP, SP, FP, RA]>
71 iterator allocation_order_end(const MachineFunction &MF) const;
74 CPURegsClass::iterator
75 CPURegsClass::allocation_order_end(const MachineFunction &MF) const {
76 // The last 8 registers on the list above are reserved