1 //===- MipsRegisterInfo.td - Mips Register defs -----------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the MIPS register file
12 //===----------------------------------------------------------------------===//
14 // We have banks of 32 registers each.
15 class MipsReg<string n> : Register<n> {
17 let Namespace = "Mips";
20 class MipsRegWithSubRegs<string n, list<Register> subregs>
21 : RegisterWithSubRegs<n, subregs> {
23 let Namespace = "Mips";
27 class MipsGPRReg<bits<5> num, string n> : MipsReg<n> {
31 // Mips 32-bit FPU Registers
32 class FPR<bits<5> num, string n> : MipsReg<n> {
36 // Mips 64-bit (aliased) FPU Registers
37 class AFPR<bits<5> num, string n, list<Register> subregs>
38 : MipsRegWithSubRegs<n, subregs> {
42 //===----------------------------------------------------------------------===//
44 //===----------------------------------------------------------------------===//
46 let Namespace = "Mips" in {
48 // General Purpose Registers
49 def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>;
50 def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;
51 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
52 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
53 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[5]>;
54 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
55 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
56 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
57 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
58 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
59 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>;
60 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>;
61 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>;
62 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>;
63 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>;
64 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>;
65 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>;
66 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>;
67 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>;
68 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>;
69 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>;
70 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>;
71 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>;
72 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>;
73 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>;
74 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>;
75 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>;
76 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>;
77 def GP : MipsGPRReg< 28, "GP">, DwarfRegNum<[28]>;
78 def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<[29]>;
79 def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<[30]>;
80 def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>;
82 /// Mips Single point precision FPU Registers
83 def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>;
84 def F1 : FPR< 1, "F1">, DwarfRegNum<[33]>;
85 def F2 : FPR< 2, "F2">, DwarfRegNum<[34]>;
86 def F3 : FPR< 3, "F3">, DwarfRegNum<[35]>;
87 def F4 : FPR< 4, "F4">, DwarfRegNum<[36]>;
88 def F5 : FPR< 5, "F5">, DwarfRegNum<[37]>;
89 def F6 : FPR< 6, "F6">, DwarfRegNum<[38]>;
90 def F7 : FPR< 7, "F7">, DwarfRegNum<[39]>;
91 def F8 : FPR< 8, "F8">, DwarfRegNum<[40]>;
92 def F9 : FPR< 9, "F9">, DwarfRegNum<[41]>;
93 def F10 : FPR<10, "F10">, DwarfRegNum<[42]>;
94 def F11 : FPR<11, "F11">, DwarfRegNum<[43]>;
95 def F12 : FPR<12, "F12">, DwarfRegNum<[44]>;
96 def F13 : FPR<13, "F13">, DwarfRegNum<[45]>;
97 def F14 : FPR<14, "F14">, DwarfRegNum<[46]>;
98 def F15 : FPR<15, "F15">, DwarfRegNum<[47]>;
99 def F16 : FPR<16, "F16">, DwarfRegNum<[48]>;
100 def F17 : FPR<17, "F17">, DwarfRegNum<[49]>;
101 def F18 : FPR<18, "F18">, DwarfRegNum<[50]>;
102 def F19 : FPR<19, "F19">, DwarfRegNum<[51]>;
103 def F20 : FPR<20, "F20">, DwarfRegNum<[52]>;
104 def F21 : FPR<21, "F21">, DwarfRegNum<[53]>;
105 def F22 : FPR<22, "F22">, DwarfRegNum<[54]>;
106 def F23 : FPR<23, "F23">, DwarfRegNum<[55]>;
107 def F24 : FPR<24, "F24">, DwarfRegNum<[56]>;
108 def F25 : FPR<25, "F25">, DwarfRegNum<[57]>;
109 def F26 : FPR<26, "F26">, DwarfRegNum<[58]>;
110 def F27 : FPR<27, "F27">, DwarfRegNum<[59]>;
111 def F28 : FPR<28, "F28">, DwarfRegNum<[60]>;
112 def F29 : FPR<29, "F29">, DwarfRegNum<[61]>;
113 def F30 : FPR<30, "F30">, DwarfRegNum<[62]>;
114 def F31 : FPR<31, "F31">, DwarfRegNum<[63]>;
116 /// Mips Double point precision FPU Registers (aliased
117 /// with the single precision to hold 64 bit values)
118 def D0 : AFPR< 0, "F0", [F0, F1]>, DwarfRegNum<[32]>;
119 def D1 : AFPR< 2, "F2", [F2, F3]>, DwarfRegNum<[34]>;
120 def D2 : AFPR< 4, "F4", [F4, F5]>, DwarfRegNum<[36]>;
121 def D3 : AFPR< 6, "F6", [F6, F7]>, DwarfRegNum<[38]>;
122 def D4 : AFPR< 8, "F8", [F8, F9]>, DwarfRegNum<[40]>;
123 def D5 : AFPR<10, "F10", [F10, F11]>, DwarfRegNum<[42]>;
124 def D6 : AFPR<12, "F12", [F12, F13]>, DwarfRegNum<[44]>;
125 def D7 : AFPR<14, "F14", [F14, F15]>, DwarfRegNum<[46]>;
126 def D8 : AFPR<16, "F16", [F16, F17]>, DwarfRegNum<[48]>;
127 def D9 : AFPR<18, "F18", [F18, F19]>, DwarfRegNum<[50]>;
128 def D10 : AFPR<20, "F20", [F20, F21]>, DwarfRegNum<[52]>;
129 def D11 : AFPR<22, "F22", [F22, F23]>, DwarfRegNum<[54]>;
130 def D12 : AFPR<24, "F24", [F24, F25]>, DwarfRegNum<[56]>;
131 def D13 : AFPR<26, "F26", [F26, F27]>, DwarfRegNum<[58]>;
132 def D14 : AFPR<28, "F28", [F28, F29]>, DwarfRegNum<[60]>;
133 def D15 : AFPR<30, "F30", [F30, F31]>, DwarfRegNum<[62]>;
136 def HI : Register<"hi">, DwarfRegNum<[64]>;
137 def LO : Register<"lo">, DwarfRegNum<[65]>;
139 // Status flags register
140 def FCR31 : Register<"31">;
143 //===----------------------------------------------------------------------===//
144 // Subregister Set Definitions
145 //===----------------------------------------------------------------------===//
147 let Namespace = "Mips" in {
148 def sub_fpeven : SubRegIndex { let NumberHack = 1; }
149 def sub_fpodd : SubRegIndex { let NumberHack = 2; }
152 def : SubRegSet<sub_fpeven, [D0, D1, D2, D3, D4, D5, D6, D7,
153 D8, D9, D10, D11, D12, D13, D14, D15],
154 [F0, F2, F4, F6, F8, F10, F12, F14,
155 F16, F18, F20, F22, F24, F26, F28, F30]>;
157 def : SubRegSet<sub_fpodd, [D0, D1, D2, D3, D4, D5, D6, D7,
158 D8, D9, D10, D11, D12, D13, D14, D15],
159 [F1, F3, F5, F7, F9, F11, F13, F15,
160 F17, F19, F21, F23, F25, F27, F29, F31]>;
162 //===----------------------------------------------------------------------===//
164 //===----------------------------------------------------------------------===//
166 def CPURegs : RegisterClass<"Mips", [i32], 32,
167 // Return Values and Arguments
168 [V0, V1, A0, A1, A2, A3,
169 // Not preserved across procedure calls
170 T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
172 S0, S1, S2, S3, S4, S5, S6, S7,
174 ZERO, AT, K0, K1, GP, SP, FP, RA]>
176 let MethodProtos = [{
177 iterator allocation_order_end(const MachineFunction &MF) const;
179 let MethodBodies = [{
180 CPURegsClass::iterator
181 CPURegsClass::allocation_order_end(const MachineFunction &MF) const {
182 // The last 8 registers on the list above are reserved
189 // * FGR64 - 32 64-bit registers
190 // * AFGR64 - 16 32-bit even registers (32-bit FP Mode)
193 // * FGR32 - 16 32-bit even registers
194 // * FGR32 - 32 32-bit registers (single float only mode)
195 def FGR32 : RegisterClass<"Mips", [f32], 32,
196 // Return Values and Arguments
197 [F0, F1, F2, F3, F12, F13, F14, F15,
198 // Not preserved across procedure calls
199 F4, F5, F6, F7, F8, F9, F10, F11, F16, F17, F18, F19,
201 F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
205 let MethodProtos = [{
206 iterator allocation_order_begin(const MachineFunction &MF) const;
207 iterator allocation_order_end(const MachineFunction &MF) const;
209 let MethodBodies = [{
211 static const unsigned MIPS_FGR32[] = {
212 Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F12, Mips::F13,
213 Mips::F14, Mips::F15, Mips::F4, Mips::F5, Mips::F6, Mips::F7,
214 Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F16, Mips::F17,
215 Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23,
216 Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
220 static const unsigned MIPS_SVR4_FGR32[] = {
221 Mips::F0, Mips::F2, Mips::F12, Mips::F14, Mips::F4,
222 Mips::F6, Mips::F8, Mips::F10, Mips::F16, Mips::F18,
223 Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30,
227 FGR32Class::allocation_order_begin(const MachineFunction &MF) const {
228 const TargetMachine &TM = MF.getTarget();
229 const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
231 if (Subtarget.isSingleFloat())
234 return MIPS_SVR4_FGR32;
238 FGR32Class::allocation_order_end(const MachineFunction &MF) const {
239 const TargetMachine &TM = MF.getTarget();
240 const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
242 if (Subtarget.isSingleFloat())
243 return MIPS_FGR32 + (sizeof(MIPS_FGR32) / sizeof(unsigned));
245 return MIPS_SVR4_FGR32 + (sizeof(MIPS_SVR4_FGR32) / sizeof(unsigned));
250 def AFGR64 : RegisterClass<"Mips", [f64], 64,
251 // Return Values and Arguments
253 // Not preserved across procedure calls
254 D2, D3, D4, D5, D8, D9,
256 D10, D11, D12, D13, D14,
260 let SubRegClasses = [(FGR32 sub_fpeven, sub_fpodd)];
261 let MethodProtos = [{
262 iterator allocation_order_end(const MachineFunction &MF) const;
264 let MethodBodies = [{
265 AFGR64Class::iterator
266 AFGR64Class::allocation_order_end(const MachineFunction &MF) const {
267 // The last register on the list above is reserved
273 // Condition Register for floating point operations
274 def CCR : RegisterClass<"Mips", [i32], 32, [FCR31]>;
277 def HILO : RegisterClass<"Mips", [i32], 32, [HI, LO]>;