1 //===-- MipsSEFrameLowering.cpp - Mips32/64 Frame Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips32/64 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsSEFrameLowering.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsSEInstrInfo.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Target/TargetOptions.h"
33 typedef MachineBasicBlock::iterator Iter;
35 /// Helper class to expand pseudos.
38 ExpandPseudo(MachineFunction &MF);
42 bool expandInstr(MachineBasicBlock &MBB, Iter I);
43 void expandLoadCCond(MachineBasicBlock &MBB, Iter I);
44 void expandStoreCCond(MachineBasicBlock &MBB, Iter I);
45 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
46 void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
47 bool expandCopy(MachineBasicBlock &MBB, Iter I);
48 bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned Dst,
49 unsigned Src, unsigned RegSize);
52 MachineRegisterInfo &MRI;
56 ExpandPseudo::ExpandPseudo(MachineFunction &MF_)
57 : MF(MF_), MRI(MF.getRegInfo()) {}
59 bool ExpandPseudo::expand() {
60 bool Expanded = false;
62 for (MachineFunction::iterator BB = MF.begin(), BBEnd = MF.end();
64 for (Iter I = BB->begin(), End = BB->end(); I != End;)
65 Expanded |= expandInstr(*BB, I++);
70 bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
71 switch(I->getOpcode()) {
72 case Mips::LOAD_CCOND_DSP:
73 case Mips::LOAD_CCOND_DSP_P8:
74 expandLoadCCond(MBB, I);
76 case Mips::STORE_CCOND_DSP:
77 case Mips::STORE_CCOND_DSP_P8:
78 expandStoreCCond(MBB, I);
81 case Mips::LOAD_AC64_P8:
82 case Mips::LOAD_AC_DSP:
83 case Mips::LOAD_AC_DSP_P8:
84 expandLoadACC(MBB, I, 4);
86 case Mips::LOAD_AC128:
87 case Mips::LOAD_AC128_P8:
88 expandLoadACC(MBB, I, 8);
90 case Mips::STORE_AC64:
91 case Mips::STORE_AC64_P8:
92 case Mips::STORE_AC_DSP:
93 case Mips::STORE_AC_DSP_P8:
94 expandStoreACC(MBB, I, 4);
96 case Mips::STORE_AC128:
97 case Mips::STORE_AC128_P8:
98 expandStoreACC(MBB, I, 8);
100 case TargetOpcode::COPY:
101 if (!expandCopy(MBB, I))
112 void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) {
116 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
118 const MipsSEInstrInfo &TII =
119 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
120 const MipsRegisterInfo &RegInfo =
121 *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
123 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
124 unsigned VR = MRI.createVirtualRegister(RC);
125 unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
127 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
128 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
129 .addReg(VR, RegState::Kill);
132 void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) {
136 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
138 const MipsSEInstrInfo &TII =
139 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
140 const MipsRegisterInfo &RegInfo =
141 *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
143 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
144 unsigned VR = MRI.createVirtualRegister(RC);
145 unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
147 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
148 .addReg(Src, getKillRegState(I->getOperand(0).isKill()));
149 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
152 void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I,
159 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
161 const MipsSEInstrInfo &TII =
162 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
163 const MipsRegisterInfo &RegInfo =
164 *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
166 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
167 unsigned VR0 = MRI.createVirtualRegister(RC);
168 unsigned VR1 = MRI.createVirtualRegister(RC);
169 unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
170 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
171 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
172 DebugLoc DL = I->getDebugLoc();
173 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
175 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0);
176 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill);
177 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize);
178 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
181 void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I,
186 // store $vr1, FI + 4
188 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
190 const MipsSEInstrInfo &TII =
191 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
192 const MipsRegisterInfo &RegInfo =
193 *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
195 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
196 unsigned VR0 = MRI.createVirtualRegister(RC);
197 unsigned VR1 = MRI.createVirtualRegister(RC);
198 unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
199 unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());
200 unsigned Lo = RegInfo.getSubReg(Src, Mips::sub_lo);
201 unsigned Hi = RegInfo.getSubReg(Src, Mips::sub_hi);
202 DebugLoc DL = I->getDebugLoc();
204 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), VR0).addReg(Lo, SrcKill);
205 TII.storeRegToStack(MBB, I, VR0, true, FI, RC, &RegInfo, 0);
206 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), VR1).addReg(Hi, SrcKill);
207 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize);
210 bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) {
211 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
213 if (Mips::ACRegsDSPRegClass.contains(Dst, Src))
214 return expandCopyACC(MBB, I, Dst, Src, 4);
216 if (Mips::ACRegs128RegClass.contains(Dst, Src))
217 return expandCopyACC(MBB, I, Dst, Src, 8);
222 bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned Dst,
223 unsigned Src, unsigned RegSize) {
229 const MipsSEInstrInfo &TII =
230 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
231 const MipsRegisterInfo &RegInfo =
232 *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
234 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
235 unsigned VR0 = MRI.createVirtualRegister(RC);
236 unsigned VR1 = MRI.createVirtualRegister(RC);
237 unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
238 unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
239 unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
240 unsigned SrcLo = RegInfo.getSubReg(Src, Mips::sub_lo);
241 unsigned SrcHi = RegInfo.getSubReg(Src, Mips::sub_hi);
242 DebugLoc DL = I->getDebugLoc();
244 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), VR0).addReg(SrcLo, SrcKill);
245 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo)
246 .addReg(VR0, RegState::Kill);
247 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), VR1).addReg(SrcHi, SrcKill);
248 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi)
249 .addReg(VR1, RegState::Kill);
253 unsigned MipsSEFrameLowering::ehDataReg(unsigned I) const {
254 static const unsigned EhDataReg[] = {
255 Mips::A0, Mips::A1, Mips::A2, Mips::A3
257 static const unsigned EhDataReg64[] = {
258 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64
261 return STI.isABI_N64() ? EhDataReg64[I] : EhDataReg[I];
264 void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
265 MachineBasicBlock &MBB = MF.front();
266 MachineFrameInfo *MFI = MF.getFrameInfo();
267 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
269 const MipsSEInstrInfo &TII =
270 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
271 const MipsRegisterInfo &RegInfo =
272 *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
274 MachineBasicBlock::iterator MBBI = MBB.begin();
275 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
276 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
277 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
278 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
279 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
281 // First, compute final stack size.
282 uint64_t StackSize = MFI->getStackSize();
284 // No need to allocate space on the stack.
285 if (StackSize == 0 && !MFI->adjustsStack()) return;
287 MachineModuleInfo &MMI = MF.getMMI();
288 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
289 MachineLocation DstML, SrcML;
292 TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
294 // emit ".cfi_def_cfa_offset StackSize"
295 MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol();
296 BuildMI(MBB, MBBI, dl,
297 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel);
299 MCCFIInstruction::createDefCfaOffset(AdjustSPLabel, -StackSize));
301 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
304 // Find the instruction past the last instruction that saves a callee-saved
305 // register to the stack.
306 for (unsigned i = 0; i < CSI.size(); ++i)
309 // Iterate over list of callee-saved registers and emit .cfi_offset
311 MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol();
312 BuildMI(MBB, MBBI, dl,
313 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
315 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
316 E = CSI.end(); I != E; ++I) {
317 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
318 unsigned Reg = I->getReg();
320 // If Reg is a double precision register, emit two cfa_offsets,
321 // one for each of the paired single precision registers.
322 if (Mips::AFGR64RegClass.contains(Reg)) {
324 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpeven), true);
326 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpodd), true);
329 std::swap(Reg0, Reg1);
332 MCCFIInstruction::createOffset(CSLabel, Reg0, Offset));
334 MCCFIInstruction::createOffset(CSLabel, Reg1, Offset + 4));
336 // Reg is either in CPURegs or FGR32.
337 MMI.addFrameInst(MCCFIInstruction::createOffset(
338 CSLabel, MRI->getDwarfRegNum(Reg, 1), Offset));
343 if (MipsFI->callsEhReturn()) {
344 const TargetRegisterClass *RC = STI.isABI_N64() ?
345 &Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass;
347 // Insert instructions that spill eh data registers.
348 for (int I = 0; I < 4; ++I) {
349 if (!MBB.isLiveIn(ehDataReg(I)))
350 MBB.addLiveIn(ehDataReg(I));
351 TII.storeRegToStackSlot(MBB, MBBI, ehDataReg(I), false,
352 MipsFI->getEhDataRegFI(I), RC, &RegInfo);
355 // Emit .cfi_offset directives for eh data registers.
356 MCSymbol *CSLabel2 = MMI.getContext().CreateTempSymbol();
357 BuildMI(MBB, MBBI, dl,
358 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel2);
359 for (int I = 0; I < 4; ++I) {
360 int64_t Offset = MFI->getObjectOffset(MipsFI->getEhDataRegFI(I));
361 unsigned Reg = MRI->getDwarfRegNum(ehDataReg(I), true);
362 MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel2, Reg, Offset));
366 // if framepointer enabled, set it to point to the stack pointer.
368 // Insert instruction "move $fp, $sp" at this location.
369 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO);
371 // emit ".cfi_def_cfa_register $fp"
372 MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol();
373 BuildMI(MBB, MBBI, dl,
374 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel);
375 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
376 SetFPLabel, MRI->getDwarfRegNum(FP, true)));
380 void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
381 MachineBasicBlock &MBB) const {
382 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
383 MachineFrameInfo *MFI = MF.getFrameInfo();
384 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
386 const MipsSEInstrInfo &TII =
387 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
388 const MipsRegisterInfo &RegInfo =
389 *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
391 DebugLoc dl = MBBI->getDebugLoc();
392 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
393 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
394 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
395 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
397 // if framepointer enabled, restore the stack pointer.
399 // Find the first instruction that restores a callee-saved register.
400 MachineBasicBlock::iterator I = MBBI;
402 for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
405 // Insert instruction "move $sp, $fp" at this location.
406 BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
409 if (MipsFI->callsEhReturn()) {
410 const TargetRegisterClass *RC = STI.isABI_N64() ?
411 &Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass;
413 // Find first instruction that restores a callee-saved register.
414 MachineBasicBlock::iterator I = MBBI;
415 for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
418 // Insert instructions that restore eh data registers.
419 for (int J = 0; J < 4; ++J) {
420 TII.loadRegFromStackSlot(MBB, I, ehDataReg(J), MipsFI->getEhDataRegFI(J),
425 // Get the number of bytes from FrameInfo
426 uint64_t StackSize = MFI->getStackSize();
432 TII.adjustStackPtr(SP, StackSize, MBB, MBBI);
435 bool MipsSEFrameLowering::
436 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
437 MachineBasicBlock::iterator MI,
438 const std::vector<CalleeSavedInfo> &CSI,
439 const TargetRegisterInfo *TRI) const {
440 MachineFunction *MF = MBB.getParent();
441 MachineBasicBlock *EntryBlock = MF->begin();
442 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
444 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
445 // Add the callee-saved register as live-in. Do not add if the register is
446 // RA and return address is taken, because it has already been added in
447 // method MipsTargetLowering::LowerRETURNADDR.
448 // It's killed at the spill, unless the register is RA and return address
450 unsigned Reg = CSI[i].getReg();
451 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
452 && MF->getFrameInfo()->isReturnAddressTaken();
453 if (!IsRAAndRetAddrIsTaken)
454 EntryBlock->addLiveIn(Reg);
456 // Insert the spill to the stack frame.
457 bool IsKill = !IsRAAndRetAddrIsTaken;
458 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
459 TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill,
460 CSI[i].getFrameIdx(), RC, TRI);
467 MipsSEFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
468 const MachineFrameInfo *MFI = MF.getFrameInfo();
470 // Reserve call frame if the size of the maximum call frame fits into 16-bit
471 // immediate field and there are no variable sized objects on the stack.
472 // Make sure the second register scavenger spill slot can be accessed with one
474 return isInt<16>(MFI->getMaxCallFrameSize() + getStackAlignment()) &&
475 !MFI->hasVarSizedObjects();
478 // Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions
479 void MipsSEFrameLowering::
480 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
481 MachineBasicBlock::iterator I) const {
482 const MipsSEInstrInfo &TII =
483 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
485 if (!hasReservedCallFrame(MF)) {
486 int64_t Amount = I->getOperand(0).getImm();
488 if (I->getOpcode() == Mips::ADJCALLSTACKDOWN)
491 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
492 TII.adjustStackPtr(SP, Amount, MBB, I);
498 void MipsSEFrameLowering::
499 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
500 RegScavenger *RS) const {
501 MachineRegisterInfo &MRI = MF.getRegInfo();
502 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
503 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
505 // Mark $fp as used if function has dedicated frame pointer.
507 MRI.setPhysRegUsed(FP);
509 // Create spill slots for eh data registers if function calls eh_return.
510 if (MipsFI->callsEhReturn())
511 MipsFI->createEhDataRegsFI();
513 // Expand pseudo instructions which load, store or copy accumulators.
514 // Add an emergency spill slot if a pseudo was expanded.
515 if (ExpandPseudo(MF).expand()) {
516 // The spill slot should be half the size of the accumulator. If target is
517 // mips64, it should be 64-bit, otherwise it should be 32-bt.
518 const TargetRegisterClass *RC = STI.hasMips64() ?
519 &Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass;
520 int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
521 RC->getAlignment(), false);
522 RS->addScavengingFrameIndex(FI);
525 // Set scavenging frame index if necessary.
526 uint64_t MaxSPOffset = MF.getInfo<MipsFunctionInfo>()->getIncomingArgSize() +
527 estimateStackSize(MF);
529 if (isInt<16>(MaxSPOffset))
532 const TargetRegisterClass *RC = STI.isABI_N64() ?
533 &Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass;
534 int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
535 RC->getAlignment(), false);
536 RS->addScavengingFrameIndex(FI);
539 const MipsFrameLowering *
540 llvm::createMipsSEFrameLowering(const MipsSubtarget &ST) {
541 return new MipsSEFrameLowering(ST);