1 //===-- MipsSEFrameLowering.cpp - Mips32/64 Frame Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips32/64 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsSEFrameLowering.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsSEInstrInfo.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/DataLayout.h"
26 #include "llvm/Function.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Target/TargetOptions.h"
32 void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
33 MachineBasicBlock &MBB = MF.front();
34 MachineFrameInfo *MFI = MF.getFrameInfo();
35 const MipsRegisterInfo *RegInfo =
36 static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
37 const MipsSEInstrInfo &TII =
38 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
39 MachineBasicBlock::iterator MBBI = MBB.begin();
40 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
41 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
42 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
43 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
44 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
46 // First, compute final stack size.
47 uint64_t StackSize = MFI->getStackSize();
49 // No need to allocate space on the stack.
50 if (StackSize == 0 && !MFI->adjustsStack()) return;
52 MachineModuleInfo &MMI = MF.getMMI();
53 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
54 MachineLocation DstML, SrcML;
57 TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
59 // emit ".cfi_def_cfa_offset StackSize"
60 MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol();
61 BuildMI(MBB, MBBI, dl,
62 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel);
63 DstML = MachineLocation(MachineLocation::VirtualFP);
64 SrcML = MachineLocation(MachineLocation::VirtualFP, -StackSize);
65 Moves.push_back(MachineMove(AdjustSPLabel, DstML, SrcML));
67 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
70 // Find the instruction past the last instruction that saves a callee-saved
71 // register to the stack.
72 for (unsigned i = 0; i < CSI.size(); ++i)
75 // Iterate over list of callee-saved registers and emit .cfi_offset
77 MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol();
78 BuildMI(MBB, MBBI, dl,
79 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
81 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
82 E = CSI.end(); I != E; ++I) {
83 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
84 unsigned Reg = I->getReg();
86 // If Reg is a double precision register, emit two cfa_offsets,
87 // one for each of the paired single precision registers.
88 if (Mips::AFGR64RegClass.contains(Reg)) {
89 MachineLocation DstML0(MachineLocation::VirtualFP, Offset);
90 MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4);
91 MachineLocation SrcML0(RegInfo->getSubReg(Reg, Mips::sub_fpeven));
92 MachineLocation SrcML1(RegInfo->getSubReg(Reg, Mips::sub_fpodd));
95 std::swap(SrcML0, SrcML1);
97 Moves.push_back(MachineMove(CSLabel, DstML0, SrcML0));
98 Moves.push_back(MachineMove(CSLabel, DstML1, SrcML1));
100 // Reg is either in CPURegs or FGR32.
101 DstML = MachineLocation(MachineLocation::VirtualFP, Offset);
102 SrcML = MachineLocation(Reg);
103 Moves.push_back(MachineMove(CSLabel, DstML, SrcML));
108 // if framepointer enabled, set it to point to the stack pointer.
110 // Insert instruction "move $fp, $sp" at this location.
111 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO);
113 // emit ".cfi_def_cfa_register $fp"
114 MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol();
115 BuildMI(MBB, MBBI, dl,
116 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel);
117 DstML = MachineLocation(FP);
118 SrcML = MachineLocation(MachineLocation::VirtualFP);
119 Moves.push_back(MachineMove(SetFPLabel, DstML, SrcML));
123 void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
124 MachineBasicBlock &MBB) const {
125 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
126 MachineFrameInfo *MFI = MF.getFrameInfo();
127 const MipsSEInstrInfo &TII =
128 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
129 DebugLoc dl = MBBI->getDebugLoc();
130 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
131 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
132 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
133 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
135 // if framepointer enabled, restore the stack pointer.
137 // Find the first instruction that restores a callee-saved register.
138 MachineBasicBlock::iterator I = MBBI;
140 for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
143 // Insert instruction "move $sp, $fp" at this location.
144 BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
147 // Get the number of bytes from FrameInfo
148 uint64_t StackSize = MFI->getStackSize();
154 TII.adjustStackPtr(SP, StackSize, MBB, MBBI);
157 bool MipsSEFrameLowering::
158 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
159 MachineBasicBlock::iterator MI,
160 const std::vector<CalleeSavedInfo> &CSI,
161 const TargetRegisterInfo *TRI) const {
162 MachineFunction *MF = MBB.getParent();
163 MachineBasicBlock *EntryBlock = MF->begin();
164 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
166 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
167 // Add the callee-saved register as live-in. Do not add if the register is
168 // RA and return address is taken, because it has already been added in
169 // method MipsTargetLowering::LowerRETURNADDR.
170 // It's killed at the spill, unless the register is RA and return address
172 unsigned Reg = CSI[i].getReg();
173 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
174 && MF->getFrameInfo()->isReturnAddressTaken();
175 if (!IsRAAndRetAddrIsTaken)
176 EntryBlock->addLiveIn(Reg);
178 // Insert the spill to the stack frame.
179 bool IsKill = !IsRAAndRetAddrIsTaken;
180 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
181 TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill,
182 CSI[i].getFrameIdx(), RC, TRI);
189 MipsSEFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
190 const MachineFrameInfo *MFI = MF.getFrameInfo();
192 // Reserve call frame if the size of the maximum call frame fits into 16-bit
193 // immediate field and there are no variable sized objects on the stack.
194 return isInt<16>(MFI->getMaxCallFrameSize()) && !MFI->hasVarSizedObjects();
197 void MipsSEFrameLowering::
198 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
199 RegScavenger *RS) const {
200 MachineRegisterInfo &MRI = MF.getRegInfo();
201 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
203 // Mark $fp as used if function has dedicated frame pointer.
205 MRI.setPhysRegUsed(FP);
207 // Set scavenging frame index if necessary.
208 uint64_t MaxSPOffset = MF.getInfo<MipsFunctionInfo>()->getIncomingArgSize() +
209 estimateStackSize(MF);
211 if (isInt<16>(MaxSPOffset))
214 const TargetRegisterClass *RC = STI.isABI_N64() ?
215 &Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass;
216 int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
217 RC->getAlignment(), false);
218 RS->setScavengingFrameIndex(FI);
221 const MipsFrameLowering *
222 llvm::createMipsSEFrameLowering(const MipsSubtarget &ST) {
223 return new MipsSEFrameLowering(ST);