1 //===-- MipsSEFrameLowering.cpp - Mips32/64 Frame Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips32/64 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsSEFrameLowering.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsSEInstrInfo.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Target/TargetOptions.h"
33 typedef MachineBasicBlock::iterator Iter;
35 /// Helper class to expand pseudos.
38 ExpandPseudo(MachineFunction &MF);
42 bool expandInstr(MachineBasicBlock &MBB, Iter I);
43 void expandLoadCCond(MachineBasicBlock &MBB, Iter I);
44 void expandStoreCCond(MachineBasicBlock &MBB, Iter I);
45 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
46 void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
47 bool expandCopy(MachineBasicBlock &MBB, Iter I);
48 bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned Dst,
49 unsigned Src, unsigned RegSize);
52 const MipsSEInstrInfo &TII;
53 const MipsRegisterInfo &RegInfo;
54 MachineRegisterInfo &MRI;
58 ExpandPseudo::ExpandPseudo(MachineFunction &MF_)
60 TII(*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo())),
61 RegInfo(TII.getRegisterInfo()), MRI(MF.getRegInfo()) {}
63 bool ExpandPseudo::expand() {
64 bool Expanded = false;
66 for (MachineFunction::iterator BB = MF.begin(), BBEnd = MF.end();
68 for (Iter I = BB->begin(), End = BB->end(); I != End;)
69 Expanded |= expandInstr(*BB, I++);
74 bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
75 switch(I->getOpcode()) {
76 case Mips::LOAD_CCOND_DSP:
77 case Mips::LOAD_CCOND_DSP_P8:
78 expandLoadCCond(MBB, I);
80 case Mips::STORE_CCOND_DSP:
81 case Mips::STORE_CCOND_DSP_P8:
82 expandStoreCCond(MBB, I);
85 case Mips::LOAD_AC64_P8:
86 case Mips::LOAD_AC_DSP:
87 case Mips::LOAD_AC_DSP_P8:
88 expandLoadACC(MBB, I, 4);
90 case Mips::LOAD_AC128:
91 case Mips::LOAD_AC128_P8:
92 expandLoadACC(MBB, I, 8);
94 case Mips::STORE_AC64:
95 case Mips::STORE_AC64_P8:
96 case Mips::STORE_AC_DSP:
97 case Mips::STORE_AC_DSP_P8:
98 expandStoreACC(MBB, I, 4);
100 case Mips::STORE_AC128:
101 case Mips::STORE_AC128_P8:
102 expandStoreACC(MBB, I, 8);
104 case TargetOpcode::COPY:
105 if (!expandCopy(MBB, I))
116 void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) {
120 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
122 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
123 unsigned VR = MRI.createVirtualRegister(RC);
124 unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
126 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
127 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
128 .addReg(VR, RegState::Kill);
131 void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) {
135 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
137 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
138 unsigned VR = MRI.createVirtualRegister(RC);
139 unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
141 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
142 .addReg(Src, getKillRegState(I->getOperand(0).isKill()));
143 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
146 void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I,
153 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
155 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
156 unsigned VR0 = MRI.createVirtualRegister(RC);
157 unsigned VR1 = MRI.createVirtualRegister(RC);
158 unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
159 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
160 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
161 DebugLoc DL = I->getDebugLoc();
162 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
164 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0);
165 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill);
166 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize);
167 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
170 void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I,
175 // store $vr1, FI + 4
177 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
179 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
180 unsigned VR0 = MRI.createVirtualRegister(RC);
181 unsigned VR1 = MRI.createVirtualRegister(RC);
182 unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
183 unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());
184 unsigned Lo = RegInfo.getSubReg(Src, Mips::sub_lo);
185 unsigned Hi = RegInfo.getSubReg(Src, Mips::sub_hi);
186 DebugLoc DL = I->getDebugLoc();
188 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), VR0).addReg(Lo, SrcKill);
189 TII.storeRegToStack(MBB, I, VR0, true, FI, RC, &RegInfo, 0);
190 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), VR1).addReg(Hi, SrcKill);
191 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize);
194 bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) {
195 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
197 if (Mips::ACRegsDSPRegClass.contains(Dst, Src))
198 return expandCopyACC(MBB, I, Dst, Src, 4);
200 if (Mips::ACRegs128RegClass.contains(Dst, Src))
201 return expandCopyACC(MBB, I, Dst, Src, 8);
206 bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned Dst,
207 unsigned Src, unsigned RegSize) {
213 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
214 unsigned VR0 = MRI.createVirtualRegister(RC);
215 unsigned VR1 = MRI.createVirtualRegister(RC);
216 unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
217 unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
218 unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
219 unsigned SrcLo = RegInfo.getSubReg(Src, Mips::sub_lo);
220 unsigned SrcHi = RegInfo.getSubReg(Src, Mips::sub_hi);
221 DebugLoc DL = I->getDebugLoc();
223 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), VR0).addReg(SrcLo, SrcKill);
224 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo)
225 .addReg(VR0, RegState::Kill);
226 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), VR1).addReg(SrcHi, SrcKill);
227 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi)
228 .addReg(VR1, RegState::Kill);
232 unsigned MipsSEFrameLowering::ehDataReg(unsigned I) const {
233 static const unsigned EhDataReg[] = {
234 Mips::A0, Mips::A1, Mips::A2, Mips::A3
236 static const unsigned EhDataReg64[] = {
237 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64
240 return STI.isABI_N64() ? EhDataReg64[I] : EhDataReg[I];
243 void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
244 MachineBasicBlock &MBB = MF.front();
245 MachineFrameInfo *MFI = MF.getFrameInfo();
246 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
247 const MipsRegisterInfo *RegInfo =
248 static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
249 const MipsSEInstrInfo &TII =
250 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
251 MachineBasicBlock::iterator MBBI = MBB.begin();
252 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
253 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
254 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
255 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
256 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
258 // First, compute final stack size.
259 uint64_t StackSize = MFI->getStackSize();
261 // No need to allocate space on the stack.
262 if (StackSize == 0 && !MFI->adjustsStack()) return;
264 MachineModuleInfo &MMI = MF.getMMI();
265 const MCRegisterInfo &MRI = MMI.getContext().getRegisterInfo();
266 MachineLocation DstML, SrcML;
269 TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
271 // emit ".cfi_def_cfa_offset StackSize"
272 MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol();
273 BuildMI(MBB, MBBI, dl,
274 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel);
276 MCCFIInstruction::createDefCfaOffset(AdjustSPLabel, -StackSize));
278 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
281 // Find the instruction past the last instruction that saves a callee-saved
282 // register to the stack.
283 for (unsigned i = 0; i < CSI.size(); ++i)
286 // Iterate over list of callee-saved registers and emit .cfi_offset
288 MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol();
289 BuildMI(MBB, MBBI, dl,
290 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
292 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
293 E = CSI.end(); I != E; ++I) {
294 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
295 unsigned Reg = I->getReg();
297 // If Reg is a double precision register, emit two cfa_offsets,
298 // one for each of the paired single precision registers.
299 if (Mips::AFGR64RegClass.contains(Reg)) {
301 MRI.getDwarfRegNum(RegInfo->getSubReg(Reg, Mips::sub_fpeven), true);
303 MRI.getDwarfRegNum(RegInfo->getSubReg(Reg, Mips::sub_fpodd), true);
306 std::swap(Reg0, Reg1);
309 MCCFIInstruction::createOffset(CSLabel, Reg0, Offset));
311 MCCFIInstruction::createOffset(CSLabel, Reg1, Offset + 4));
313 // Reg is either in CPURegs or FGR32.
314 MMI.addFrameInst(MCCFIInstruction::createOffset(
315 CSLabel, MRI.getDwarfRegNum(Reg, 1), Offset));
320 if (MipsFI->callsEhReturn()) {
321 const TargetRegisterClass *RC = STI.isABI_N64() ?
322 &Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass;
324 // Insert instructions that spill eh data registers.
325 for (int I = 0; I < 4; ++I) {
326 if (!MBB.isLiveIn(ehDataReg(I)))
327 MBB.addLiveIn(ehDataReg(I));
328 TII.storeRegToStackSlot(MBB, MBBI, ehDataReg(I), false,
329 MipsFI->getEhDataRegFI(I), RC, RegInfo);
332 // Emit .cfi_offset directives for eh data registers.
333 MCSymbol *CSLabel2 = MMI.getContext().CreateTempSymbol();
334 BuildMI(MBB, MBBI, dl,
335 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel2);
336 for (int I = 0; I < 4; ++I) {
337 int64_t Offset = MFI->getObjectOffset(MipsFI->getEhDataRegFI(I));
338 unsigned Reg = MRI.getDwarfRegNum(ehDataReg(I), true);
339 MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel2, Reg, Offset));
343 // if framepointer enabled, set it to point to the stack pointer.
345 // Insert instruction "move $fp, $sp" at this location.
346 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO);
348 // emit ".cfi_def_cfa_register $fp"
349 MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol();
350 BuildMI(MBB, MBBI, dl,
351 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel);
352 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
353 SetFPLabel, MRI.getDwarfRegNum(FP, true)));
357 void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
358 MachineBasicBlock &MBB) const {
359 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
360 MachineFrameInfo *MFI = MF.getFrameInfo();
361 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
362 const MipsRegisterInfo *RegInfo =
363 static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
364 const MipsSEInstrInfo &TII =
365 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
366 DebugLoc dl = MBBI->getDebugLoc();
367 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
368 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
369 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
370 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
372 // if framepointer enabled, restore the stack pointer.
374 // Find the first instruction that restores a callee-saved register.
375 MachineBasicBlock::iterator I = MBBI;
377 for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
380 // Insert instruction "move $sp, $fp" at this location.
381 BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
384 if (MipsFI->callsEhReturn()) {
385 const TargetRegisterClass *RC = STI.isABI_N64() ?
386 &Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass;
388 // Find first instruction that restores a callee-saved register.
389 MachineBasicBlock::iterator I = MBBI;
390 for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
393 // Insert instructions that restore eh data registers.
394 for (int J = 0; J < 4; ++J) {
395 TII.loadRegFromStackSlot(MBB, I, ehDataReg(J), MipsFI->getEhDataRegFI(J),
400 // Get the number of bytes from FrameInfo
401 uint64_t StackSize = MFI->getStackSize();
407 TII.adjustStackPtr(SP, StackSize, MBB, MBBI);
410 bool MipsSEFrameLowering::
411 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
412 MachineBasicBlock::iterator MI,
413 const std::vector<CalleeSavedInfo> &CSI,
414 const TargetRegisterInfo *TRI) const {
415 MachineFunction *MF = MBB.getParent();
416 MachineBasicBlock *EntryBlock = MF->begin();
417 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
419 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
420 // Add the callee-saved register as live-in. Do not add if the register is
421 // RA and return address is taken, because it has already been added in
422 // method MipsTargetLowering::LowerRETURNADDR.
423 // It's killed at the spill, unless the register is RA and return address
425 unsigned Reg = CSI[i].getReg();
426 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
427 && MF->getFrameInfo()->isReturnAddressTaken();
428 if (!IsRAAndRetAddrIsTaken)
429 EntryBlock->addLiveIn(Reg);
431 // Insert the spill to the stack frame.
432 bool IsKill = !IsRAAndRetAddrIsTaken;
433 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
434 TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill,
435 CSI[i].getFrameIdx(), RC, TRI);
442 MipsSEFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
443 const MachineFrameInfo *MFI = MF.getFrameInfo();
445 // Reserve call frame if the size of the maximum call frame fits into 16-bit
446 // immediate field and there are no variable sized objects on the stack.
447 // Make sure the second register scavenger spill slot can be accessed with one
449 return isInt<16>(MFI->getMaxCallFrameSize() + getStackAlignment()) &&
450 !MFI->hasVarSizedObjects();
453 // Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions
454 void MipsSEFrameLowering::
455 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
456 MachineBasicBlock::iterator I) const {
457 const MipsSEInstrInfo &TII =
458 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
460 if (!hasReservedCallFrame(MF)) {
461 int64_t Amount = I->getOperand(0).getImm();
463 if (I->getOpcode() == Mips::ADJCALLSTACKDOWN)
466 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
467 TII.adjustStackPtr(SP, Amount, MBB, I);
473 void MipsSEFrameLowering::
474 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
475 RegScavenger *RS) const {
476 MachineRegisterInfo &MRI = MF.getRegInfo();
477 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
478 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
480 // Mark $fp as used if function has dedicated frame pointer.
482 MRI.setPhysRegUsed(FP);
484 // Create spill slots for eh data registers if function calls eh_return.
485 if (MipsFI->callsEhReturn())
486 MipsFI->createEhDataRegsFI();
488 // Expand pseudo instructions which load, store or copy accumulators.
489 // Add an emergency spill slot if a pseudo was expanded.
490 if (ExpandPseudo(MF).expand()) {
491 // The spill slot should be half the size of the accumulator. If target is
492 // mips64, it should be 64-bit, otherwise it should be 32-bt.
493 const TargetRegisterClass *RC = STI.hasMips64() ?
494 &Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass;
495 int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
496 RC->getAlignment(), false);
497 RS->addScavengingFrameIndex(FI);
500 // Set scavenging frame index if necessary.
501 uint64_t MaxSPOffset = MF.getInfo<MipsFunctionInfo>()->getIncomingArgSize() +
502 estimateStackSize(MF);
504 if (isInt<16>(MaxSPOffset))
507 const TargetRegisterClass *RC = STI.isABI_N64() ?
508 &Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass;
509 int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
510 RC->getAlignment(), false);
511 RS->addScavengingFrameIndex(FI);
514 const MipsFrameLowering *
515 llvm::createMipsSEFrameLowering(const MipsSubtarget &ST) {
516 return new MipsSEFrameLowering(ST);