1 //===-- MipsSEFrameLowering.cpp - Mips32/64 Frame Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips32/64 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsSEFrameLowering.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsSEInstrInfo.h"
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Target/TargetOptions.h"
34 typedef MachineBasicBlock::iterator Iter;
36 static std::pair<unsigned, unsigned> getMFHiLoOpc(unsigned Src) {
37 if (Mips::ACC64RegClass.contains(Src))
38 return std::make_pair((unsigned)Mips::PseudoMFHI,
39 (unsigned)Mips::PseudoMFLO);
41 if (Mips::ACC64DSPRegClass.contains(Src))
42 return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP);
44 if (Mips::ACC128RegClass.contains(Src))
45 return std::make_pair((unsigned)Mips::PseudoMFHI64,
46 (unsigned)Mips::PseudoMFLO64);
48 return std::make_pair(0, 0);
51 /// Helper class to expand pseudos.
54 ExpandPseudo(MachineFunction &MF);
58 bool expandInstr(MachineBasicBlock &MBB, Iter I);
59 void expandLoadCCond(MachineBasicBlock &MBB, Iter I);
60 void expandStoreCCond(MachineBasicBlock &MBB, Iter I);
61 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
62 void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,
63 unsigned MFLoOpc, unsigned RegSize);
64 bool expandCopy(MachineBasicBlock &MBB, Iter I);
65 bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,
67 bool expandBuildPairF64(MachineBasicBlock &MBB,
68 MachineBasicBlock::iterator I, bool FP64) const;
71 MachineRegisterInfo &MRI;
75 ExpandPseudo::ExpandPseudo(MachineFunction &MF_)
76 : MF(MF_), MRI(MF.getRegInfo()) {}
78 bool ExpandPseudo::expand() {
79 bool Expanded = false;
81 for (MachineFunction::iterator BB = MF.begin(), BBEnd = MF.end();
83 for (Iter I = BB->begin(), End = BB->end(); I != End;)
84 Expanded |= expandInstr(*BB, I++);
89 bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
90 switch(I->getOpcode()) {
91 case Mips::LOAD_CCOND_DSP:
92 expandLoadCCond(MBB, I);
94 case Mips::STORE_CCOND_DSP:
95 expandStoreCCond(MBB, I);
97 case Mips::LOAD_ACC64:
98 case Mips::LOAD_ACC64DSP:
99 expandLoadACC(MBB, I, 4);
101 case Mips::LOAD_ACC128:
102 expandLoadACC(MBB, I, 8);
104 case Mips::STORE_ACC64:
105 expandStoreACC(MBB, I, Mips::PseudoMFHI, Mips::PseudoMFLO, 4);
107 case Mips::STORE_ACC64DSP:
108 expandStoreACC(MBB, I, Mips::MFHI_DSP, Mips::MFLO_DSP, 4);
110 case Mips::STORE_ACC128:
111 expandStoreACC(MBB, I, Mips::PseudoMFHI64, Mips::PseudoMFLO64, 8);
113 case Mips::BuildPairF64:
114 if (expandBuildPairF64(MBB, I, false))
117 case Mips::BuildPairF64_64:
118 if (expandBuildPairF64(MBB, I, true))
121 case TargetOpcode::COPY:
122 if (!expandCopy(MBB, I))
133 void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) {
137 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
139 const MipsSEInstrInfo &TII =
140 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
141 const MipsRegisterInfo &RegInfo =
142 *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
144 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
145 unsigned VR = MRI.createVirtualRegister(RC);
146 unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
148 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
149 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
150 .addReg(VR, RegState::Kill);
153 void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) {
157 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
159 const MipsSEInstrInfo &TII =
160 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
161 const MipsRegisterInfo &RegInfo =
162 *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
164 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
165 unsigned VR = MRI.createVirtualRegister(RC);
166 unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
168 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
169 .addReg(Src, getKillRegState(I->getOperand(0).isKill()));
170 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
173 void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I,
180 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
182 const MipsSEInstrInfo &TII =
183 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
184 const MipsRegisterInfo &RegInfo =
185 *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
187 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
188 unsigned VR0 = MRI.createVirtualRegister(RC);
189 unsigned VR1 = MRI.createVirtualRegister(RC);
190 unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
191 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
192 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
193 DebugLoc DL = I->getDebugLoc();
194 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
196 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0);
197 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill);
198 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize);
199 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
202 void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I,
203 unsigned MFHiOpc, unsigned MFLoOpc,
208 // store $vr1, FI + 4
210 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
212 const MipsSEInstrInfo &TII =
213 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
214 const MipsRegisterInfo &RegInfo =
215 *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
217 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
218 unsigned VR0 = MRI.createVirtualRegister(RC);
219 unsigned VR1 = MRI.createVirtualRegister(RC);
220 unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
221 unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());
222 DebugLoc DL = I->getDebugLoc();
224 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
225 TII.storeRegToStack(MBB, I, VR0, true, FI, RC, &RegInfo, 0);
226 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
227 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize);
230 bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) {
231 unsigned Src = I->getOperand(1).getReg();
232 std::pair<unsigned, unsigned> Opcodes = getMFHiLoOpc(Src);
237 return expandCopyACC(MBB, I, Opcodes.first, Opcodes.second);
240 bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I,
241 unsigned MFHiOpc, unsigned MFLoOpc) {
247 const MipsSEInstrInfo &TII =
248 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
249 const MipsRegisterInfo &RegInfo =
250 *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
252 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
253 unsigned VRegSize = RegInfo.getMinimalPhysRegClass(Dst)->getSize() / 2;
254 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize);
255 unsigned VR0 = MRI.createVirtualRegister(RC);
256 unsigned VR1 = MRI.createVirtualRegister(RC);
257 unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
258 unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
259 unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
260 DebugLoc DL = I->getDebugLoc();
262 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
263 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo)
264 .addReg(VR0, RegState::Kill);
265 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
266 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi)
267 .addReg(VR1, RegState::Kill);
271 /// This method expands the same instruction that MipsSEInstrInfo::
272 /// expandBuildPairF64 does, for the case when ABI is fpxx and mthc1 is
273 /// not available. It is implemented here because frame indexes are
274 /// eliminated before MipsSEInstrInfo::expandBuildPairF64 is called.
275 bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB,
276 MachineBasicBlock::iterator I,
278 // For fpxx and when mthc1 is not available, use:
279 // spill + reload via ldc1
281 // The case where dmtc1 is available doesn't need to be handled here
282 // because it never creates a BuildPairF64 node.
284 const TargetMachine &TM = MF.getTarget();
285 if (TM.getSubtarget<MipsSubtarget>().isABI_FPXX()
286 && !TM.getSubtarget<MipsSubtarget>().hasMTHC1()) {
287 const MipsSEInstrInfo &TII =
288 *static_cast<const MipsSEInstrInfo*>(TM.getInstrInfo());
289 const MipsRegisterInfo &TRI =
290 *static_cast<const MipsRegisterInfo*>(TM.getRegisterInfo());
292 unsigned DstReg = I->getOperand(0).getReg();
293 unsigned LoReg = I->getOperand(1).getReg();
294 unsigned HiReg = I->getOperand(2).getReg();
296 // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
297 // the cases where mthc1 is not available).
298 assert(!TM.getSubtarget<MipsSubtarget>().isFP64bit());
300 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
301 const TargetRegisterClass *RC2 = &Mips::AFGR64RegClass;
303 int FI = MF.getInfo<MipsFunctionInfo>()->getBuildPairF64_FI(RC2);
304 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, &TRI,
306 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, &TRI,
308 TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &TRI, 0);
315 MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI)
316 : MipsFrameLowering(STI, STI.stackAlignment()) {}
318 unsigned MipsSEFrameLowering::ehDataReg(unsigned I) const {
319 static const unsigned EhDataReg[] = {
320 Mips::A0, Mips::A1, Mips::A2, Mips::A3
322 static const unsigned EhDataReg64[] = {
323 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64
326 return STI.isABI_N64() ? EhDataReg64[I] : EhDataReg[I];
329 void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
330 MachineBasicBlock &MBB = MF.front();
331 MachineFrameInfo *MFI = MF.getFrameInfo();
332 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
334 const MipsSEInstrInfo &TII =
335 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
336 const MipsRegisterInfo &RegInfo =
337 *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
339 MachineBasicBlock::iterator MBBI = MBB.begin();
340 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
341 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
342 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
343 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
344 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
346 // First, compute final stack size.
347 uint64_t StackSize = MFI->getStackSize();
349 // No need to allocate space on the stack.
350 if (StackSize == 0 && !MFI->adjustsStack()) return;
352 MachineModuleInfo &MMI = MF.getMMI();
353 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
354 MachineLocation DstML, SrcML;
357 TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
359 // emit ".cfi_def_cfa_offset StackSize"
360 unsigned CFIIndex = MMI.addFrameInst(
361 MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
362 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
363 .addCFIIndex(CFIIndex);
365 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
368 // Find the instruction past the last instruction that saves a callee-saved
369 // register to the stack.
370 for (unsigned i = 0; i < CSI.size(); ++i)
373 // Iterate over list of callee-saved registers and emit .cfi_offset
375 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
376 E = CSI.end(); I != E; ++I) {
377 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
378 unsigned Reg = I->getReg();
380 // If Reg is a double precision register, emit two cfa_offsets,
381 // one for each of the paired single precision registers.
382 if (Mips::AFGR64RegClass.contains(Reg)) {
384 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true);
386 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true);
389 std::swap(Reg0, Reg1);
391 unsigned CFIIndex = MMI.addFrameInst(
392 MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
393 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
394 .addCFIIndex(CFIIndex);
396 CFIIndex = MMI.addFrameInst(
397 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
398 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
399 .addCFIIndex(CFIIndex);
400 } else if (Mips::FGR64RegClass.contains(Reg)) {
401 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true);
402 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1;
405 std::swap(Reg0, Reg1);
407 unsigned CFIIndex = MMI.addFrameInst(
408 MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
409 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
410 .addCFIIndex(CFIIndex);
412 CFIIndex = MMI.addFrameInst(
413 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
414 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
415 .addCFIIndex(CFIIndex);
417 // Reg is either in GPR32 or FGR32.
418 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
419 nullptr, MRI->getDwarfRegNum(Reg, 1), Offset));
420 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
421 .addCFIIndex(CFIIndex);
426 if (MipsFI->callsEhReturn()) {
427 const TargetRegisterClass *RC = STI.isABI_N64() ?
428 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
430 // Insert instructions that spill eh data registers.
431 for (int I = 0; I < 4; ++I) {
432 if (!MBB.isLiveIn(ehDataReg(I)))
433 MBB.addLiveIn(ehDataReg(I));
434 TII.storeRegToStackSlot(MBB, MBBI, ehDataReg(I), false,
435 MipsFI->getEhDataRegFI(I), RC, &RegInfo);
438 // Emit .cfi_offset directives for eh data registers.
439 for (int I = 0; I < 4; ++I) {
440 int64_t Offset = MFI->getObjectOffset(MipsFI->getEhDataRegFI(I));
441 unsigned Reg = MRI->getDwarfRegNum(ehDataReg(I), true);
442 unsigned CFIIndex = MMI.addFrameInst(
443 MCCFIInstruction::createOffset(nullptr, Reg, Offset));
444 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
445 .addCFIIndex(CFIIndex);
449 // if framepointer enabled, set it to point to the stack pointer.
451 // Insert instruction "move $fp, $sp" at this location.
452 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO)
453 .setMIFlag(MachineInstr::FrameSetup);
455 // emit ".cfi_def_cfa_register $fp"
456 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
457 nullptr, MRI->getDwarfRegNum(FP, true)));
458 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
459 .addCFIIndex(CFIIndex);
463 void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
464 MachineBasicBlock &MBB) const {
465 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
466 MachineFrameInfo *MFI = MF.getFrameInfo();
467 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
469 const MipsSEInstrInfo &TII =
470 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
471 const MipsRegisterInfo &RegInfo =
472 *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
474 DebugLoc dl = MBBI->getDebugLoc();
475 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
476 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
477 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
478 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
480 // if framepointer enabled, restore the stack pointer.
482 // Find the first instruction that restores a callee-saved register.
483 MachineBasicBlock::iterator I = MBBI;
485 for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
488 // Insert instruction "move $sp, $fp" at this location.
489 BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
492 if (MipsFI->callsEhReturn()) {
493 const TargetRegisterClass *RC = STI.isABI_N64() ?
494 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
496 // Find first instruction that restores a callee-saved register.
497 MachineBasicBlock::iterator I = MBBI;
498 for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
501 // Insert instructions that restore eh data registers.
502 for (int J = 0; J < 4; ++J) {
503 TII.loadRegFromStackSlot(MBB, I, ehDataReg(J), MipsFI->getEhDataRegFI(J),
508 // Get the number of bytes from FrameInfo
509 uint64_t StackSize = MFI->getStackSize();
515 TII.adjustStackPtr(SP, StackSize, MBB, MBBI);
518 bool MipsSEFrameLowering::
519 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
520 MachineBasicBlock::iterator MI,
521 const std::vector<CalleeSavedInfo> &CSI,
522 const TargetRegisterInfo *TRI) const {
523 MachineFunction *MF = MBB.getParent();
524 MachineBasicBlock *EntryBlock = MF->begin();
525 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
527 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
528 // Add the callee-saved register as live-in. Do not add if the register is
529 // RA and return address is taken, because it has already been added in
530 // method MipsTargetLowering::LowerRETURNADDR.
531 // It's killed at the spill, unless the register is RA and return address
533 unsigned Reg = CSI[i].getReg();
534 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
535 && MF->getFrameInfo()->isReturnAddressTaken();
536 if (!IsRAAndRetAddrIsTaken)
537 EntryBlock->addLiveIn(Reg);
539 // Insert the spill to the stack frame.
540 bool IsKill = !IsRAAndRetAddrIsTaken;
541 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
542 TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill,
543 CSI[i].getFrameIdx(), RC, TRI);
550 MipsSEFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
551 const MachineFrameInfo *MFI = MF.getFrameInfo();
553 // Reserve call frame if the size of the maximum call frame fits into 16-bit
554 // immediate field and there are no variable sized objects on the stack.
555 // Make sure the second register scavenger spill slot can be accessed with one
557 return isInt<16>(MFI->getMaxCallFrameSize() + getStackAlignment()) &&
558 !MFI->hasVarSizedObjects();
561 // Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions
562 void MipsSEFrameLowering::
563 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
564 MachineBasicBlock::iterator I) const {
565 const MipsSEInstrInfo &TII =
566 *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
568 if (!hasReservedCallFrame(MF)) {
569 int64_t Amount = I->getOperand(0).getImm();
571 if (I->getOpcode() == Mips::ADJCALLSTACKDOWN)
574 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
575 TII.adjustStackPtr(SP, Amount, MBB, I);
581 void MipsSEFrameLowering::
582 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
583 RegScavenger *RS) const {
584 MachineRegisterInfo &MRI = MF.getRegInfo();
585 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
586 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
588 // Mark $fp as used if function has dedicated frame pointer.
590 MRI.setPhysRegUsed(FP);
592 // Create spill slots for eh data registers if function calls eh_return.
593 if (MipsFI->callsEhReturn())
594 MipsFI->createEhDataRegsFI();
596 // Expand pseudo instructions which load, store or copy accumulators.
597 // Add an emergency spill slot if a pseudo was expanded.
598 if (ExpandPseudo(MF).expand()) {
599 // The spill slot should be half the size of the accumulator. If target is
600 // mips64, it should be 64-bit, otherwise it should be 32-bt.
601 const TargetRegisterClass *RC = STI.hasMips64() ?
602 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
603 int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
604 RC->getAlignment(), false);
605 RS->addScavengingFrameIndex(FI);
608 // Set scavenging frame index if necessary.
609 uint64_t MaxSPOffset = MF.getInfo<MipsFunctionInfo>()->getIncomingArgSize() +
610 estimateStackSize(MF);
612 if (isInt<16>(MaxSPOffset))
615 const TargetRegisterClass *RC = STI.isABI_N64() ?
616 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
617 int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
618 RC->getAlignment(), false);
619 RS->addScavengingFrameIndex(FI);
622 const MipsFrameLowering *
623 llvm::createMipsSEFrameLowering(const MipsSubtarget &ST) {
624 return new MipsSEFrameLowering(ST);