1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
15 #include "MipsSEISelDAGToDAG.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
18 #include "MipsAnalyzeImmediate.h"
19 #include "MipsMachineFunction.h"
20 #include "MipsRegisterInfo.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CFG.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
38 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
39 if (Subtarget.inMips16Mode())
41 return MipsDAGToDAGISel::runOnMachineFunction(MF);
44 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
45 const MachineInstr& MI) {
46 unsigned DstReg = 0, ZeroReg = 0;
48 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
49 if ((MI.getOpcode() == Mips::ADDiu) &&
50 (MI.getOperand(1).getReg() == Mips::ZERO) &&
51 (MI.getOperand(2).getImm() == 0)) {
52 DstReg = MI.getOperand(0).getReg();
54 } else if ((MI.getOpcode() == Mips::DADDiu) &&
55 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
56 (MI.getOperand(2).getImm() == 0)) {
57 DstReg = MI.getOperand(0).getReg();
58 ZeroReg = Mips::ZERO_64;
64 // Replace uses with ZeroReg.
65 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
66 E = MRI->use_end(); U != E;) {
67 MachineOperand &MO = U.getOperand();
68 unsigned OpNo = U.getOperandNo();
69 MachineInstr *MI = MO.getParent();
72 // Do not replace if it is a phi's operand or is tied to def operand.
73 if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
82 void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
83 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
85 if (!MipsFI->globalBaseRegSet())
88 MachineBasicBlock &MBB = MF.front();
89 MachineBasicBlock::iterator I = MBB.begin();
90 MachineRegisterInfo &RegInfo = MF.getRegInfo();
91 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
92 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
93 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
94 const TargetRegisterClass *RC;
96 if (Subtarget.isABI_N64())
97 RC = (const TargetRegisterClass*)&Mips::CPU64RegsRegClass;
99 RC = (const TargetRegisterClass*)&Mips::CPURegsRegClass;
101 V0 = RegInfo.createVirtualRegister(RC);
102 V1 = RegInfo.createVirtualRegister(RC);
104 if (Subtarget.isABI_N64()) {
105 MF.getRegInfo().addLiveIn(Mips::T9_64);
106 MBB.addLiveIn(Mips::T9_64);
108 // lui $v0, %hi(%neg(%gp_rel(fname)))
109 // daddu $v1, $v0, $t9
110 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
111 const GlobalValue *FName = MF.getFunction();
112 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
113 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
114 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
115 .addReg(Mips::T9_64);
116 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
117 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
121 if (MF.getTarget().getRelocationModel() == Reloc::Static) {
122 // Set global register to __gnu_local_gp.
124 // lui $v0, %hi(__gnu_local_gp)
125 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
126 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
127 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
128 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
129 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
133 MF.getRegInfo().addLiveIn(Mips::T9);
134 MBB.addLiveIn(Mips::T9);
136 if (Subtarget.isABI_N32()) {
137 // lui $v0, %hi(%neg(%gp_rel(fname)))
138 // addu $v1, $v0, $t9
139 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
140 const GlobalValue *FName = MF.getFunction();
141 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
142 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
143 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
144 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
145 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
149 assert(Subtarget.isABI_O32());
151 // For O32 ABI, the following instruction sequence is emitted to initialize
152 // the global base register:
154 // 0. lui $2, %hi(_gp_disp)
155 // 1. addiu $2, $2, %lo(_gp_disp)
156 // 2. addu $globalbasereg, $2, $t9
158 // We emit only the last instruction here.
160 // GNU linker requires that the first two instructions appear at the beginning
161 // of a function and no instructions be inserted before or between them.
162 // The two instructions are emitted during lowering to MC layer in order to
163 // avoid any reordering.
165 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
166 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
168 MF.getRegInfo().addLiveIn(Mips::V0);
169 MBB.addLiveIn(Mips::V0);
170 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
171 .addReg(Mips::V0).addReg(Mips::T9);
174 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
175 initGlobalBaseReg(MF);
177 MachineRegisterInfo *MRI = &MF.getRegInfo();
179 for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
181 for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I)
182 replaceUsesWithZeroReg(MRI, *I);
185 /// Select multiply instructions.
186 std::pair<SDNode*, SDNode*>
187 MipsSEDAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, DebugLoc DL, EVT Ty,
188 bool HasLo, bool HasHi) {
189 SDNode *Lo = 0, *Hi = 0;
190 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
192 SDValue InFlag = SDValue(Mul, 0);
195 unsigned Opcode = (Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64);
196 Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
197 InFlag = SDValue(Lo, 1);
200 unsigned Opcode = (Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64);
201 Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InFlag);
203 return std::make_pair(Lo, Hi);
206 SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
207 SDValue CmpLHS, DebugLoc DL,
208 SDNode *Node) const {
209 unsigned Opc = InFlag.getOpcode(); (void)Opc;
211 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
212 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
213 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
215 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
216 SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
217 EVT VT = LHS.getValueType();
219 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops, 2);
220 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,
221 SDValue(Carry, 0), RHS);
222 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
223 SDValue(AddCarry, 0));
226 /// ComplexPattern used on MipsInstrInfo
227 /// Used on Mips Load/Store instructions
228 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
229 SDValue &Offset) const {
230 EVT ValTy = Addr.getValueType();
232 // if Address is FI, get the TargetFrameIndex.
233 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
234 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
235 Offset = CurDAG->getTargetConstant(0, ValTy);
239 // on PIC code Load GA
240 if (Addr.getOpcode() == MipsISD::Wrapper) {
241 Base = Addr.getOperand(0);
242 Offset = Addr.getOperand(1);
246 if (TM.getRelocationModel() != Reloc::PIC_) {
247 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
248 Addr.getOpcode() == ISD::TargetGlobalAddress))
252 // Addresses of the form FI+const or FI|const
253 if (CurDAG->isBaseWithConstantOffset(Addr)) {
254 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
255 if (isInt<16>(CN->getSExtValue())) {
257 // If the first operand is a FI, get the TargetFI Node
258 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
259 (Addr.getOperand(0)))
260 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
262 Base = Addr.getOperand(0);
264 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
269 // Operand is a result from an ADD.
270 if (Addr.getOpcode() == ISD::ADD) {
271 // When loading from constant pools, load the lower address part in
272 // the instruction itself. Example, instead of:
273 // lui $2, %hi($CPI1_0)
274 // addiu $2, $2, %lo($CPI1_0)
277 // lui $2, %hi($CPI1_0)
278 // lwc1 $f0, %lo($CPI1_0)($2)
279 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
280 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
281 SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
282 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
283 isa<JumpTableSDNode>(Opnd0)) {
284 Base = Addr.getOperand(0);
294 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
295 SDValue &Offset) const {
297 Offset = CurDAG->getTargetConstant(0, Addr.getValueType());
301 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
302 SDValue &Offset) const {
303 return selectAddrRegImm(Addr, Base, Offset) ||
304 selectAddrDefault(Addr, Base, Offset);
307 std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
308 unsigned Opcode = Node->getOpcode();
309 DebugLoc DL = Node->getDebugLoc();
312 // Instruction Selection not handled by the auto-generated
313 // tablegen selection should be handled here.
315 EVT NodeTy = Node->getValueType(0);
323 SDValue InFlag = Node->getOperand(2);
324 Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node);
325 return std::make_pair(true, Result);
329 SDValue InFlag = Node->getOperand(2);
330 Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);
331 return std::make_pair(true, Result);
334 /// Mul with two results
336 case ISD::UMUL_LOHI: {
337 if (NodeTy == MVT::i32)
338 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
340 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT);
342 std::pair<SDNode*, SDNode*> LoHi = selectMULT(Node, MultOpc, DL, NodeTy,
345 if (!SDValue(Node, 0).use_empty())
346 ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
348 if (!SDValue(Node, 1).use_empty())
349 ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
351 return std::make_pair(true, (SDNode*)NULL);
356 // Mips32 has a 32-bit three operand mul instruction.
357 if (Subtarget.hasMips32() && NodeTy == MVT::i32)
359 MultOpc = NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT;
360 Result = selectMULT(Node, MultOpc, DL, NodeTy, true, false).first;
361 return std::make_pair(true, Result);
365 if (NodeTy == MVT::i32)
366 MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
368 MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT);
370 Result = selectMULT(Node, MultOpc, DL, NodeTy, false, true).second;
371 return std::make_pair(true, Result);
374 case ISD::ConstantFP: {
375 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
376 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
377 if (Subtarget.hasMips64()) {
378 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
379 Mips::ZERO_64, MVT::i64);
380 Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
382 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
383 Mips::ZERO, MVT::i32);
384 Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
388 return std::make_pair(true, Result);
393 case ISD::Constant: {
394 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
395 unsigned Size = CN->getValueSizeInBits(0);
400 MipsAnalyzeImmediate AnalyzeImm;
401 int64_t Imm = CN->getSExtValue();
403 const MipsAnalyzeImmediate::InstSeq &Seq =
404 AnalyzeImm.Analyze(Imm, Size, false);
406 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
407 DebugLoc DL = CN->getDebugLoc();
409 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
412 // The first instruction can be a LUi which is different from other
413 // instructions (ADDiu, ORI and SLL) in that it does not have a register
415 if (Inst->Opc == Mips::LUi64)
416 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
419 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
420 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
423 // The remaining instructions in the sequence are handled here.
424 for (++Inst; Inst != Seq.end(); ++Inst) {
425 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
427 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
428 SDValue(RegOpnd, 0), ImmOpnd);
431 return std::make_pair(true, RegOpnd);
434 case MipsISD::ThreadPointer: {
435 EVT PtrVT = TLI.getPointerTy();
436 unsigned RdhwrOpc, SrcReg, DestReg;
438 if (PtrVT == MVT::i32) {
439 RdhwrOpc = Mips::RDHWR;
440 SrcReg = Mips::HWR29;
443 RdhwrOpc = Mips::RDHWR64;
444 SrcReg = Mips::HWR29_64;
445 DestReg = Mips::V1_64;
449 CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
450 Node->getValueType(0),
451 CurDAG->getRegister(SrcReg, PtrVT));
452 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
454 SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
455 ReplaceUses(SDValue(Node, 0), ResNode);
456 return std::make_pair(true, ResNode.getNode());
459 case MipsISD::InsertLOHI: {
460 unsigned RCID = Subtarget.hasDSP() ? Mips::ACRegsDSPRegClassID :
461 Mips::ACRegsRegClassID;
462 SDValue RegClass = CurDAG->getTargetConstant(RCID, MVT::i32);
463 SDValue LoIdx = CurDAG->getTargetConstant(Mips::sub_lo, MVT::i32);
464 SDValue HiIdx = CurDAG->getTargetConstant(Mips::sub_hi, MVT::i32);
465 const SDValue Ops[] = { RegClass, Node->getOperand(0), LoIdx,
466 Node->getOperand(1), HiIdx };
467 SDNode *Res = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
468 MVT::Untyped, Ops, 5);
469 return std::make_pair(true, Res);
473 return std::make_pair(false, (SDNode*)NULL);
476 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
477 return new MipsSEDAGToDAGISel(TM);