1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
14 #include "MipsSEISelDAGToDAG.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "MipsAnalyzeImmediate.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsRegisterInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 #include "llvm/IR/CFG.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetMachine.h"
37 #define DEBUG_TYPE "mips-isel"
39 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
40 Subtarget = &TM.getSubtarget<MipsSubtarget>();
41 if (Subtarget->inMips16Mode())
43 return MipsDAGToDAGISel::runOnMachineFunction(MF);
46 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
47 MachineFunction &MF) {
48 MachineInstrBuilder MIB(MF, &MI);
49 unsigned Mask = MI.getOperand(1).getImm();
50 unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit;
53 MIB.addReg(Mips::DSPPos, Flag);
56 MIB.addReg(Mips::DSPSCount, Flag);
59 MIB.addReg(Mips::DSPCarry, Flag);
62 MIB.addReg(Mips::DSPOutFlag, Flag);
65 MIB.addReg(Mips::DSPCCond, Flag);
68 MIB.addReg(Mips::DSPEFI, Flag);
71 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
72 switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
74 llvm_unreachable("Could not map int to register");
75 case 0: return Mips::MSAIR;
76 case 1: return Mips::MSACSR;
77 case 2: return Mips::MSAAccess;
78 case 3: return Mips::MSASave;
79 case 4: return Mips::MSAModify;
80 case 5: return Mips::MSARequest;
81 case 6: return Mips::MSAMap;
82 case 7: return Mips::MSAUnmap;
86 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
87 const MachineInstr& MI) {
88 unsigned DstReg = 0, ZeroReg = 0;
90 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
91 if ((MI.getOpcode() == Mips::ADDiu) &&
92 (MI.getOperand(1).getReg() == Mips::ZERO) &&
93 (MI.getOperand(2).getImm() == 0)) {
94 DstReg = MI.getOperand(0).getReg();
96 } else if ((MI.getOpcode() == Mips::DADDiu) &&
97 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
98 (MI.getOperand(2).getImm() == 0)) {
99 DstReg = MI.getOperand(0).getReg();
100 ZeroReg = Mips::ZERO_64;
106 // Replace uses with ZeroReg.
107 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
108 E = MRI->use_end(); U != E;) {
109 MachineOperand &MO = *U;
110 unsigned OpNo = U.getOperandNo();
111 MachineInstr *MI = MO.getParent();
114 // Do not replace if it is a phi's operand or is tied to def operand.
115 if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
124 void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
125 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
127 if (!MipsFI->globalBaseRegSet())
130 MachineBasicBlock &MBB = MF.front();
131 MachineBasicBlock::iterator I = MBB.begin();
132 MachineRegisterInfo &RegInfo = MF.getRegInfo();
133 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
134 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
135 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
136 const TargetRegisterClass *RC;
138 RC = (Subtarget->isABI_N64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
140 V0 = RegInfo.createVirtualRegister(RC);
141 V1 = RegInfo.createVirtualRegister(RC);
143 if (Subtarget->isABI_N64()) {
144 MF.getRegInfo().addLiveIn(Mips::T9_64);
145 MBB.addLiveIn(Mips::T9_64);
147 // lui $v0, %hi(%neg(%gp_rel(fname)))
148 // daddu $v1, $v0, $t9
149 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
150 const GlobalValue *FName = MF.getFunction();
151 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
152 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
153 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
154 .addReg(Mips::T9_64);
155 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
156 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
160 if (MF.getTarget().getRelocationModel() == Reloc::Static) {
161 // Set global register to __gnu_local_gp.
163 // lui $v0, %hi(__gnu_local_gp)
164 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
165 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
166 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
167 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
168 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
172 MF.getRegInfo().addLiveIn(Mips::T9);
173 MBB.addLiveIn(Mips::T9);
175 if (Subtarget->isABI_N32()) {
176 // lui $v0, %hi(%neg(%gp_rel(fname)))
177 // addu $v1, $v0, $t9
178 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
179 const GlobalValue *FName = MF.getFunction();
180 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
181 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
182 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
183 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
184 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
188 assert(Subtarget->isABI_O32());
190 // For O32 ABI, the following instruction sequence is emitted to initialize
191 // the global base register:
193 // 0. lui $2, %hi(_gp_disp)
194 // 1. addiu $2, $2, %lo(_gp_disp)
195 // 2. addu $globalbasereg, $2, $t9
197 // We emit only the last instruction here.
199 // GNU linker requires that the first two instructions appear at the beginning
200 // of a function and no instructions be inserted before or between them.
201 // The two instructions are emitted during lowering to MC layer in order to
202 // avoid any reordering.
204 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
205 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
207 MF.getRegInfo().addLiveIn(Mips::V0);
208 MBB.addLiveIn(Mips::V0);
209 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
210 .addReg(Mips::V0).addReg(Mips::T9);
213 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
214 initGlobalBaseReg(MF);
216 MachineRegisterInfo *MRI = &MF.getRegInfo();
218 for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
220 for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
221 if (I->getOpcode() == Mips::RDDSP)
222 addDSPCtrlRegOperands(false, *I, MF);
223 else if (I->getOpcode() == Mips::WRDSP)
224 addDSPCtrlRegOperands(true, *I, MF);
226 replaceUsesWithZeroReg(MRI, *I);
230 SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
231 SDValue CmpLHS, SDLoc DL,
232 SDNode *Node) const {
233 unsigned Opc = InFlag.getOpcode(); (void)Opc;
235 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
236 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
237 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
239 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
240 SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
241 EVT VT = LHS.getValueType();
243 unsigned SltOp = Mips::SLTu;
244 unsigned AddOp = Mips::ADDu;
245 if (VT == MVT::i64) {
246 SltOp = Mips::SLTu64;
250 SDValue Carry = SDValue(CurDAG->getMachineNode(SltOp, DL, VT, Ops), 0);
251 if (SltOp == Mips::SLTu64) {
252 // On 64-bit targets, sltu produces an i64 but our backend currently says
253 // that SLTu64 produces an i32. We need to fix this in the long run but for
254 // now, just make the DAG type-correct by asserting the upper bits are zero.
255 Carry = SDValue(CurDAG->getMachineNode(
256 Mips::SUBREG_TO_REG, DL, VT,
257 CurDAG->getTargetConstant(0, VT), Carry,
258 CurDAG->getTargetConstant(Mips::sub_32, MVT::i32)),
262 SDNode *AddCarry = CurDAG->getMachineNode(AddOp, DL, VT, Carry, RHS);
264 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
265 SDValue(AddCarry, 0));
269 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
270 SDValue &Offset) const {
271 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
272 EVT ValTy = Addr.getValueType();
274 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
275 Offset = CurDAG->getTargetConstant(0, ValTy);
281 /// Match frameindex+offset and frameindex|offset
282 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base,
284 unsigned OffsetBits) const {
285 if (CurDAG->isBaseWithConstantOffset(Addr)) {
286 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
287 if (isIntN(OffsetBits, CN->getSExtValue())) {
288 EVT ValTy = Addr.getValueType();
290 // If the first operand is a FI, get the TargetFI Node
291 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
292 (Addr.getOperand(0)))
293 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
295 Base = Addr.getOperand(0);
297 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
304 /// ComplexPattern used on MipsInstrInfo
305 /// Used on Mips Load/Store instructions
306 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
307 SDValue &Offset) const {
308 // if Address is FI, get the TargetFrameIndex.
309 if (selectAddrFrameIndex(Addr, Base, Offset))
312 // on PIC code Load GA
313 if (Addr.getOpcode() == MipsISD::Wrapper) {
314 Base = Addr.getOperand(0);
315 Offset = Addr.getOperand(1);
319 if (TM.getRelocationModel() != Reloc::PIC_) {
320 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
321 Addr.getOpcode() == ISD::TargetGlobalAddress))
325 // Addresses of the form FI+const or FI|const
326 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
329 // Operand is a result from an ADD.
330 if (Addr.getOpcode() == ISD::ADD) {
331 // When loading from constant pools, load the lower address part in
332 // the instruction itself. Example, instead of:
333 // lui $2, %hi($CPI1_0)
334 // addiu $2, $2, %lo($CPI1_0)
337 // lui $2, %hi($CPI1_0)
338 // lwc1 $f0, %lo($CPI1_0)($2)
339 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
340 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
341 SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
342 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
343 isa<JumpTableSDNode>(Opnd0)) {
344 Base = Addr.getOperand(0);
354 /// ComplexPattern used on MipsInstrInfo
355 /// Used on Mips Load/Store instructions
356 bool MipsSEDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base,
357 SDValue &Offset) const {
358 // Operand is a result from an ADD.
359 if (Addr.getOpcode() == ISD::ADD) {
360 Base = Addr.getOperand(0);
361 Offset = Addr.getOperand(1);
368 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
369 SDValue &Offset) const {
371 Offset = CurDAG->getTargetConstant(0, Addr.getValueType());
375 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
376 SDValue &Offset) const {
377 return selectAddrRegImm(Addr, Base, Offset) ||
378 selectAddrDefault(Addr, Base, Offset);
381 bool MipsSEDAGToDAGISel::selectAddrRegImm10(SDValue Addr, SDValue &Base,
382 SDValue &Offset) const {
383 if (selectAddrFrameIndex(Addr, Base, Offset))
386 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
392 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
393 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
394 SDValue &Offset) const {
395 if (selectAddrFrameIndex(Addr, Base, Offset))
398 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
404 bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
405 SDValue &Offset) const {
406 return selectAddrRegImm12(Addr, Base, Offset) ||
407 selectAddrDefault(Addr, Base, Offset);
410 bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
411 SDValue &Offset) const {
412 if (selectAddrRegImm10(Addr, Base, Offset))
415 if (selectAddrDefault(Addr, Base, Offset))
421 // Select constant vector splats.
423 // Returns true and sets Imm if:
425 // * N is a ISD::BUILD_VECTOR representing a constant splat
426 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
427 if (!Subtarget->hasMSA())
430 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
435 APInt SplatValue, SplatUndef;
436 unsigned SplatBitSize;
439 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
441 !Subtarget->isLittle()))
449 // Select constant vector splats.
451 // In addition to the requirements of selectVSplat(), this function returns
452 // true and sets Imm if:
453 // * The splat value is the same width as the elements of the vector
454 // * The splat value fits in an integer with the specified signed-ness and
457 // This function looks through ISD::BITCAST nodes.
458 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
459 // sometimes a shuffle in big-endian mode.
461 // It's worth noting that this function is not used as part of the selection
462 // of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
463 // instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
464 // MipsSEDAGToDAGISel::selectNode.
465 bool MipsSEDAGToDAGISel::
466 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
467 unsigned ImmBitSize) const {
469 EVT EltTy = N->getValueType(0).getVectorElementType();
471 if (N->getOpcode() == ISD::BITCAST)
472 N = N->getOperand(0);
474 if (selectVSplat (N.getNode(), ImmValue) &&
475 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
476 if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
477 (!Signed && ImmValue.isIntN(ImmBitSize))) {
478 Imm = CurDAG->getTargetConstant(ImmValue, EltTy);
486 // Select constant vector splats.
487 bool MipsSEDAGToDAGISel::
488 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
489 return selectVSplatCommon(N, Imm, false, 1);
492 bool MipsSEDAGToDAGISel::
493 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
494 return selectVSplatCommon(N, Imm, false, 2);
497 bool MipsSEDAGToDAGISel::
498 selectVSplatUimm3(SDValue N, SDValue &Imm) const {
499 return selectVSplatCommon(N, Imm, false, 3);
502 // Select constant vector splats.
503 bool MipsSEDAGToDAGISel::
504 selectVSplatUimm4(SDValue N, SDValue &Imm) const {
505 return selectVSplatCommon(N, Imm, false, 4);
508 // Select constant vector splats.
509 bool MipsSEDAGToDAGISel::
510 selectVSplatUimm5(SDValue N, SDValue &Imm) const {
511 return selectVSplatCommon(N, Imm, false, 5);
514 // Select constant vector splats.
515 bool MipsSEDAGToDAGISel::
516 selectVSplatUimm6(SDValue N, SDValue &Imm) const {
517 return selectVSplatCommon(N, Imm, false, 6);
520 // Select constant vector splats.
521 bool MipsSEDAGToDAGISel::
522 selectVSplatUimm8(SDValue N, SDValue &Imm) const {
523 return selectVSplatCommon(N, Imm, false, 8);
526 // Select constant vector splats.
527 bool MipsSEDAGToDAGISel::
528 selectVSplatSimm5(SDValue N, SDValue &Imm) const {
529 return selectVSplatCommon(N, Imm, true, 5);
532 // Select constant vector splats whose value is a power of 2.
534 // In addition to the requirements of selectVSplat(), this function returns
535 // true and sets Imm if:
536 // * The splat value is the same width as the elements of the vector
537 // * The splat value is a power of two.
539 // This function looks through ISD::BITCAST nodes.
540 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
541 // sometimes a shuffle in big-endian mode.
542 bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
544 EVT EltTy = N->getValueType(0).getVectorElementType();
546 if (N->getOpcode() == ISD::BITCAST)
547 N = N->getOperand(0);
549 if (selectVSplat (N.getNode(), ImmValue) &&
550 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
551 int32_t Log2 = ImmValue.exactLogBase2();
554 Imm = CurDAG->getTargetConstant(Log2, EltTy);
562 // Select constant vector splats whose value only has a consecutive sequence
563 // of left-most bits set (e.g. 0b11...1100...00).
565 // In addition to the requirements of selectVSplat(), this function returns
566 // true and sets Imm if:
567 // * The splat value is the same width as the elements of the vector
568 // * The splat value is a consecutive sequence of left-most bits.
570 // This function looks through ISD::BITCAST nodes.
571 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
572 // sometimes a shuffle in big-endian mode.
573 bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
575 EVT EltTy = N->getValueType(0).getVectorElementType();
577 if (N->getOpcode() == ISD::BITCAST)
578 N = N->getOperand(0);
580 if (selectVSplat(N.getNode(), ImmValue) &&
581 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
582 // Extract the run of set bits starting with bit zero from the bitwise
583 // inverse of ImmValue, and test that the inverse of this is the same
584 // as the original value.
585 if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
587 Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
595 // Select constant vector splats whose value only has a consecutive sequence
596 // of right-most bits set (e.g. 0b00...0011...11).
598 // In addition to the requirements of selectVSplat(), this function returns
599 // true and sets Imm if:
600 // * The splat value is the same width as the elements of the vector
601 // * The splat value is a consecutive sequence of right-most bits.
603 // This function looks through ISD::BITCAST nodes.
604 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
605 // sometimes a shuffle in big-endian mode.
606 bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
608 EVT EltTy = N->getValueType(0).getVectorElementType();
610 if (N->getOpcode() == ISD::BITCAST)
611 N = N->getOperand(0);
613 if (selectVSplat(N.getNode(), ImmValue) &&
614 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
615 // Extract the run of set bits starting with bit zero, and test that the
616 // result is the same as the original value
617 if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
618 Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
626 bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
627 SDValue &Imm) const {
629 EVT EltTy = N->getValueType(0).getVectorElementType();
631 if (N->getOpcode() == ISD::BITCAST)
632 N = N->getOperand(0);
634 if (selectVSplat(N.getNode(), ImmValue) &&
635 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
636 int32_t Log2 = (~ImmValue).exactLogBase2();
639 Imm = CurDAG->getTargetConstant(Log2, EltTy);
647 std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
648 unsigned Opcode = Node->getOpcode();
652 // Instruction Selection not handled by the auto-generated
653 // tablegen selection should be handled here.
661 SDValue InFlag = Node->getOperand(2);
663 Node->getValueType(0) == MVT::i64 ? Mips::DSUBu : Mips::SUBu;
664 Result = selectAddESubE(SubOp, InFlag, InFlag.getOperand(0), DL, Node);
665 return std::make_pair(true, Result);
669 if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
671 SDValue InFlag = Node->getOperand(2);
673 Node->getValueType(0) == MVT::i64 ? Mips::DADDu : Mips::ADDu;
674 Result = selectAddESubE(AddOp, InFlag, InFlag.getValue(0), DL, Node);
675 return std::make_pair(true, Result);
678 case ISD::ConstantFP: {
679 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
680 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
681 if (Subtarget->isGP64bit()) {
682 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
683 Mips::ZERO_64, MVT::i64);
684 Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
685 } else if (Subtarget->isFP64bit()) {
686 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
687 Mips::ZERO, MVT::i32);
688 Result = CurDAG->getMachineNode(Mips::BuildPairF64_64, DL, MVT::f64,
691 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
692 Mips::ZERO, MVT::i32);
693 Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
697 return std::make_pair(true, Result);
702 case ISD::Constant: {
703 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
704 unsigned Size = CN->getValueSizeInBits(0);
709 MipsAnalyzeImmediate AnalyzeImm;
710 int64_t Imm = CN->getSExtValue();
712 const MipsAnalyzeImmediate::InstSeq &Seq =
713 AnalyzeImm.Analyze(Imm, Size, false);
715 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
718 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
721 // The first instruction can be a LUi which is different from other
722 // instructions (ADDiu, ORI and SLL) in that it does not have a register
724 if (Inst->Opc == Mips::LUi64)
725 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
728 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
729 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
732 // The remaining instructions in the sequence are handled here.
733 for (++Inst; Inst != Seq.end(); ++Inst) {
734 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
736 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
737 SDValue(RegOpnd, 0), ImmOpnd);
740 return std::make_pair(true, RegOpnd);
743 case ISD::INTRINSIC_W_CHAIN: {
744 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
748 case Intrinsic::mips_cfcmsa: {
749 SDValue ChainIn = Node->getOperand(0);
750 SDValue RegIdx = Node->getOperand(2);
751 SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
752 getMSACtrlReg(RegIdx), MVT::i32);
753 return std::make_pair(true, Reg.getNode());
759 case ISD::INTRINSIC_WO_CHAIN: {
760 switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
764 case Intrinsic::mips_move_v:
765 // Like an assignment but will always produce a move.v even if
767 return std::make_pair(true,
768 CurDAG->getMachineNode(Mips::MOVE_V, DL,
769 Node->getValueType(0),
770 Node->getOperand(1)));
775 case ISD::INTRINSIC_VOID: {
776 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
780 case Intrinsic::mips_ctcmsa: {
781 SDValue ChainIn = Node->getOperand(0);
782 SDValue RegIdx = Node->getOperand(2);
783 SDValue Value = Node->getOperand(3);
784 SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
785 getMSACtrlReg(RegIdx), Value);
786 return std::make_pair(true, ChainOut.getNode());
792 case MipsISD::ThreadPointer: {
793 EVT PtrVT = getTargetLowering()->getPointerTy();
794 unsigned RdhwrOpc, DestReg;
796 if (PtrVT == MVT::i32) {
797 RdhwrOpc = Mips::RDHWR;
800 RdhwrOpc = Mips::RDHWR64;
801 DestReg = Mips::V1_64;
805 CurDAG->getMachineNode(RdhwrOpc, SDLoc(Node),
806 Node->getValueType(0),
807 CurDAG->getRegister(Mips::HWR29, MVT::i32));
808 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
810 SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
811 ReplaceUses(SDValue(Node, 0), ResNode);
812 return std::make_pair(true, ResNode.getNode());
815 case ISD::BUILD_VECTOR: {
816 // Select appropriate ldi.[bhwd] instructions for constant splats of
817 // 128-bit when MSA is enabled. Fixup any register class mismatches that
818 // occur as a result.
820 // This allows the compiler to use a wider range of immediates than would
821 // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
822 // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
823 // 0x01010101 } without using a constant pool. This would be sub-optimal
824 // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
825 // same set/ of registers. Similarly, ldi.h isn't capable of producing {
826 // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
828 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
829 APInt SplatValue, SplatUndef;
830 unsigned SplatBitSize;
833 EVT ResVecTy = BVN->getValueType(0);
836 if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
837 return std::make_pair(false, nullptr);
839 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
841 !Subtarget->isLittle()))
842 return std::make_pair(false, nullptr);
844 switch (SplatBitSize) {
846 return std::make_pair(false, nullptr);
849 ViaVecTy = MVT::v16i8;
853 ViaVecTy = MVT::v8i16;
857 ViaVecTy = MVT::v4i32;
861 ViaVecTy = MVT::v2i64;
865 if (!SplatValue.isSignedIntN(10))
866 return std::make_pair(false, nullptr);
868 SDValue Imm = CurDAG->getTargetConstant(SplatValue,
869 ViaVecTy.getVectorElementType());
871 SDNode *Res = CurDAG->getMachineNode(LdiOp, SDLoc(Node), ViaVecTy, Imm);
873 if (ResVecTy != ViaVecTy) {
874 // If LdiOp is writing to a different register class to ResVecTy, then
875 // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
876 // since the source and destination register sets contain the same
878 const TargetLowering *TLI = getTargetLowering();
879 MVT ResVecTySimple = ResVecTy.getSimpleVT();
880 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
881 Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, SDLoc(Node),
882 ResVecTy, SDValue(Res, 0),
883 CurDAG->getTargetConstant(RC->getID(),
887 return std::make_pair(true, Res);
892 return std::make_pair(false, nullptr);
895 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
896 return new MipsSEDAGToDAGISel(TM);