1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
15 #include "MipsSEISelDAGToDAG.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
18 #include "MipsAnalyzeImmediate.h"
19 #include "MipsMachineFunction.h"
20 #include "MipsRegisterInfo.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CFG.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
38 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
39 if (Subtarget.inMips16Mode())
41 return MipsDAGToDAGISel::runOnMachineFunction(MF);
44 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
45 MachineFunction &MF) {
46 MachineInstrBuilder MIB(MF, &MI);
47 unsigned Mask = MI.getOperand(1).getImm();
48 unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit;
51 MIB.addReg(Mips::DSPPos, Flag);
54 MIB.addReg(Mips::DSPSCount, Flag);
57 MIB.addReg(Mips::DSPCarry, Flag);
60 MIB.addReg(Mips::DSPOutFlag, Flag);
63 MIB.addReg(Mips::DSPCCond, Flag);
66 MIB.addReg(Mips::DSPEFI, Flag);
69 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
70 switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
72 llvm_unreachable("Could not map int to register");
73 case 0: return Mips::MSAIR;
74 case 1: return Mips::MSACSR;
75 case 2: return Mips::MSAAccess;
76 case 3: return Mips::MSASave;
77 case 4: return Mips::MSAModify;
78 case 5: return Mips::MSARequest;
79 case 6: return Mips::MSAMap;
80 case 7: return Mips::MSAUnmap;
84 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
85 const MachineInstr& MI) {
86 unsigned DstReg = 0, ZeroReg = 0;
88 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
89 if ((MI.getOpcode() == Mips::ADDiu) &&
90 (MI.getOperand(1).getReg() == Mips::ZERO) &&
91 (MI.getOperand(2).getImm() == 0)) {
92 DstReg = MI.getOperand(0).getReg();
94 } else if ((MI.getOpcode() == Mips::DADDiu) &&
95 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
96 (MI.getOperand(2).getImm() == 0)) {
97 DstReg = MI.getOperand(0).getReg();
98 ZeroReg = Mips::ZERO_64;
104 // Replace uses with ZeroReg.
105 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
106 E = MRI->use_end(); U != E;) {
107 MachineOperand &MO = U.getOperand();
108 unsigned OpNo = U.getOperandNo();
109 MachineInstr *MI = MO.getParent();
112 // Do not replace if it is a phi's operand or is tied to def operand.
113 if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
122 void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
123 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
125 if (!MipsFI->globalBaseRegSet())
128 MachineBasicBlock &MBB = MF.front();
129 MachineBasicBlock::iterator I = MBB.begin();
130 MachineRegisterInfo &RegInfo = MF.getRegInfo();
131 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
132 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
133 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
134 const TargetRegisterClass *RC;
136 if (Subtarget.isABI_N64())
137 RC = (const TargetRegisterClass*)&Mips::GPR64RegClass;
139 RC = (const TargetRegisterClass*)&Mips::GPR32RegClass;
141 V0 = RegInfo.createVirtualRegister(RC);
142 V1 = RegInfo.createVirtualRegister(RC);
144 if (Subtarget.isABI_N64()) {
145 MF.getRegInfo().addLiveIn(Mips::T9_64);
146 MBB.addLiveIn(Mips::T9_64);
148 // lui $v0, %hi(%neg(%gp_rel(fname)))
149 // daddu $v1, $v0, $t9
150 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
151 const GlobalValue *FName = MF.getFunction();
152 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
153 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
154 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
155 .addReg(Mips::T9_64);
156 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
157 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
161 if (MF.getTarget().getRelocationModel() == Reloc::Static) {
162 // Set global register to __gnu_local_gp.
164 // lui $v0, %hi(__gnu_local_gp)
165 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
166 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
167 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
168 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
169 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
173 MF.getRegInfo().addLiveIn(Mips::T9);
174 MBB.addLiveIn(Mips::T9);
176 if (Subtarget.isABI_N32()) {
177 // lui $v0, %hi(%neg(%gp_rel(fname)))
178 // addu $v1, $v0, $t9
179 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
180 const GlobalValue *FName = MF.getFunction();
181 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
182 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
183 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
184 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
185 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
189 assert(Subtarget.isABI_O32());
191 // For O32 ABI, the following instruction sequence is emitted to initialize
192 // the global base register:
194 // 0. lui $2, %hi(_gp_disp)
195 // 1. addiu $2, $2, %lo(_gp_disp)
196 // 2. addu $globalbasereg, $2, $t9
198 // We emit only the last instruction here.
200 // GNU linker requires that the first two instructions appear at the beginning
201 // of a function and no instructions be inserted before or between them.
202 // The two instructions are emitted during lowering to MC layer in order to
203 // avoid any reordering.
205 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
206 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
208 MF.getRegInfo().addLiveIn(Mips::V0);
209 MBB.addLiveIn(Mips::V0);
210 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
211 .addReg(Mips::V0).addReg(Mips::T9);
214 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
215 initGlobalBaseReg(MF);
217 MachineRegisterInfo *MRI = &MF.getRegInfo();
219 for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
221 for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
222 if (I->getOpcode() == Mips::RDDSP)
223 addDSPCtrlRegOperands(false, *I, MF);
224 else if (I->getOpcode() == Mips::WRDSP)
225 addDSPCtrlRegOperands(true, *I, MF);
227 replaceUsesWithZeroReg(MRI, *I);
231 SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
232 SDValue CmpLHS, SDLoc DL,
233 SDNode *Node) const {
234 unsigned Opc = InFlag.getOpcode(); (void)Opc;
236 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
237 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
238 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
240 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
241 SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
242 EVT VT = LHS.getValueType();
244 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops);
245 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,
246 SDValue(Carry, 0), RHS);
247 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
248 SDValue(AddCarry, 0));
251 /// ComplexPattern used on MipsInstrInfo
252 /// Used on Mips Load/Store instructions
253 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
254 SDValue &Offset) const {
255 EVT ValTy = Addr.getValueType();
257 // if Address is FI, get the TargetFrameIndex.
258 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
259 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
260 Offset = CurDAG->getTargetConstant(0, ValTy);
264 // on PIC code Load GA
265 if (Addr.getOpcode() == MipsISD::Wrapper) {
266 Base = Addr.getOperand(0);
267 Offset = Addr.getOperand(1);
271 if (TM.getRelocationModel() != Reloc::PIC_) {
272 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
273 Addr.getOpcode() == ISD::TargetGlobalAddress))
277 // Addresses of the form FI+const or FI|const
278 if (CurDAG->isBaseWithConstantOffset(Addr)) {
279 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
280 if (isInt<16>(CN->getSExtValue())) {
282 // If the first operand is a FI, get the TargetFI Node
283 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
284 (Addr.getOperand(0)))
285 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
287 Base = Addr.getOperand(0);
289 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
294 // Operand is a result from an ADD.
295 if (Addr.getOpcode() == ISD::ADD) {
296 // When loading from constant pools, load the lower address part in
297 // the instruction itself. Example, instead of:
298 // lui $2, %hi($CPI1_0)
299 // addiu $2, $2, %lo($CPI1_0)
302 // lui $2, %hi($CPI1_0)
303 // lwc1 $f0, %lo($CPI1_0)($2)
304 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
305 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
306 SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
307 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
308 isa<JumpTableSDNode>(Opnd0)) {
309 Base = Addr.getOperand(0);
319 /// ComplexPattern used on MipsInstrInfo
320 /// Used on Mips Load/Store instructions
321 bool MipsSEDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base,
322 SDValue &Offset) const {
323 // Operand is a result from an ADD.
324 if (Addr.getOpcode() == ISD::ADD) {
325 Base = Addr.getOperand(0);
326 Offset = Addr.getOperand(1);
333 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
334 SDValue &Offset) const {
336 Offset = CurDAG->getTargetConstant(0, Addr.getValueType());
340 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
341 SDValue &Offset) const {
342 return selectAddrRegImm(Addr, Base, Offset) ||
343 selectAddrDefault(Addr, Base, Offset);
346 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
347 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
348 SDValue &Offset) const {
349 EVT ValTy = Addr.getValueType();
351 // Addresses of the form FI+const or FI|const
352 if (CurDAG->isBaseWithConstantOffset(Addr)) {
353 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
354 if (isInt<12>(CN->getSExtValue())) {
356 // If the first operand is a FI then get the TargetFI Node
357 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
358 (Addr.getOperand(0)))
359 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
361 Base = Addr.getOperand(0);
363 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
371 bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
372 SDValue &Offset) const {
373 return selectAddrRegImm12(Addr, Base, Offset) ||
374 selectAddrDefault(Addr, Base, Offset);
377 // Select constant vector splats.
379 // Returns true and sets Imm if:
381 // * N is a ISD::BUILD_VECTOR representing a constant splat
382 // * The splat value fits in a signed 32-bit value.
384 // That last requirement isn't strictly a requirement of the instruction set
385 // but it simplifies the callers by allowing them to assume they don't have to
386 // handle 64-bit values. The callers will also be placing stricter requirements
387 // on the immediates so this doesn't prohibit selection of legal immediates.
388 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
389 if (!Subtarget.hasMSA())
392 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
397 APInt SplatValue, SplatUndef;
398 unsigned SplatBitSize;
401 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
403 !Subtarget.isLittle()))
406 // None of the immediate forms can handle more than 32 bits
407 if (!SplatValue.isIntN(32))
415 // Select constant vector splats.
417 // In addition to the requirements of selectVSplat(), this function returns
418 // true and sets Imm if:
419 // * The splat value is the same width as the elements of the vector
420 // * The splat value fits in an integer with the specified signed-ness and
423 // This function looks through ISD::BITCAST nodes.
424 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
425 // sometimes a shuffle in big-endian mode.
427 // It's worth noting that this function is not used as part of the selection
428 // of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
429 // instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
430 // MipsSEDAGToDAGISel::selectNode.
431 bool MipsSEDAGToDAGISel::
432 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
433 unsigned ImmBitSize) const {
435 EVT EltTy = N->getValueType(0).getVectorElementType();
437 if (N->getOpcode() == ISD::BITCAST)
438 N = N->getOperand(0);
440 if (selectVSplat (N.getNode(), ImmValue) &&
441 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
442 if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
443 (!Signed && ImmValue.isIntN(ImmBitSize))) {
444 Imm = CurDAG->getTargetConstant(ImmValue, EltTy);
452 // Select constant vector splats.
453 bool MipsSEDAGToDAGISel::
454 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
455 return selectVSplatCommon(N, Imm, false, 1);
458 bool MipsSEDAGToDAGISel::
459 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
460 return selectVSplatCommon(N, Imm, false, 2);
463 bool MipsSEDAGToDAGISel::
464 selectVSplatUimm3(SDValue N, SDValue &Imm) const {
465 return selectVSplatCommon(N, Imm, false, 3);
468 // Select constant vector splats.
469 bool MipsSEDAGToDAGISel::
470 selectVSplatUimm4(SDValue N, SDValue &Imm) const {
471 return selectVSplatCommon(N, Imm, false, 4);
474 // Select constant vector splats.
475 bool MipsSEDAGToDAGISel::
476 selectVSplatUimm5(SDValue N, SDValue &Imm) const {
477 return selectVSplatCommon(N, Imm, false, 5);
480 // Select constant vector splats.
481 bool MipsSEDAGToDAGISel::
482 selectVSplatUimm6(SDValue N, SDValue &Imm) const {
483 return selectVSplatCommon(N, Imm, false, 6);
486 // Select constant vector splats.
487 bool MipsSEDAGToDAGISel::
488 selectVSplatUimm8(SDValue N, SDValue &Imm) const {
489 return selectVSplatCommon(N, Imm, false, 8);
492 // Select constant vector splats.
493 bool MipsSEDAGToDAGISel::
494 selectVSplatSimm5(SDValue N, SDValue &Imm) const {
495 return selectVSplatCommon(N, Imm, true, 5);
498 // Select constant vector splats whose value is a power of 2.
500 // In addition to the requirements of selectVSplat(), this function returns
501 // true and sets Imm if:
502 // * The splat value is the same width as the elements of the vector
503 // * The splat value is a power of two.
505 // This function looks through ISD::BITCAST nodes.
506 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
507 // sometimes a shuffle in big-endian mode.
508 bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
510 EVT EltTy = N->getValueType(0).getVectorElementType();
512 if (N->getOpcode() == ISD::BITCAST)
513 N = N->getOperand(0);
515 if (selectVSplat (N.getNode(), ImmValue) &&
516 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
517 int32_t Log2 = ImmValue.exactLogBase2();
520 Imm = CurDAG->getTargetConstant(Log2, EltTy);
528 std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
529 unsigned Opcode = Node->getOpcode();
533 // Instruction Selection not handled by the auto-generated
534 // tablegen selection should be handled here.
542 SDValue InFlag = Node->getOperand(2);
543 Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node);
544 return std::make_pair(true, Result);
548 if (Subtarget.hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
550 SDValue InFlag = Node->getOperand(2);
551 Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);
552 return std::make_pair(true, Result);
555 case ISD::ConstantFP: {
556 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
557 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
558 if (Subtarget.hasMips64()) {
559 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
560 Mips::ZERO_64, MVT::i64);
561 Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
563 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
564 Mips::ZERO, MVT::i32);
565 Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
569 return std::make_pair(true, Result);
574 case ISD::Constant: {
575 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
576 unsigned Size = CN->getValueSizeInBits(0);
581 MipsAnalyzeImmediate AnalyzeImm;
582 int64_t Imm = CN->getSExtValue();
584 const MipsAnalyzeImmediate::InstSeq &Seq =
585 AnalyzeImm.Analyze(Imm, Size, false);
587 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
590 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
593 // The first instruction can be a LUi which is different from other
594 // instructions (ADDiu, ORI and SLL) in that it does not have a register
596 if (Inst->Opc == Mips::LUi64)
597 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
600 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
601 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
604 // The remaining instructions in the sequence are handled here.
605 for (++Inst; Inst != Seq.end(); ++Inst) {
606 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
608 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
609 SDValue(RegOpnd, 0), ImmOpnd);
612 return std::make_pair(true, RegOpnd);
615 case ISD::INTRINSIC_W_CHAIN: {
616 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
620 case Intrinsic::mips_cfcmsa: {
621 SDValue ChainIn = Node->getOperand(0);
622 SDValue RegIdx = Node->getOperand(2);
623 SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
624 getMSACtrlReg(RegIdx), MVT::i32);
625 return std::make_pair(true, Reg.getNode());
631 case ISD::INTRINSIC_WO_CHAIN: {
632 switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
636 case Intrinsic::mips_move_v:
637 // Like an assignment but will always produce a move.v even if
639 return std::make_pair(true,
640 CurDAG->getMachineNode(Mips::MOVE_V, DL,
641 Node->getValueType(0),
642 Node->getOperand(1)));
647 case ISD::INTRINSIC_VOID: {
648 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
652 case Intrinsic::mips_ctcmsa: {
653 SDValue ChainIn = Node->getOperand(0);
654 SDValue RegIdx = Node->getOperand(2);
655 SDValue Value = Node->getOperand(3);
656 SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
657 getMSACtrlReg(RegIdx), Value);
658 return std::make_pair(true, ChainOut.getNode());
664 case MipsISD::ThreadPointer: {
665 EVT PtrVT = getTargetLowering()->getPointerTy();
666 unsigned RdhwrOpc, DestReg;
668 if (PtrVT == MVT::i32) {
669 RdhwrOpc = Mips::RDHWR;
672 RdhwrOpc = Mips::RDHWR64;
673 DestReg = Mips::V1_64;
677 CurDAG->getMachineNode(RdhwrOpc, SDLoc(Node),
678 Node->getValueType(0),
679 CurDAG->getRegister(Mips::HWR29, MVT::i32));
680 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
682 SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
683 ReplaceUses(SDValue(Node, 0), ResNode);
684 return std::make_pair(true, ResNode.getNode());
687 case MipsISD::MTLOHI: {
688 unsigned RCID = Subtarget.hasDSP() ? Mips::ACC64DSPRegClassID :
689 Mips::ACC64RegClassID;
690 SDValue RegClass = CurDAG->getTargetConstant(RCID, MVT::i32);
691 SDValue LoIdx = CurDAG->getTargetConstant(Mips::sub_lo, MVT::i32);
692 SDValue HiIdx = CurDAG->getTargetConstant(Mips::sub_hi, MVT::i32);
693 const SDValue Ops[] = { RegClass, Node->getOperand(0), LoIdx,
694 Node->getOperand(1), HiIdx };
695 SDNode *Res = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
697 return std::make_pair(true, Res);
700 case ISD::BUILD_VECTOR: {
701 // Select appropriate ldi.[bhwd] instructions for constant splats of
702 // 128-bit when MSA is enabled. Fixup any register class mismatches that
703 // occur as a result.
705 // This allows the compiler to use a wider range of immediates than would
706 // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
707 // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
708 // 0x01010101 } without using a constant pool. This would be sub-optimal
709 // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
710 // same set/ of registers. Similarly, ldi.h isn't capable of producing {
711 // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
713 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
714 APInt SplatValue, SplatUndef;
715 unsigned SplatBitSize;
718 EVT ResVecTy = BVN->getValueType(0);
721 if (!Subtarget.hasMSA() || !BVN->getValueType(0).is128BitVector())
722 return std::make_pair(false, (SDNode*)NULL);
724 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
726 !Subtarget.isLittle()))
727 return std::make_pair(false, (SDNode*)NULL);
729 switch (SplatBitSize) {
731 return std::make_pair(false, (SDNode*)NULL);
734 ViaVecTy = MVT::v16i8;
738 ViaVecTy = MVT::v8i16;
742 ViaVecTy = MVT::v4i32;
746 ViaVecTy = MVT::v2i64;
750 if (!SplatValue.isSignedIntN(10))
751 return std::make_pair(false, (SDNode*)NULL);
753 SDValue Imm = CurDAG->getTargetConstant(SplatValue,
754 ViaVecTy.getVectorElementType());
756 SDNode *Res = CurDAG->getMachineNode(LdiOp, SDLoc(Node), ViaVecTy, Imm);
758 if (ResVecTy != ViaVecTy) {
759 // If LdiOp is writing to a different register class to ResVecTy, then
760 // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
761 // since the source and destination register sets contain the same
763 const TargetLowering *TLI = getTargetLowering();
764 MVT ResVecTySimple = ResVecTy.getSimpleVT();
765 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
766 Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, SDLoc(Node),
767 ResVecTy, SDValue(Res, 0),
768 CurDAG->getTargetConstant(RC->getID(),
772 return std::make_pair(true, Res);
777 return std::make_pair(false, (SDNode*)NULL);
780 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
781 return new MipsSEDAGToDAGISel(TM);