1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
14 #include "MipsSEISelDAGToDAG.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "MipsAnalyzeImmediate.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsRegisterInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 #include "llvm/IR/CFG.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetMachine.h"
37 #define DEBUG_TYPE "mips-isel"
39 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
40 Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
41 if (Subtarget->inMips16Mode())
43 return MipsDAGToDAGISel::runOnMachineFunction(MF);
46 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
47 MachineFunction &MF) {
48 MachineInstrBuilder MIB(MF, &MI);
49 unsigned Mask = MI.getOperand(1).getImm();
50 unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit;
53 MIB.addReg(Mips::DSPPos, Flag);
56 MIB.addReg(Mips::DSPSCount, Flag);
59 MIB.addReg(Mips::DSPCarry, Flag);
62 MIB.addReg(Mips::DSPOutFlag, Flag);
65 MIB.addReg(Mips::DSPCCond, Flag);
68 MIB.addReg(Mips::DSPEFI, Flag);
71 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
72 switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
74 llvm_unreachable("Could not map int to register");
75 case 0: return Mips::MSAIR;
76 case 1: return Mips::MSACSR;
77 case 2: return Mips::MSAAccess;
78 case 3: return Mips::MSASave;
79 case 4: return Mips::MSAModify;
80 case 5: return Mips::MSARequest;
81 case 6: return Mips::MSAMap;
82 case 7: return Mips::MSAUnmap;
86 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
87 const MachineInstr& MI) {
88 unsigned DstReg = 0, ZeroReg = 0;
90 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
91 if ((MI.getOpcode() == Mips::ADDiu) &&
92 (MI.getOperand(1).getReg() == Mips::ZERO) &&
93 (MI.getOperand(2).getImm() == 0)) {
94 DstReg = MI.getOperand(0).getReg();
96 } else if ((MI.getOpcode() == Mips::DADDiu) &&
97 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
98 (MI.getOperand(2).getImm() == 0)) {
99 DstReg = MI.getOperand(0).getReg();
100 ZeroReg = Mips::ZERO_64;
106 // Replace uses with ZeroReg.
107 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
108 E = MRI->use_end(); U != E;) {
109 MachineOperand &MO = *U;
110 unsigned OpNo = U.getOperandNo();
111 MachineInstr *MI = MO.getParent();
114 // Do not replace if it is a phi's operand or is tied to def operand.
115 if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
124 void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
125 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
127 if (!MipsFI->globalBaseRegSet())
130 MachineBasicBlock &MBB = MF.front();
131 MachineBasicBlock::iterator I = MBB.begin();
132 MachineRegisterInfo &RegInfo = MF.getRegInfo();
133 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
134 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
135 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
136 const TargetRegisterClass *RC;
137 const MipsABIInfo &ABI = static_cast<const MipsTargetMachine &>(TM).getABI();
138 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
140 V0 = RegInfo.createVirtualRegister(RC);
141 V1 = RegInfo.createVirtualRegister(RC);
144 MF.getRegInfo().addLiveIn(Mips::T9_64);
145 MBB.addLiveIn(Mips::T9_64);
147 // lui $v0, %hi(%neg(%gp_rel(fname)))
148 // daddu $v1, $v0, $t9
149 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
150 const GlobalValue *FName = MF.getFunction();
151 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
152 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
153 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
154 .addReg(Mips::T9_64);
155 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
156 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
160 if (MF.getTarget().getRelocationModel() == Reloc::Static) {
161 // Set global register to __gnu_local_gp.
163 // lui $v0, %hi(__gnu_local_gp)
164 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
165 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
166 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
167 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
168 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
172 MF.getRegInfo().addLiveIn(Mips::T9);
173 MBB.addLiveIn(Mips::T9);
176 // lui $v0, %hi(%neg(%gp_rel(fname)))
177 // addu $v1, $v0, $t9
178 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
179 const GlobalValue *FName = MF.getFunction();
180 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
181 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
182 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
183 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
184 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
190 // For O32 ABI, the following instruction sequence is emitted to initialize
191 // the global base register:
193 // 0. lui $2, %hi(_gp_disp)
194 // 1. addiu $2, $2, %lo(_gp_disp)
195 // 2. addu $globalbasereg, $2, $t9
197 // We emit only the last instruction here.
199 // GNU linker requires that the first two instructions appear at the beginning
200 // of a function and no instructions be inserted before or between them.
201 // The two instructions are emitted during lowering to MC layer in order to
202 // avoid any reordering.
204 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
205 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
207 MF.getRegInfo().addLiveIn(Mips::V0);
208 MBB.addLiveIn(Mips::V0);
209 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
210 .addReg(Mips::V0).addReg(Mips::T9);
213 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
214 initGlobalBaseReg(MF);
216 MachineRegisterInfo *MRI = &MF.getRegInfo();
218 for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
220 for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
221 if (I->getOpcode() == Mips::RDDSP)
222 addDSPCtrlRegOperands(false, *I, MF);
223 else if (I->getOpcode() == Mips::WRDSP)
224 addDSPCtrlRegOperands(true, *I, MF);
226 replaceUsesWithZeroReg(MRI, *I);
230 SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
231 SDValue CmpLHS, SDLoc DL,
232 SDNode *Node) const {
233 unsigned Opc = InFlag.getOpcode(); (void)Opc;
235 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
236 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
237 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
239 unsigned SLTuOp = Mips::SLTu, ADDuOp = Mips::ADDu;
240 if (Subtarget->isGP64bit()) {
241 SLTuOp = Mips::SLTu64;
242 ADDuOp = Mips::DADDu;
245 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
246 SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
247 EVT VT = LHS.getValueType();
249 SDNode *Carry = CurDAG->getMachineNode(SLTuOp, DL, VT, Ops);
251 if (Subtarget->isGP64bit()) {
252 // On 64-bit targets, sltu produces an i64 but our backend currently says
253 // that SLTu64 produces an i32. We need to fix this in the long run but for
254 // now, just make the DAG type-correct by asserting the upper bits are zero.
255 Carry = CurDAG->getMachineNode(Mips::SUBREG_TO_REG, DL, VT,
256 CurDAG->getTargetConstant(0, VT),
258 CurDAG->getTargetConstant(Mips::sub_32, VT));
261 // Generate a second addition only if we know that RHS is not a
262 // constant-zero node.
263 SDNode *AddCarry = Carry;
264 ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);
265 if (!C || C->getZExtValue())
266 AddCarry = CurDAG->getMachineNode(ADDuOp, DL, VT, SDValue(Carry, 0), RHS);
268 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
269 SDValue(AddCarry, 0));
273 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
274 SDValue &Offset) const {
275 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
276 EVT ValTy = Addr.getValueType();
278 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
279 Offset = CurDAG->getTargetConstant(0, ValTy);
285 /// Match frameindex+offset and frameindex|offset
286 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base,
288 unsigned OffsetBits) const {
289 if (CurDAG->isBaseWithConstantOffset(Addr)) {
290 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
291 if (isIntN(OffsetBits, CN->getSExtValue())) {
292 EVT ValTy = Addr.getValueType();
294 // If the first operand is a FI, get the TargetFI Node
295 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
296 (Addr.getOperand(0)))
297 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
299 Base = Addr.getOperand(0);
301 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
308 /// ComplexPattern used on MipsInstrInfo
309 /// Used on Mips Load/Store instructions
310 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
311 SDValue &Offset) const {
312 // if Address is FI, get the TargetFrameIndex.
313 if (selectAddrFrameIndex(Addr, Base, Offset))
316 // on PIC code Load GA
317 if (Addr.getOpcode() == MipsISD::Wrapper) {
318 Base = Addr.getOperand(0);
319 Offset = Addr.getOperand(1);
323 if (TM.getRelocationModel() != Reloc::PIC_) {
324 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
325 Addr.getOpcode() == ISD::TargetGlobalAddress))
329 // Addresses of the form FI+const or FI|const
330 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
333 // Operand is a result from an ADD.
334 if (Addr.getOpcode() == ISD::ADD) {
335 // When loading from constant pools, load the lower address part in
336 // the instruction itself. Example, instead of:
337 // lui $2, %hi($CPI1_0)
338 // addiu $2, $2, %lo($CPI1_0)
341 // lui $2, %hi($CPI1_0)
342 // lwc1 $f0, %lo($CPI1_0)($2)
343 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
344 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
345 SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
346 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
347 isa<JumpTableSDNode>(Opnd0)) {
348 Base = Addr.getOperand(0);
358 /// ComplexPattern used on MipsInstrInfo
359 /// Used on Mips Load/Store instructions
360 bool MipsSEDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base,
361 SDValue &Offset) const {
362 // Operand is a result from an ADD.
363 if (Addr.getOpcode() == ISD::ADD) {
364 Base = Addr.getOperand(0);
365 Offset = Addr.getOperand(1);
372 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
373 SDValue &Offset) const {
375 Offset = CurDAG->getTargetConstant(0, Addr.getValueType());
379 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
380 SDValue &Offset) const {
381 return selectAddrRegImm(Addr, Base, Offset) ||
382 selectAddrDefault(Addr, Base, Offset);
385 bool MipsSEDAGToDAGISel::selectAddrRegImm10(SDValue Addr, SDValue &Base,
386 SDValue &Offset) const {
387 if (selectAddrFrameIndex(Addr, Base, Offset))
390 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
396 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
397 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
398 SDValue &Offset) const {
399 if (selectAddrFrameIndex(Addr, Base, Offset))
402 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
408 bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
409 SDValue &Offset) const {
410 return selectAddrRegImm12(Addr, Base, Offset) ||
411 selectAddrDefault(Addr, Base, Offset);
414 bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
415 SDValue &Offset) const {
416 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 7)) {
417 if (isa<FrameIndexSDNode>(Base))
420 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Offset)) {
421 unsigned CnstOff = CN->getZExtValue();
422 return (CnstOff == (CnstOff & 0x3c));
428 // For all other cases where "lw" would be selected, don't select "lw16"
429 // because it would result in additional instructions to prepare operands.
430 if (selectAddrRegImm(Addr, Base, Offset))
433 return selectAddrDefault(Addr, Base, Offset);
436 bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
437 SDValue &Offset) const {
438 if (selectAddrRegImm10(Addr, Base, Offset))
441 if (selectAddrDefault(Addr, Base, Offset))
447 // Select constant vector splats.
449 // Returns true and sets Imm if:
451 // * N is a ISD::BUILD_VECTOR representing a constant splat
452 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
453 if (!Subtarget->hasMSA())
456 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
461 APInt SplatValue, SplatUndef;
462 unsigned SplatBitSize;
465 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
467 !Subtarget->isLittle()))
475 // Select constant vector splats.
477 // In addition to the requirements of selectVSplat(), this function returns
478 // true and sets Imm if:
479 // * The splat value is the same width as the elements of the vector
480 // * The splat value fits in an integer with the specified signed-ness and
483 // This function looks through ISD::BITCAST nodes.
484 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
485 // sometimes a shuffle in big-endian mode.
487 // It's worth noting that this function is not used as part of the selection
488 // of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
489 // instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
490 // MipsSEDAGToDAGISel::selectNode.
491 bool MipsSEDAGToDAGISel::
492 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
493 unsigned ImmBitSize) const {
495 EVT EltTy = N->getValueType(0).getVectorElementType();
497 if (N->getOpcode() == ISD::BITCAST)
498 N = N->getOperand(0);
500 if (selectVSplat (N.getNode(), ImmValue) &&
501 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
502 if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
503 (!Signed && ImmValue.isIntN(ImmBitSize))) {
504 Imm = CurDAG->getTargetConstant(ImmValue, EltTy);
512 // Select constant vector splats.
513 bool MipsSEDAGToDAGISel::
514 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
515 return selectVSplatCommon(N, Imm, false, 1);
518 bool MipsSEDAGToDAGISel::
519 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
520 return selectVSplatCommon(N, Imm, false, 2);
523 bool MipsSEDAGToDAGISel::
524 selectVSplatUimm3(SDValue N, SDValue &Imm) const {
525 return selectVSplatCommon(N, Imm, false, 3);
528 // Select constant vector splats.
529 bool MipsSEDAGToDAGISel::
530 selectVSplatUimm4(SDValue N, SDValue &Imm) const {
531 return selectVSplatCommon(N, Imm, false, 4);
534 // Select constant vector splats.
535 bool MipsSEDAGToDAGISel::
536 selectVSplatUimm5(SDValue N, SDValue &Imm) const {
537 return selectVSplatCommon(N, Imm, false, 5);
540 // Select constant vector splats.
541 bool MipsSEDAGToDAGISel::
542 selectVSplatUimm6(SDValue N, SDValue &Imm) const {
543 return selectVSplatCommon(N, Imm, false, 6);
546 // Select constant vector splats.
547 bool MipsSEDAGToDAGISel::
548 selectVSplatUimm8(SDValue N, SDValue &Imm) const {
549 return selectVSplatCommon(N, Imm, false, 8);
552 // Select constant vector splats.
553 bool MipsSEDAGToDAGISel::
554 selectVSplatSimm5(SDValue N, SDValue &Imm) const {
555 return selectVSplatCommon(N, Imm, true, 5);
558 // Select constant vector splats whose value is a power of 2.
560 // In addition to the requirements of selectVSplat(), this function returns
561 // true and sets Imm if:
562 // * The splat value is the same width as the elements of the vector
563 // * The splat value is a power of two.
565 // This function looks through ISD::BITCAST nodes.
566 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
567 // sometimes a shuffle in big-endian mode.
568 bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
570 EVT EltTy = N->getValueType(0).getVectorElementType();
572 if (N->getOpcode() == ISD::BITCAST)
573 N = N->getOperand(0);
575 if (selectVSplat (N.getNode(), ImmValue) &&
576 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
577 int32_t Log2 = ImmValue.exactLogBase2();
580 Imm = CurDAG->getTargetConstant(Log2, EltTy);
588 // Select constant vector splats whose value only has a consecutive sequence
589 // of left-most bits set (e.g. 0b11...1100...00).
591 // In addition to the requirements of selectVSplat(), this function returns
592 // true and sets Imm if:
593 // * The splat value is the same width as the elements of the vector
594 // * The splat value is a consecutive sequence of left-most bits.
596 // This function looks through ISD::BITCAST nodes.
597 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
598 // sometimes a shuffle in big-endian mode.
599 bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
601 EVT EltTy = N->getValueType(0).getVectorElementType();
603 if (N->getOpcode() == ISD::BITCAST)
604 N = N->getOperand(0);
606 if (selectVSplat(N.getNode(), ImmValue) &&
607 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
608 // Extract the run of set bits starting with bit zero from the bitwise
609 // inverse of ImmValue, and test that the inverse of this is the same
610 // as the original value.
611 if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
613 Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
621 // Select constant vector splats whose value only has a consecutive sequence
622 // of right-most bits set (e.g. 0b00...0011...11).
624 // In addition to the requirements of selectVSplat(), this function returns
625 // true and sets Imm if:
626 // * The splat value is the same width as the elements of the vector
627 // * The splat value is a consecutive sequence of right-most bits.
629 // This function looks through ISD::BITCAST nodes.
630 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
631 // sometimes a shuffle in big-endian mode.
632 bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
634 EVT EltTy = N->getValueType(0).getVectorElementType();
636 if (N->getOpcode() == ISD::BITCAST)
637 N = N->getOperand(0);
639 if (selectVSplat(N.getNode(), ImmValue) &&
640 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
641 // Extract the run of set bits starting with bit zero, and test that the
642 // result is the same as the original value
643 if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
644 Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
652 bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
653 SDValue &Imm) const {
655 EVT EltTy = N->getValueType(0).getVectorElementType();
657 if (N->getOpcode() == ISD::BITCAST)
658 N = N->getOperand(0);
660 if (selectVSplat(N.getNode(), ImmValue) &&
661 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
662 int32_t Log2 = (~ImmValue).exactLogBase2();
665 Imm = CurDAG->getTargetConstant(Log2, EltTy);
673 std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
674 unsigned Opcode = Node->getOpcode();
678 // Instruction Selection not handled by the auto-generated
679 // tablegen selection should be handled here.
687 SDValue InFlag = Node->getOperand(2);
688 unsigned Opc = Subtarget->isGP64bit() ? Mips::DSUBu : Mips::SUBu;
689 Result = selectAddESubE(Opc, InFlag, InFlag.getOperand(0), DL, Node);
690 return std::make_pair(true, Result);
694 if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
696 SDValue InFlag = Node->getOperand(2);
697 unsigned Opc = Subtarget->isGP64bit() ? Mips::DADDu : Mips::ADDu;
698 Result = selectAddESubE(Opc, InFlag, InFlag.getValue(0), DL, Node);
699 return std::make_pair(true, Result);
702 case ISD::ConstantFP: {
703 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
704 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
705 if (Subtarget->isGP64bit()) {
706 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
707 Mips::ZERO_64, MVT::i64);
708 Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
709 } else if (Subtarget->isFP64bit()) {
710 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
711 Mips::ZERO, MVT::i32);
712 Result = CurDAG->getMachineNode(Mips::BuildPairF64_64, DL, MVT::f64,
715 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
716 Mips::ZERO, MVT::i32);
717 Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
721 return std::make_pair(true, Result);
726 case ISD::Constant: {
727 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
728 unsigned Size = CN->getValueSizeInBits(0);
733 MipsAnalyzeImmediate AnalyzeImm;
734 int64_t Imm = CN->getSExtValue();
736 const MipsAnalyzeImmediate::InstSeq &Seq =
737 AnalyzeImm.Analyze(Imm, Size, false);
739 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
742 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
745 // The first instruction can be a LUi which is different from other
746 // instructions (ADDiu, ORI and SLL) in that it does not have a register
748 if (Inst->Opc == Mips::LUi64)
749 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
752 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
753 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
756 // The remaining instructions in the sequence are handled here.
757 for (++Inst; Inst != Seq.end(); ++Inst) {
758 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
760 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
761 SDValue(RegOpnd, 0), ImmOpnd);
764 return std::make_pair(true, RegOpnd);
767 case ISD::INTRINSIC_W_CHAIN: {
768 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
772 case Intrinsic::mips_cfcmsa: {
773 SDValue ChainIn = Node->getOperand(0);
774 SDValue RegIdx = Node->getOperand(2);
775 SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
776 getMSACtrlReg(RegIdx), MVT::i32);
777 return std::make_pair(true, Reg.getNode());
783 case ISD::INTRINSIC_WO_CHAIN: {
784 switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
788 case Intrinsic::mips_move_v:
789 // Like an assignment but will always produce a move.v even if
791 return std::make_pair(true,
792 CurDAG->getMachineNode(Mips::MOVE_V, DL,
793 Node->getValueType(0),
794 Node->getOperand(1)));
799 case ISD::INTRINSIC_VOID: {
800 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
804 case Intrinsic::mips_ctcmsa: {
805 SDValue ChainIn = Node->getOperand(0);
806 SDValue RegIdx = Node->getOperand(2);
807 SDValue Value = Node->getOperand(3);
808 SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
809 getMSACtrlReg(RegIdx), Value);
810 return std::make_pair(true, ChainOut.getNode());
816 case MipsISD::ThreadPointer: {
817 EVT PtrVT = getTargetLowering()->getPointerTy();
818 unsigned RdhwrOpc, DestReg;
820 if (PtrVT == MVT::i32) {
821 RdhwrOpc = Mips::RDHWR;
824 RdhwrOpc = Mips::RDHWR64;
825 DestReg = Mips::V1_64;
829 CurDAG->getMachineNode(RdhwrOpc, SDLoc(Node),
830 Node->getValueType(0),
831 CurDAG->getRegister(Mips::HWR29, MVT::i32));
832 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
834 SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
835 ReplaceUses(SDValue(Node, 0), ResNode);
836 return std::make_pair(true, ResNode.getNode());
839 case ISD::BUILD_VECTOR: {
840 // Select appropriate ldi.[bhwd] instructions for constant splats of
841 // 128-bit when MSA is enabled. Fixup any register class mismatches that
842 // occur as a result.
844 // This allows the compiler to use a wider range of immediates than would
845 // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
846 // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
847 // 0x01010101 } without using a constant pool. This would be sub-optimal
848 // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
849 // same set/ of registers. Similarly, ldi.h isn't capable of producing {
850 // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
852 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
853 APInt SplatValue, SplatUndef;
854 unsigned SplatBitSize;
857 EVT ResVecTy = BVN->getValueType(0);
860 if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
861 return std::make_pair(false, nullptr);
863 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
865 !Subtarget->isLittle()))
866 return std::make_pair(false, nullptr);
868 switch (SplatBitSize) {
870 return std::make_pair(false, nullptr);
873 ViaVecTy = MVT::v16i8;
877 ViaVecTy = MVT::v8i16;
881 ViaVecTy = MVT::v4i32;
885 ViaVecTy = MVT::v2i64;
889 if (!SplatValue.isSignedIntN(10))
890 return std::make_pair(false, nullptr);
892 SDValue Imm = CurDAG->getTargetConstant(SplatValue,
893 ViaVecTy.getVectorElementType());
895 SDNode *Res = CurDAG->getMachineNode(LdiOp, SDLoc(Node), ViaVecTy, Imm);
897 if (ResVecTy != ViaVecTy) {
898 // If LdiOp is writing to a different register class to ResVecTy, then
899 // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
900 // since the source and destination register sets contain the same
902 const TargetLowering *TLI = getTargetLowering();
903 MVT ResVecTySimple = ResVecTy.getSimpleVT();
904 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
905 Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, SDLoc(Node),
906 ResVecTy, SDValue(Res, 0),
907 CurDAG->getTargetConstant(RC->getID(),
911 return std::make_pair(true, Res);
916 return std::make_pair(false, nullptr);
919 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
920 return new MipsSEDAGToDAGISel(TM);