1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
15 #include "MipsSEISelDAGToDAG.h"
16 #include "MCTargetDesc/MipsBaseInfo.h"
18 #include "MipsAnalyzeImmediate.h"
19 #include "MipsMachineFunction.h"
20 #include "MipsRegisterInfo.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 #include "llvm/IR/CFG.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/IR/Instructions.h"
30 #include "llvm/IR/Intrinsics.h"
31 #include "llvm/IR/Type.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
38 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
39 if (Subtarget.inMips16Mode())
41 return MipsDAGToDAGISel::runOnMachineFunction(MF);
44 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
45 MachineFunction &MF) {
46 MachineInstrBuilder MIB(MF, &MI);
47 unsigned Mask = MI.getOperand(1).getImm();
48 unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit;
51 MIB.addReg(Mips::DSPPos, Flag);
54 MIB.addReg(Mips::DSPSCount, Flag);
57 MIB.addReg(Mips::DSPCarry, Flag);
60 MIB.addReg(Mips::DSPOutFlag, Flag);
63 MIB.addReg(Mips::DSPCCond, Flag);
66 MIB.addReg(Mips::DSPEFI, Flag);
69 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
70 switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
72 llvm_unreachable("Could not map int to register");
73 case 0: return Mips::MSAIR;
74 case 1: return Mips::MSACSR;
75 case 2: return Mips::MSAAccess;
76 case 3: return Mips::MSASave;
77 case 4: return Mips::MSAModify;
78 case 5: return Mips::MSARequest;
79 case 6: return Mips::MSAMap;
80 case 7: return Mips::MSAUnmap;
84 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
85 const MachineInstr& MI) {
86 unsigned DstReg = 0, ZeroReg = 0;
88 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
89 if ((MI.getOpcode() == Mips::ADDiu) &&
90 (MI.getOperand(1).getReg() == Mips::ZERO) &&
91 (MI.getOperand(2).getImm() == 0)) {
92 DstReg = MI.getOperand(0).getReg();
94 } else if ((MI.getOpcode() == Mips::DADDiu) &&
95 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
96 (MI.getOperand(2).getImm() == 0)) {
97 DstReg = MI.getOperand(0).getReg();
98 ZeroReg = Mips::ZERO_64;
104 // Replace uses with ZeroReg.
105 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
106 E = MRI->use_end(); U != E;) {
107 MachineOperand &MO = U.getOperand();
108 unsigned OpNo = U.getOperandNo();
109 MachineInstr *MI = MO.getParent();
112 // Do not replace if it is a phi's operand or is tied to def operand.
113 if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
122 void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
123 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
125 if (!MipsFI->globalBaseRegSet())
128 MachineBasicBlock &MBB = MF.front();
129 MachineBasicBlock::iterator I = MBB.begin();
130 MachineRegisterInfo &RegInfo = MF.getRegInfo();
131 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
132 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
133 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
134 const TargetRegisterClass *RC;
136 if (Subtarget.isABI_N64())
137 RC = (const TargetRegisterClass*)&Mips::GPR64RegClass;
139 RC = (const TargetRegisterClass*)&Mips::GPR32RegClass;
141 V0 = RegInfo.createVirtualRegister(RC);
142 V1 = RegInfo.createVirtualRegister(RC);
144 if (Subtarget.isABI_N64()) {
145 MF.getRegInfo().addLiveIn(Mips::T9_64);
146 MBB.addLiveIn(Mips::T9_64);
148 // lui $v0, %hi(%neg(%gp_rel(fname)))
149 // daddu $v1, $v0, $t9
150 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
151 const GlobalValue *FName = MF.getFunction();
152 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
153 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
154 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
155 .addReg(Mips::T9_64);
156 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
157 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
161 if (MF.getTarget().getRelocationModel() == Reloc::Static) {
162 // Set global register to __gnu_local_gp.
164 // lui $v0, %hi(__gnu_local_gp)
165 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
166 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
167 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
168 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
169 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
173 MF.getRegInfo().addLiveIn(Mips::T9);
174 MBB.addLiveIn(Mips::T9);
176 if (Subtarget.isABI_N32()) {
177 // lui $v0, %hi(%neg(%gp_rel(fname)))
178 // addu $v1, $v0, $t9
179 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
180 const GlobalValue *FName = MF.getFunction();
181 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
182 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
183 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
184 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
185 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
189 assert(Subtarget.isABI_O32());
191 // For O32 ABI, the following instruction sequence is emitted to initialize
192 // the global base register:
194 // 0. lui $2, %hi(_gp_disp)
195 // 1. addiu $2, $2, %lo(_gp_disp)
196 // 2. addu $globalbasereg, $2, $t9
198 // We emit only the last instruction here.
200 // GNU linker requires that the first two instructions appear at the beginning
201 // of a function and no instructions be inserted before or between them.
202 // The two instructions are emitted during lowering to MC layer in order to
203 // avoid any reordering.
205 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
206 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
208 MF.getRegInfo().addLiveIn(Mips::V0);
209 MBB.addLiveIn(Mips::V0);
210 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
211 .addReg(Mips::V0).addReg(Mips::T9);
214 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
215 initGlobalBaseReg(MF);
217 MachineRegisterInfo *MRI = &MF.getRegInfo();
219 for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
221 for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
222 if (I->getOpcode() == Mips::RDDSP)
223 addDSPCtrlRegOperands(false, *I, MF);
224 else if (I->getOpcode() == Mips::WRDSP)
225 addDSPCtrlRegOperands(true, *I, MF);
227 replaceUsesWithZeroReg(MRI, *I);
231 SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
232 SDValue CmpLHS, SDLoc DL,
233 SDNode *Node) const {
234 unsigned Opc = InFlag.getOpcode(); (void)Opc;
236 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
237 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
238 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
240 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
241 SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
242 EVT VT = LHS.getValueType();
244 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops);
245 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,
246 SDValue(Carry, 0), RHS);
247 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
248 SDValue(AddCarry, 0));
252 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
253 SDValue &Offset) const {
254 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
255 EVT ValTy = Addr.getValueType();
257 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
258 Offset = CurDAG->getTargetConstant(0, ValTy);
264 /// Match frameindex+offset and frameindex|offset
265 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base,
267 unsigned OffsetBits) const {
268 if (CurDAG->isBaseWithConstantOffset(Addr)) {
269 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
270 if (isIntN(OffsetBits, CN->getSExtValue())) {
271 EVT ValTy = Addr.getValueType();
273 // If the first operand is a FI, get the TargetFI Node
274 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
275 (Addr.getOperand(0)))
276 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
278 Base = Addr.getOperand(0);
280 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
287 /// ComplexPattern used on MipsInstrInfo
288 /// Used on Mips Load/Store instructions
289 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
290 SDValue &Offset) const {
291 // if Address is FI, get the TargetFrameIndex.
292 if (selectAddrFrameIndex(Addr, Base, Offset))
295 // on PIC code Load GA
296 if (Addr.getOpcode() == MipsISD::Wrapper) {
297 Base = Addr.getOperand(0);
298 Offset = Addr.getOperand(1);
302 if (TM.getRelocationModel() != Reloc::PIC_) {
303 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
304 Addr.getOpcode() == ISD::TargetGlobalAddress))
308 // Addresses of the form FI+const or FI|const
309 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
312 // Operand is a result from an ADD.
313 if (Addr.getOpcode() == ISD::ADD) {
314 // When loading from constant pools, load the lower address part in
315 // the instruction itself. Example, instead of:
316 // lui $2, %hi($CPI1_0)
317 // addiu $2, $2, %lo($CPI1_0)
320 // lui $2, %hi($CPI1_0)
321 // lwc1 $f0, %lo($CPI1_0)($2)
322 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
323 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
324 SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
325 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
326 isa<JumpTableSDNode>(Opnd0)) {
327 Base = Addr.getOperand(0);
337 /// ComplexPattern used on MipsInstrInfo
338 /// Used on Mips Load/Store instructions
339 bool MipsSEDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base,
340 SDValue &Offset) const {
341 // Operand is a result from an ADD.
342 if (Addr.getOpcode() == ISD::ADD) {
343 Base = Addr.getOperand(0);
344 Offset = Addr.getOperand(1);
351 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
352 SDValue &Offset) const {
354 Offset = CurDAG->getTargetConstant(0, Addr.getValueType());
358 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
359 SDValue &Offset) const {
360 return selectAddrRegImm(Addr, Base, Offset) ||
361 selectAddrDefault(Addr, Base, Offset);
364 bool MipsSEDAGToDAGISel::selectAddrRegImm10(SDValue Addr, SDValue &Base,
365 SDValue &Offset) const {
366 if (selectAddrFrameIndex(Addr, Base, Offset))
369 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
375 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
376 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
377 SDValue &Offset) const {
378 if (selectAddrFrameIndex(Addr, Base, Offset))
381 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
387 bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
388 SDValue &Offset) const {
389 return selectAddrRegImm12(Addr, Base, Offset) ||
390 selectAddrDefault(Addr, Base, Offset);
393 bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
394 SDValue &Offset) const {
395 if (selectAddrRegImm10(Addr, Base, Offset))
398 if (selectAddrDefault(Addr, Base, Offset))
404 // Select constant vector splats.
406 // Returns true and sets Imm if:
408 // * N is a ISD::BUILD_VECTOR representing a constant splat
409 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
410 if (!Subtarget.hasMSA())
413 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
418 APInt SplatValue, SplatUndef;
419 unsigned SplatBitSize;
422 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
424 !Subtarget.isLittle()))
432 // Select constant vector splats.
434 // In addition to the requirements of selectVSplat(), this function returns
435 // true and sets Imm if:
436 // * The splat value is the same width as the elements of the vector
437 // * The splat value fits in an integer with the specified signed-ness and
440 // This function looks through ISD::BITCAST nodes.
441 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
442 // sometimes a shuffle in big-endian mode.
444 // It's worth noting that this function is not used as part of the selection
445 // of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
446 // instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
447 // MipsSEDAGToDAGISel::selectNode.
448 bool MipsSEDAGToDAGISel::
449 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
450 unsigned ImmBitSize) const {
452 EVT EltTy = N->getValueType(0).getVectorElementType();
454 if (N->getOpcode() == ISD::BITCAST)
455 N = N->getOperand(0);
457 if (selectVSplat (N.getNode(), ImmValue) &&
458 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
459 if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
460 (!Signed && ImmValue.isIntN(ImmBitSize))) {
461 Imm = CurDAG->getTargetConstant(ImmValue, EltTy);
469 // Select constant vector splats.
470 bool MipsSEDAGToDAGISel::
471 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
472 return selectVSplatCommon(N, Imm, false, 1);
475 bool MipsSEDAGToDAGISel::
476 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
477 return selectVSplatCommon(N, Imm, false, 2);
480 bool MipsSEDAGToDAGISel::
481 selectVSplatUimm3(SDValue N, SDValue &Imm) const {
482 return selectVSplatCommon(N, Imm, false, 3);
485 // Select constant vector splats.
486 bool MipsSEDAGToDAGISel::
487 selectVSplatUimm4(SDValue N, SDValue &Imm) const {
488 return selectVSplatCommon(N, Imm, false, 4);
491 // Select constant vector splats.
492 bool MipsSEDAGToDAGISel::
493 selectVSplatUimm5(SDValue N, SDValue &Imm) const {
494 return selectVSplatCommon(N, Imm, false, 5);
497 // Select constant vector splats.
498 bool MipsSEDAGToDAGISel::
499 selectVSplatUimm6(SDValue N, SDValue &Imm) const {
500 return selectVSplatCommon(N, Imm, false, 6);
503 // Select constant vector splats.
504 bool MipsSEDAGToDAGISel::
505 selectVSplatUimm8(SDValue N, SDValue &Imm) const {
506 return selectVSplatCommon(N, Imm, false, 8);
509 // Select constant vector splats.
510 bool MipsSEDAGToDAGISel::
511 selectVSplatSimm5(SDValue N, SDValue &Imm) const {
512 return selectVSplatCommon(N, Imm, true, 5);
515 // Select constant vector splats whose value is a power of 2.
517 // In addition to the requirements of selectVSplat(), this function returns
518 // true and sets Imm if:
519 // * The splat value is the same width as the elements of the vector
520 // * The splat value is a power of two.
522 // This function looks through ISD::BITCAST nodes.
523 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
524 // sometimes a shuffle in big-endian mode.
525 bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
527 EVT EltTy = N->getValueType(0).getVectorElementType();
529 if (N->getOpcode() == ISD::BITCAST)
530 N = N->getOperand(0);
532 if (selectVSplat (N.getNode(), ImmValue) &&
533 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
534 int32_t Log2 = ImmValue.exactLogBase2();
537 Imm = CurDAG->getTargetConstant(Log2, EltTy);
545 // Select constant vector splats whose value only has a consecutive sequence
546 // of left-most bits set (e.g. 0b11...1100...00).
548 // In addition to the requirements of selectVSplat(), this function returns
549 // true and sets Imm if:
550 // * The splat value is the same width as the elements of the vector
551 // * The splat value is a consecutive sequence of left-most bits.
553 // This function looks through ISD::BITCAST nodes.
554 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
555 // sometimes a shuffle in big-endian mode.
556 bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
558 EVT EltTy = N->getValueType(0).getVectorElementType();
560 if (N->getOpcode() == ISD::BITCAST)
561 N = N->getOperand(0);
563 if (selectVSplat(N.getNode(), ImmValue) &&
564 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
565 // Extract the run of set bits starting with bit zero from the bitwise
566 // inverse of ImmValue, and test that the inverse of this is the same
567 // as the original value.
568 if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
570 Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
578 // Select constant vector splats whose value only has a consecutive sequence
579 // of right-most bits set (e.g. 0b00...0011...11).
581 // In addition to the requirements of selectVSplat(), this function returns
582 // true and sets Imm if:
583 // * The splat value is the same width as the elements of the vector
584 // * The splat value is a consecutive sequence of right-most bits.
586 // This function looks through ISD::BITCAST nodes.
587 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
588 // sometimes a shuffle in big-endian mode.
589 bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
591 EVT EltTy = N->getValueType(0).getVectorElementType();
593 if (N->getOpcode() == ISD::BITCAST)
594 N = N->getOperand(0);
596 if (selectVSplat(N.getNode(), ImmValue) &&
597 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
598 // Extract the run of set bits starting with bit zero, and test that the
599 // result is the same as the original value
600 if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
601 Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
609 bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
610 SDValue &Imm) const {
612 EVT EltTy = N->getValueType(0).getVectorElementType();
614 if (N->getOpcode() == ISD::BITCAST)
615 N = N->getOperand(0);
617 if (selectVSplat(N.getNode(), ImmValue) &&
618 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
619 int32_t Log2 = (~ImmValue).exactLogBase2();
622 Imm = CurDAG->getTargetConstant(Log2, EltTy);
630 std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
631 unsigned Opcode = Node->getOpcode();
635 // Instruction Selection not handled by the auto-generated
636 // tablegen selection should be handled here.
644 SDValue InFlag = Node->getOperand(2);
645 Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node);
646 return std::make_pair(true, Result);
650 if (Subtarget.hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
652 SDValue InFlag = Node->getOperand(2);
653 Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);
654 return std::make_pair(true, Result);
657 case ISD::ConstantFP: {
658 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
659 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
660 if (Subtarget.hasMips64()) {
661 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
662 Mips::ZERO_64, MVT::i64);
663 Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
664 } else if (Subtarget.isFP64bit()) {
665 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
666 Mips::ZERO, MVT::i32);
667 Result = CurDAG->getMachineNode(Mips::BuildPairF64_64, DL, MVT::f64,
670 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
671 Mips::ZERO, MVT::i32);
672 Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
676 return std::make_pair(true, Result);
681 case ISD::Constant: {
682 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
683 unsigned Size = CN->getValueSizeInBits(0);
688 MipsAnalyzeImmediate AnalyzeImm;
689 int64_t Imm = CN->getSExtValue();
691 const MipsAnalyzeImmediate::InstSeq &Seq =
692 AnalyzeImm.Analyze(Imm, Size, false);
694 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
697 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
700 // The first instruction can be a LUi which is different from other
701 // instructions (ADDiu, ORI and SLL) in that it does not have a register
703 if (Inst->Opc == Mips::LUi64)
704 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
707 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
708 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
711 // The remaining instructions in the sequence are handled here.
712 for (++Inst; Inst != Seq.end(); ++Inst) {
713 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
715 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
716 SDValue(RegOpnd, 0), ImmOpnd);
719 return std::make_pair(true, RegOpnd);
722 case ISD::INTRINSIC_W_CHAIN: {
723 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
727 case Intrinsic::mips_cfcmsa: {
728 SDValue ChainIn = Node->getOperand(0);
729 SDValue RegIdx = Node->getOperand(2);
730 SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
731 getMSACtrlReg(RegIdx), MVT::i32);
732 return std::make_pair(true, Reg.getNode());
738 case ISD::INTRINSIC_WO_CHAIN: {
739 switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
743 case Intrinsic::mips_move_v:
744 // Like an assignment but will always produce a move.v even if
746 return std::make_pair(true,
747 CurDAG->getMachineNode(Mips::MOVE_V, DL,
748 Node->getValueType(0),
749 Node->getOperand(1)));
754 case ISD::INTRINSIC_VOID: {
755 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
759 case Intrinsic::mips_ctcmsa: {
760 SDValue ChainIn = Node->getOperand(0);
761 SDValue RegIdx = Node->getOperand(2);
762 SDValue Value = Node->getOperand(3);
763 SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
764 getMSACtrlReg(RegIdx), Value);
765 return std::make_pair(true, ChainOut.getNode());
771 case MipsISD::ThreadPointer: {
772 EVT PtrVT = getTargetLowering()->getPointerTy();
773 unsigned RdhwrOpc, DestReg;
775 if (PtrVT == MVT::i32) {
776 RdhwrOpc = Mips::RDHWR;
779 RdhwrOpc = Mips::RDHWR64;
780 DestReg = Mips::V1_64;
784 CurDAG->getMachineNode(RdhwrOpc, SDLoc(Node),
785 Node->getValueType(0),
786 CurDAG->getRegister(Mips::HWR29, MVT::i32));
787 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
789 SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
790 ReplaceUses(SDValue(Node, 0), ResNode);
791 return std::make_pair(true, ResNode.getNode());
794 case ISD::BUILD_VECTOR: {
795 // Select appropriate ldi.[bhwd] instructions for constant splats of
796 // 128-bit when MSA is enabled. Fixup any register class mismatches that
797 // occur as a result.
799 // This allows the compiler to use a wider range of immediates than would
800 // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
801 // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
802 // 0x01010101 } without using a constant pool. This would be sub-optimal
803 // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
804 // same set/ of registers. Similarly, ldi.h isn't capable of producing {
805 // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
807 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
808 APInt SplatValue, SplatUndef;
809 unsigned SplatBitSize;
812 EVT ResVecTy = BVN->getValueType(0);
815 if (!Subtarget.hasMSA() || !BVN->getValueType(0).is128BitVector())
816 return std::make_pair(false, (SDNode*)NULL);
818 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
820 !Subtarget.isLittle()))
821 return std::make_pair(false, (SDNode*)NULL);
823 switch (SplatBitSize) {
825 return std::make_pair(false, (SDNode*)NULL);
828 ViaVecTy = MVT::v16i8;
832 ViaVecTy = MVT::v8i16;
836 ViaVecTy = MVT::v4i32;
840 ViaVecTy = MVT::v2i64;
844 if (!SplatValue.isSignedIntN(10))
845 return std::make_pair(false, (SDNode*)NULL);
847 SDValue Imm = CurDAG->getTargetConstant(SplatValue,
848 ViaVecTy.getVectorElementType());
850 SDNode *Res = CurDAG->getMachineNode(LdiOp, SDLoc(Node), ViaVecTy, Imm);
852 if (ResVecTy != ViaVecTy) {
853 // If LdiOp is writing to a different register class to ResVecTy, then
854 // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
855 // since the source and destination register sets contain the same
857 const TargetLowering *TLI = getTargetLowering();
858 MVT ResVecTySimple = ResVecTy.getSimpleVT();
859 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
860 Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, SDLoc(Node),
861 ResVecTy, SDValue(Res, 0),
862 CurDAG->getTargetConstant(RC->getID(),
866 return std::make_pair(true, Res);
871 return std::make_pair(false, (SDNode*)NULL);
874 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
875 return new MipsSEDAGToDAGISel(TM);