1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
14 #include "MipsSEISelDAGToDAG.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "MipsAnalyzeImmediate.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsRegisterInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 #include "llvm/IR/CFG.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetMachine.h"
37 #define DEBUG_TYPE "mips-isel"
39 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
40 Subtarget = &TM.getSubtarget<MipsSubtarget>();
41 if (Subtarget->inMips16Mode())
43 return MipsDAGToDAGISel::runOnMachineFunction(MF);
46 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
47 MachineFunction &MF) {
48 MachineInstrBuilder MIB(MF, &MI);
49 unsigned Mask = MI.getOperand(1).getImm();
50 unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit;
53 MIB.addReg(Mips::DSPPos, Flag);
56 MIB.addReg(Mips::DSPSCount, Flag);
59 MIB.addReg(Mips::DSPCarry, Flag);
62 MIB.addReg(Mips::DSPOutFlag, Flag);
65 MIB.addReg(Mips::DSPCCond, Flag);
68 MIB.addReg(Mips::DSPEFI, Flag);
71 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
72 switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
74 llvm_unreachable("Could not map int to register");
75 case 0: return Mips::MSAIR;
76 case 1: return Mips::MSACSR;
77 case 2: return Mips::MSAAccess;
78 case 3: return Mips::MSASave;
79 case 4: return Mips::MSAModify;
80 case 5: return Mips::MSARequest;
81 case 6: return Mips::MSAMap;
82 case 7: return Mips::MSAUnmap;
86 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
87 const MachineInstr& MI) {
88 unsigned DstReg = 0, ZeroReg = 0;
90 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
91 if ((MI.getOpcode() == Mips::ADDiu) &&
92 (MI.getOperand(1).getReg() == Mips::ZERO) &&
93 (MI.getOperand(2).getImm() == 0)) {
94 DstReg = MI.getOperand(0).getReg();
96 } else if ((MI.getOpcode() == Mips::DADDiu) &&
97 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
98 (MI.getOperand(2).getImm() == 0)) {
99 DstReg = MI.getOperand(0).getReg();
100 ZeroReg = Mips::ZERO_64;
106 // Replace uses with ZeroReg.
107 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
108 E = MRI->use_end(); U != E;) {
109 MachineOperand &MO = *U;
110 unsigned OpNo = U.getOperandNo();
111 MachineInstr *MI = MO.getParent();
114 // Do not replace if it is a phi's operand or is tied to def operand.
115 if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
124 void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
125 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
127 if (!MipsFI->globalBaseRegSet())
130 MachineBasicBlock &MBB = MF.front();
131 MachineBasicBlock::iterator I = MBB.begin();
132 MachineRegisterInfo &RegInfo = MF.getRegInfo();
133 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
134 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
135 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
136 const TargetRegisterClass *RC;
138 if (Subtarget->isABI_N64())
139 RC = (const TargetRegisterClass*)&Mips::GPR64RegClass;
141 RC = (const TargetRegisterClass*)&Mips::GPR32RegClass;
143 V0 = RegInfo.createVirtualRegister(RC);
144 V1 = RegInfo.createVirtualRegister(RC);
146 if (Subtarget->isABI_N64()) {
147 MF.getRegInfo().addLiveIn(Mips::T9_64);
148 MBB.addLiveIn(Mips::T9_64);
150 // lui $v0, %hi(%neg(%gp_rel(fname)))
151 // daddu $v1, $v0, $t9
152 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
153 const GlobalValue *FName = MF.getFunction();
154 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
155 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
156 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
157 .addReg(Mips::T9_64);
158 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
159 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
163 if (MF.getTarget().getRelocationModel() == Reloc::Static) {
164 // Set global register to __gnu_local_gp.
166 // lui $v0, %hi(__gnu_local_gp)
167 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
168 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
169 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
170 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
171 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
175 MF.getRegInfo().addLiveIn(Mips::T9);
176 MBB.addLiveIn(Mips::T9);
178 if (Subtarget->isABI_N32()) {
179 // lui $v0, %hi(%neg(%gp_rel(fname)))
180 // addu $v1, $v0, $t9
181 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
182 const GlobalValue *FName = MF.getFunction();
183 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
184 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
185 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
186 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
187 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
191 assert(Subtarget->isABI_O32());
193 // For O32 ABI, the following instruction sequence is emitted to initialize
194 // the global base register:
196 // 0. lui $2, %hi(_gp_disp)
197 // 1. addiu $2, $2, %lo(_gp_disp)
198 // 2. addu $globalbasereg, $2, $t9
200 // We emit only the last instruction here.
202 // GNU linker requires that the first two instructions appear at the beginning
203 // of a function and no instructions be inserted before or between them.
204 // The two instructions are emitted during lowering to MC layer in order to
205 // avoid any reordering.
207 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
208 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
210 MF.getRegInfo().addLiveIn(Mips::V0);
211 MBB.addLiveIn(Mips::V0);
212 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
213 .addReg(Mips::V0).addReg(Mips::T9);
216 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
217 initGlobalBaseReg(MF);
219 MachineRegisterInfo *MRI = &MF.getRegInfo();
221 for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
223 for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
224 if (I->getOpcode() == Mips::RDDSP)
225 addDSPCtrlRegOperands(false, *I, MF);
226 else if (I->getOpcode() == Mips::WRDSP)
227 addDSPCtrlRegOperands(true, *I, MF);
229 replaceUsesWithZeroReg(MRI, *I);
233 SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
234 SDValue CmpLHS, SDLoc DL,
235 SDNode *Node) const {
236 unsigned Opc = InFlag.getOpcode(); (void)Opc;
238 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
239 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
240 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
242 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
243 SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
244 EVT VT = LHS.getValueType();
246 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops);
247 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,
248 SDValue(Carry, 0), RHS);
249 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
250 SDValue(AddCarry, 0));
254 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
255 SDValue &Offset) const {
256 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
257 EVT ValTy = Addr.getValueType();
259 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
260 Offset = CurDAG->getTargetConstant(0, ValTy);
266 /// Match frameindex+offset and frameindex|offset
267 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base,
269 unsigned OffsetBits) const {
270 if (CurDAG->isBaseWithConstantOffset(Addr)) {
271 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
272 if (isIntN(OffsetBits, CN->getSExtValue())) {
273 EVT ValTy = Addr.getValueType();
275 // If the first operand is a FI, get the TargetFI Node
276 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
277 (Addr.getOperand(0)))
278 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
280 Base = Addr.getOperand(0);
282 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
289 /// ComplexPattern used on MipsInstrInfo
290 /// Used on Mips Load/Store instructions
291 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
292 SDValue &Offset) const {
293 // if Address is FI, get the TargetFrameIndex.
294 if (selectAddrFrameIndex(Addr, Base, Offset))
297 // on PIC code Load GA
298 if (Addr.getOpcode() == MipsISD::Wrapper) {
299 Base = Addr.getOperand(0);
300 Offset = Addr.getOperand(1);
304 if (TM.getRelocationModel() != Reloc::PIC_) {
305 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
306 Addr.getOpcode() == ISD::TargetGlobalAddress))
310 // Addresses of the form FI+const or FI|const
311 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
314 // Operand is a result from an ADD.
315 if (Addr.getOpcode() == ISD::ADD) {
316 // When loading from constant pools, load the lower address part in
317 // the instruction itself. Example, instead of:
318 // lui $2, %hi($CPI1_0)
319 // addiu $2, $2, %lo($CPI1_0)
322 // lui $2, %hi($CPI1_0)
323 // lwc1 $f0, %lo($CPI1_0)($2)
324 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
325 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
326 SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
327 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
328 isa<JumpTableSDNode>(Opnd0)) {
329 Base = Addr.getOperand(0);
339 /// ComplexPattern used on MipsInstrInfo
340 /// Used on Mips Load/Store instructions
341 bool MipsSEDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base,
342 SDValue &Offset) const {
343 // Operand is a result from an ADD.
344 if (Addr.getOpcode() == ISD::ADD) {
345 Base = Addr.getOperand(0);
346 Offset = Addr.getOperand(1);
353 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
354 SDValue &Offset) const {
356 Offset = CurDAG->getTargetConstant(0, Addr.getValueType());
360 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
361 SDValue &Offset) const {
362 return selectAddrRegImm(Addr, Base, Offset) ||
363 selectAddrDefault(Addr, Base, Offset);
366 bool MipsSEDAGToDAGISel::selectAddrRegImm10(SDValue Addr, SDValue &Base,
367 SDValue &Offset) const {
368 if (selectAddrFrameIndex(Addr, Base, Offset))
371 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
377 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
378 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
379 SDValue &Offset) const {
380 if (selectAddrFrameIndex(Addr, Base, Offset))
383 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
389 bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
390 SDValue &Offset) const {
391 return selectAddrRegImm12(Addr, Base, Offset) ||
392 selectAddrDefault(Addr, Base, Offset);
395 bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
396 SDValue &Offset) const {
397 if (selectAddrRegImm10(Addr, Base, Offset))
400 if (selectAddrDefault(Addr, Base, Offset))
406 // Select constant vector splats.
408 // Returns true and sets Imm if:
410 // * N is a ISD::BUILD_VECTOR representing a constant splat
411 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
412 if (!Subtarget->hasMSA())
415 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
420 APInt SplatValue, SplatUndef;
421 unsigned SplatBitSize;
424 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
426 !Subtarget->isLittle()))
434 // Select constant vector splats.
436 // In addition to the requirements of selectVSplat(), this function returns
437 // true and sets Imm if:
438 // * The splat value is the same width as the elements of the vector
439 // * The splat value fits in an integer with the specified signed-ness and
442 // This function looks through ISD::BITCAST nodes.
443 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
444 // sometimes a shuffle in big-endian mode.
446 // It's worth noting that this function is not used as part of the selection
447 // of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
448 // instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
449 // MipsSEDAGToDAGISel::selectNode.
450 bool MipsSEDAGToDAGISel::
451 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
452 unsigned ImmBitSize) const {
454 EVT EltTy = N->getValueType(0).getVectorElementType();
456 if (N->getOpcode() == ISD::BITCAST)
457 N = N->getOperand(0);
459 if (selectVSplat (N.getNode(), ImmValue) &&
460 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
461 if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
462 (!Signed && ImmValue.isIntN(ImmBitSize))) {
463 Imm = CurDAG->getTargetConstant(ImmValue, EltTy);
471 // Select constant vector splats.
472 bool MipsSEDAGToDAGISel::
473 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
474 return selectVSplatCommon(N, Imm, false, 1);
477 bool MipsSEDAGToDAGISel::
478 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
479 return selectVSplatCommon(N, Imm, false, 2);
482 bool MipsSEDAGToDAGISel::
483 selectVSplatUimm3(SDValue N, SDValue &Imm) const {
484 return selectVSplatCommon(N, Imm, false, 3);
487 // Select constant vector splats.
488 bool MipsSEDAGToDAGISel::
489 selectVSplatUimm4(SDValue N, SDValue &Imm) const {
490 return selectVSplatCommon(N, Imm, false, 4);
493 // Select constant vector splats.
494 bool MipsSEDAGToDAGISel::
495 selectVSplatUimm5(SDValue N, SDValue &Imm) const {
496 return selectVSplatCommon(N, Imm, false, 5);
499 // Select constant vector splats.
500 bool MipsSEDAGToDAGISel::
501 selectVSplatUimm6(SDValue N, SDValue &Imm) const {
502 return selectVSplatCommon(N, Imm, false, 6);
505 // Select constant vector splats.
506 bool MipsSEDAGToDAGISel::
507 selectVSplatUimm8(SDValue N, SDValue &Imm) const {
508 return selectVSplatCommon(N, Imm, false, 8);
511 // Select constant vector splats.
512 bool MipsSEDAGToDAGISel::
513 selectVSplatSimm5(SDValue N, SDValue &Imm) const {
514 return selectVSplatCommon(N, Imm, true, 5);
517 // Select constant vector splats whose value is a power of 2.
519 // In addition to the requirements of selectVSplat(), this function returns
520 // true and sets Imm if:
521 // * The splat value is the same width as the elements of the vector
522 // * The splat value is a power of two.
524 // This function looks through ISD::BITCAST nodes.
525 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
526 // sometimes a shuffle in big-endian mode.
527 bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
529 EVT EltTy = N->getValueType(0).getVectorElementType();
531 if (N->getOpcode() == ISD::BITCAST)
532 N = N->getOperand(0);
534 if (selectVSplat (N.getNode(), ImmValue) &&
535 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
536 int32_t Log2 = ImmValue.exactLogBase2();
539 Imm = CurDAG->getTargetConstant(Log2, EltTy);
547 // Select constant vector splats whose value only has a consecutive sequence
548 // of left-most bits set (e.g. 0b11...1100...00).
550 // In addition to the requirements of selectVSplat(), this function returns
551 // true and sets Imm if:
552 // * The splat value is the same width as the elements of the vector
553 // * The splat value is a consecutive sequence of left-most bits.
555 // This function looks through ISD::BITCAST nodes.
556 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
557 // sometimes a shuffle in big-endian mode.
558 bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
560 EVT EltTy = N->getValueType(0).getVectorElementType();
562 if (N->getOpcode() == ISD::BITCAST)
563 N = N->getOperand(0);
565 if (selectVSplat(N.getNode(), ImmValue) &&
566 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
567 // Extract the run of set bits starting with bit zero from the bitwise
568 // inverse of ImmValue, and test that the inverse of this is the same
569 // as the original value.
570 if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
572 Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
580 // Select constant vector splats whose value only has a consecutive sequence
581 // of right-most bits set (e.g. 0b00...0011...11).
583 // In addition to the requirements of selectVSplat(), this function returns
584 // true and sets Imm if:
585 // * The splat value is the same width as the elements of the vector
586 // * The splat value is a consecutive sequence of right-most bits.
588 // This function looks through ISD::BITCAST nodes.
589 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
590 // sometimes a shuffle in big-endian mode.
591 bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
593 EVT EltTy = N->getValueType(0).getVectorElementType();
595 if (N->getOpcode() == ISD::BITCAST)
596 N = N->getOperand(0);
598 if (selectVSplat(N.getNode(), ImmValue) &&
599 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
600 // Extract the run of set bits starting with bit zero, and test that the
601 // result is the same as the original value
602 if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
603 Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
611 bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
612 SDValue &Imm) const {
614 EVT EltTy = N->getValueType(0).getVectorElementType();
616 if (N->getOpcode() == ISD::BITCAST)
617 N = N->getOperand(0);
619 if (selectVSplat(N.getNode(), ImmValue) &&
620 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
621 int32_t Log2 = (~ImmValue).exactLogBase2();
624 Imm = CurDAG->getTargetConstant(Log2, EltTy);
632 std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
633 unsigned Opcode = Node->getOpcode();
637 // Instruction Selection not handled by the auto-generated
638 // tablegen selection should be handled here.
646 SDValue InFlag = Node->getOperand(2);
647 Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node);
648 return std::make_pair(true, Result);
652 if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
654 SDValue InFlag = Node->getOperand(2);
655 Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);
656 return std::make_pair(true, Result);
659 case ISD::ConstantFP: {
660 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
661 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
662 if (Subtarget->isGP64bit()) {
663 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
664 Mips::ZERO_64, MVT::i64);
665 Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
666 } else if (Subtarget->isFP64bit()) {
667 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
668 Mips::ZERO, MVT::i32);
669 Result = CurDAG->getMachineNode(Mips::BuildPairF64_64, DL, MVT::f64,
672 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
673 Mips::ZERO, MVT::i32);
674 Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
678 return std::make_pair(true, Result);
683 case ISD::Constant: {
684 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
685 unsigned Size = CN->getValueSizeInBits(0);
690 MipsAnalyzeImmediate AnalyzeImm;
691 int64_t Imm = CN->getSExtValue();
693 const MipsAnalyzeImmediate::InstSeq &Seq =
694 AnalyzeImm.Analyze(Imm, Size, false);
696 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
699 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
702 // The first instruction can be a LUi which is different from other
703 // instructions (ADDiu, ORI and SLL) in that it does not have a register
705 if (Inst->Opc == Mips::LUi64)
706 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
709 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
710 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
713 // The remaining instructions in the sequence are handled here.
714 for (++Inst; Inst != Seq.end(); ++Inst) {
715 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
717 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
718 SDValue(RegOpnd, 0), ImmOpnd);
721 return std::make_pair(true, RegOpnd);
724 case ISD::INTRINSIC_W_CHAIN: {
725 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
729 case Intrinsic::mips_cfcmsa: {
730 SDValue ChainIn = Node->getOperand(0);
731 SDValue RegIdx = Node->getOperand(2);
732 SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
733 getMSACtrlReg(RegIdx), MVT::i32);
734 return std::make_pair(true, Reg.getNode());
740 case ISD::INTRINSIC_WO_CHAIN: {
741 switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
745 case Intrinsic::mips_move_v:
746 // Like an assignment but will always produce a move.v even if
748 return std::make_pair(true,
749 CurDAG->getMachineNode(Mips::MOVE_V, DL,
750 Node->getValueType(0),
751 Node->getOperand(1)));
756 case ISD::INTRINSIC_VOID: {
757 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
761 case Intrinsic::mips_ctcmsa: {
762 SDValue ChainIn = Node->getOperand(0);
763 SDValue RegIdx = Node->getOperand(2);
764 SDValue Value = Node->getOperand(3);
765 SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
766 getMSACtrlReg(RegIdx), Value);
767 return std::make_pair(true, ChainOut.getNode());
773 case MipsISD::ThreadPointer: {
774 EVT PtrVT = getTargetLowering()->getPointerTy();
775 unsigned RdhwrOpc, DestReg;
777 if (PtrVT == MVT::i32) {
778 RdhwrOpc = Mips::RDHWR;
781 RdhwrOpc = Mips::RDHWR64;
782 DestReg = Mips::V1_64;
786 CurDAG->getMachineNode(RdhwrOpc, SDLoc(Node),
787 Node->getValueType(0),
788 CurDAG->getRegister(Mips::HWR29, MVT::i32));
789 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
791 SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
792 ReplaceUses(SDValue(Node, 0), ResNode);
793 return std::make_pair(true, ResNode.getNode());
796 case ISD::BUILD_VECTOR: {
797 // Select appropriate ldi.[bhwd] instructions for constant splats of
798 // 128-bit when MSA is enabled. Fixup any register class mismatches that
799 // occur as a result.
801 // This allows the compiler to use a wider range of immediates than would
802 // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
803 // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
804 // 0x01010101 } without using a constant pool. This would be sub-optimal
805 // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
806 // same set/ of registers. Similarly, ldi.h isn't capable of producing {
807 // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
809 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
810 APInt SplatValue, SplatUndef;
811 unsigned SplatBitSize;
814 EVT ResVecTy = BVN->getValueType(0);
817 if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
818 return std::make_pair(false, nullptr);
820 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
822 !Subtarget->isLittle()))
823 return std::make_pair(false, nullptr);
825 switch (SplatBitSize) {
827 return std::make_pair(false, nullptr);
830 ViaVecTy = MVT::v16i8;
834 ViaVecTy = MVT::v8i16;
838 ViaVecTy = MVT::v4i32;
842 ViaVecTy = MVT::v2i64;
846 if (!SplatValue.isSignedIntN(10))
847 return std::make_pair(false, nullptr);
849 SDValue Imm = CurDAG->getTargetConstant(SplatValue,
850 ViaVecTy.getVectorElementType());
852 SDNode *Res = CurDAG->getMachineNode(LdiOp, SDLoc(Node), ViaVecTy, Imm);
854 if (ResVecTy != ViaVecTy) {
855 // If LdiOp is writing to a different register class to ResVecTy, then
856 // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
857 // since the source and destination register sets contain the same
859 const TargetLowering *TLI = getTargetLowering();
860 MVT ResVecTySimple = ResVecTy.getSimpleVT();
861 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
862 Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, SDLoc(Node),
863 ResVecTy, SDValue(Res, 0),
864 CurDAG->getTargetConstant(RC->getID(),
868 return std::make_pair(true, Res);
873 return std::make_pair(false, nullptr);
876 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
877 return new MipsSEDAGToDAGISel(TM);