1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
13 #define DEBUG_TYPE "mips-isel"
14 #include "MipsSEISelLowering.h"
15 #include "MipsRegisterInfo.h"
16 #include "MipsTargetMachine.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/IR/Intrinsics.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/Target/TargetInstrInfo.h"
28 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
29 cl::desc("MIPS: Enable tail calls."), cl::init(false));
31 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
32 cl::desc("Expand double precision loads and "
33 "stores to their single precision "
36 MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
37 : MipsTargetLowering(TM) {
38 // Set up the register classes
39 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
42 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
44 if (Subtarget->hasDSP() || Subtarget->hasMSA()) {
45 // Expand all truncating stores and extending loads.
46 unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
47 unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
49 for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
50 for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
51 setTruncStoreAction((MVT::SimpleValueType)VT0,
52 (MVT::SimpleValueType)VT1, Expand);
54 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
55 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
56 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
60 if (Subtarget->hasDSP()) {
61 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
63 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
64 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
66 // Expand all builtin opcodes.
67 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
68 setOperationAction(Opc, VecTys[i], Expand);
70 setOperationAction(ISD::ADD, VecTys[i], Legal);
71 setOperationAction(ISD::SUB, VecTys[i], Legal);
72 setOperationAction(ISD::LOAD, VecTys[i], Legal);
73 setOperationAction(ISD::STORE, VecTys[i], Legal);
74 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
77 setTargetDAGCombine(ISD::SHL);
78 setTargetDAGCombine(ISD::SRA);
79 setTargetDAGCombine(ISD::SRL);
80 setTargetDAGCombine(ISD::SETCC);
81 setTargetDAGCombine(ISD::VSELECT);
84 if (Subtarget->hasDSPR2())
85 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
87 if (Subtarget->hasMSA()) {
88 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
89 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
90 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
91 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
92 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
93 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
94 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
96 setTargetDAGCombine(ISD::AND);
97 setTargetDAGCombine(ISD::OR);
98 setTargetDAGCombine(ISD::SRA);
99 setTargetDAGCombine(ISD::VSELECT);
100 setTargetDAGCombine(ISD::XOR);
103 if (!Subtarget->mipsSEUsesSoftFloat()) {
104 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
106 // When dealing with single precision only, use libcalls
107 if (!Subtarget->isSingleFloat()) {
108 if (Subtarget->isFP64bit())
109 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
111 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
115 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
116 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
117 setOperationAction(ISD::MULHS, MVT::i32, Custom);
118 setOperationAction(ISD::MULHU, MVT::i32, Custom);
121 setOperationAction(ISD::MULHS, MVT::i64, Custom);
122 setOperationAction(ISD::MULHU, MVT::i64, Custom);
123 setOperationAction(ISD::MUL, MVT::i64, Custom);
126 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
127 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
129 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
130 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
131 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
132 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
133 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
134 setOperationAction(ISD::LOAD, MVT::i32, Custom);
135 setOperationAction(ISD::STORE, MVT::i32, Custom);
137 setTargetDAGCombine(ISD::ADDE);
138 setTargetDAGCombine(ISD::SUBE);
139 setTargetDAGCombine(ISD::MUL);
141 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
142 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
143 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
146 setOperationAction(ISD::LOAD, MVT::f64, Custom);
147 setOperationAction(ISD::STORE, MVT::f64, Custom);
150 computeRegisterProperties();
153 const MipsTargetLowering *
154 llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
155 return new MipsSETargetLowering(TM);
158 // Enable MSA support for the given integer type and Register class.
159 void MipsSETargetLowering::
160 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
161 addRegisterClass(Ty, RC);
163 // Expand all builtin opcodes.
164 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
165 setOperationAction(Opc, Ty, Expand);
167 setOperationAction(ISD::BITCAST, Ty, Legal);
168 setOperationAction(ISD::LOAD, Ty, Legal);
169 setOperationAction(ISD::STORE, Ty, Legal);
170 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
171 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
172 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
174 setOperationAction(ISD::ADD, Ty, Legal);
175 setOperationAction(ISD::AND, Ty, Legal);
176 setOperationAction(ISD::CTLZ, Ty, Legal);
177 setOperationAction(ISD::CTPOP, Ty, Legal);
178 setOperationAction(ISD::MUL, Ty, Legal);
179 setOperationAction(ISD::OR, Ty, Legal);
180 setOperationAction(ISD::SDIV, Ty, Legal);
181 setOperationAction(ISD::SREM, Ty, Legal);
182 setOperationAction(ISD::SHL, Ty, Legal);
183 setOperationAction(ISD::SRA, Ty, Legal);
184 setOperationAction(ISD::SRL, Ty, Legal);
185 setOperationAction(ISD::SUB, Ty, Legal);
186 setOperationAction(ISD::UDIV, Ty, Legal);
187 setOperationAction(ISD::UREM, Ty, Legal);
188 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
189 setOperationAction(ISD::VSELECT, Ty, Legal);
190 setOperationAction(ISD::XOR, Ty, Legal);
192 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
193 setOperationAction(ISD::FP_TO_SINT, Ty, Legal);
194 setOperationAction(ISD::FP_TO_UINT, Ty, Legal);
195 setOperationAction(ISD::SINT_TO_FP, Ty, Legal);
196 setOperationAction(ISD::UINT_TO_FP, Ty, Legal);
199 setOperationAction(ISD::SETCC, Ty, Legal);
200 setCondCodeAction(ISD::SETNE, Ty, Expand);
201 setCondCodeAction(ISD::SETGE, Ty, Expand);
202 setCondCodeAction(ISD::SETGT, Ty, Expand);
203 setCondCodeAction(ISD::SETUGE, Ty, Expand);
204 setCondCodeAction(ISD::SETUGT, Ty, Expand);
207 // Enable MSA support for the given floating-point type and Register class.
208 void MipsSETargetLowering::
209 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
210 addRegisterClass(Ty, RC);
212 // Expand all builtin opcodes.
213 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
214 setOperationAction(Opc, Ty, Expand);
216 setOperationAction(ISD::LOAD, Ty, Legal);
217 setOperationAction(ISD::STORE, Ty, Legal);
218 setOperationAction(ISD::BITCAST, Ty, Legal);
219 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
220 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
221 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
223 if (Ty != MVT::v8f16) {
224 setOperationAction(ISD::FABS, Ty, Legal);
225 setOperationAction(ISD::FADD, Ty, Legal);
226 setOperationAction(ISD::FDIV, Ty, Legal);
227 setOperationAction(ISD::FEXP2, Ty, Legal);
228 setOperationAction(ISD::FLOG2, Ty, Legal);
229 setOperationAction(ISD::FMA, Ty, Legal);
230 setOperationAction(ISD::FMUL, Ty, Legal);
231 setOperationAction(ISD::FRINT, Ty, Legal);
232 setOperationAction(ISD::FSQRT, Ty, Legal);
233 setOperationAction(ISD::FSUB, Ty, Legal);
234 setOperationAction(ISD::VSELECT, Ty, Legal);
236 setOperationAction(ISD::SETCC, Ty, Legal);
237 setCondCodeAction(ISD::SETOGE, Ty, Expand);
238 setCondCodeAction(ISD::SETOGT, Ty, Expand);
239 setCondCodeAction(ISD::SETUGE, Ty, Expand);
240 setCondCodeAction(ISD::SETUGT, Ty, Expand);
241 setCondCodeAction(ISD::SETGE, Ty, Expand);
242 setCondCodeAction(ISD::SETGT, Ty, Expand);
247 MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
248 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
261 SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
262 SelectionDAG &DAG) const {
263 switch(Op.getOpcode()) {
264 case ISD::LOAD: return lowerLOAD(Op, DAG);
265 case ISD::STORE: return lowerSTORE(Op, DAG);
266 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
267 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
268 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
269 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
270 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
271 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
272 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
274 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
275 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
276 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
277 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
278 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
279 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
282 return MipsTargetLowering::LowerOperation(Op, DAG);
286 // Transforms a subgraph in CurDAG if the following pattern is found:
287 // (addc multLo, Lo0), (adde multHi, Hi0),
289 // multHi/Lo: product of multiplication
290 // Lo0: initial value of Lo register
291 // Hi0: initial value of Hi register
292 // Return true if pattern matching was successful.
293 static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
294 // ADDENode's second operand must be a flag output of an ADDC node in order
295 // for the matching to be successful.
296 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
298 if (ADDCNode->getOpcode() != ISD::ADDC)
301 SDValue MultHi = ADDENode->getOperand(0);
302 SDValue MultLo = ADDCNode->getOperand(0);
303 SDNode *MultNode = MultHi.getNode();
304 unsigned MultOpc = MultHi.getOpcode();
306 // MultHi and MultLo must be generated by the same node,
307 if (MultLo.getNode() != MultNode)
310 // and it must be a multiplication.
311 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
314 // MultLo amd MultHi must be the first and second output of MultNode
316 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
319 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
320 // of the values of MultNode, in which case MultNode will be removed in later
322 // If there exist users other than ADDENode or ADDCNode, this function returns
323 // here, which will result in MultNode being mapped to a single MULT
324 // instruction node rather than a pair of MULT and MADD instructions being
326 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
331 // Initialize accumulator.
332 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
333 ADDCNode->getOperand(1),
334 ADDENode->getOperand(1));
336 // create MipsMAdd(u) node
337 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
339 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
340 MultNode->getOperand(0),// Factor 0
341 MultNode->getOperand(1),// Factor 1
344 // replace uses of adde and addc here
345 if (!SDValue(ADDCNode, 0).use_empty()) {
346 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
347 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
349 if (!SDValue(ADDENode, 0).use_empty()) {
350 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
351 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
358 // Transforms a subgraph in CurDAG if the following pattern is found:
359 // (addc Lo0, multLo), (sube Hi0, multHi),
361 // multHi/Lo: product of multiplication
362 // Lo0: initial value of Lo register
363 // Hi0: initial value of Hi register
364 // Return true if pattern matching was successful.
365 static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
366 // SUBENode's second operand must be a flag output of an SUBC node in order
367 // for the matching to be successful.
368 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
370 if (SUBCNode->getOpcode() != ISD::SUBC)
373 SDValue MultHi = SUBENode->getOperand(1);
374 SDValue MultLo = SUBCNode->getOperand(1);
375 SDNode *MultNode = MultHi.getNode();
376 unsigned MultOpc = MultHi.getOpcode();
378 // MultHi and MultLo must be generated by the same node,
379 if (MultLo.getNode() != MultNode)
382 // and it must be a multiplication.
383 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
386 // MultLo amd MultHi must be the first and second output of MultNode
388 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
391 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
392 // of the values of MultNode, in which case MultNode will be removed in later
394 // If there exist users other than SUBENode or SUBCNode, this function returns
395 // here, which will result in MultNode being mapped to a single MULT
396 // instruction node rather than a pair of MULT and MSUB instructions being
398 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
403 // Initialize accumulator.
404 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
405 SUBCNode->getOperand(0),
406 SUBENode->getOperand(0));
408 // create MipsSub(u) node
409 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
411 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
412 MultNode->getOperand(0),// Factor 0
413 MultNode->getOperand(1),// Factor 1
416 // replace uses of sube and subc here
417 if (!SDValue(SUBCNode, 0).use_empty()) {
418 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub);
419 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
421 if (!SDValue(SUBENode, 0).use_empty()) {
422 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub);
423 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
429 static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
430 TargetLowering::DAGCombinerInfo &DCI,
431 const MipsSubtarget *Subtarget) {
432 if (DCI.isBeforeLegalize())
435 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
437 return SDValue(N, 0);
442 // Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
444 // Performs the following transformations:
445 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
446 // sign/zero-extension is completely overwritten by the new one performed by
448 // - Removes redundant zero extensions performed by an ISD::AND.
449 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
450 TargetLowering::DAGCombinerInfo &DCI,
451 const MipsSubtarget *Subtarget) {
452 if (!Subtarget->hasMSA())
455 SDValue Op0 = N->getOperand(0);
456 SDValue Op1 = N->getOperand(1);
457 unsigned Op0Opcode = Op0->getOpcode();
459 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
460 // where $d + 1 == 2^n and n == 32
461 // or $d + 1 == 2^n and n <= 32 and ZExt
462 // -> (MipsVExtractZExt $a, $b, $c)
463 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
464 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
465 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
470 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
472 if (Log2IfPositive <= 0)
473 return SDValue(); // Mask+1 is not a power of 2
475 SDValue Op0Op2 = Op0->getOperand(2);
476 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
477 unsigned ExtendTySize = ExtendTy.getSizeInBits();
478 unsigned Log2 = Log2IfPositive;
480 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
481 Log2 == ExtendTySize) {
482 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
483 DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT,
484 Op0->getVTList(), Ops, Op0->getNumOperands());
492 // Determine if the specified node is a constant vector splat.
494 // Returns true and sets Imm if:
495 // * N is a ISD::BUILD_VECTOR representing a constant splat
497 // This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The
498 // differences are that it assumes the MSA has already been checked and the
499 // arbitrary requirement for a maximum of 32-bit integers isn't applied (and
500 // must not be in order for binsri.d to be selectable).
501 static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) {
502 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N.getNode());
507 APInt SplatValue, SplatUndef;
508 unsigned SplatBitSize;
511 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
520 // Test whether the given node is an all-ones build_vector.
521 static bool isVectorAllOnes(SDValue N) {
522 // Look through bitcasts. Endianness doesn't matter because we are looking
523 // for an all-ones value.
524 if (N->getOpcode() == ISD::BITCAST)
525 N = N->getOperand(0);
527 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
532 APInt SplatValue, SplatUndef;
533 unsigned SplatBitSize;
536 // Endianness doesn't matter in this context because we are looking for
537 // an all-ones value.
538 if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
539 return SplatValue.isAllOnesValue();
544 // Test whether N is the bitwise inverse of OfNode.
545 static bool isBitwiseInverse(SDValue N, SDValue OfNode) {
546 if (N->getOpcode() != ISD::XOR)
549 if (isVectorAllOnes(N->getOperand(0)))
550 return N->getOperand(1) == OfNode;
552 if (isVectorAllOnes(N->getOperand(1)))
553 return N->getOperand(0) == OfNode;
558 // Perform combines where ISD::OR is the root node.
560 // Performs the following transformations:
561 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
562 // where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
564 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
565 TargetLowering::DAGCombinerInfo &DCI,
566 const MipsSubtarget *Subtarget) {
567 if (!Subtarget->hasMSA())
570 EVT Ty = N->getValueType(0);
572 if (!Ty.is128BitVector())
575 SDValue Op0 = N->getOperand(0);
576 SDValue Op1 = N->getOperand(1);
578 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
579 SDValue Op0Op0 = Op0->getOperand(0);
580 SDValue Op0Op1 = Op0->getOperand(1);
581 SDValue Op1Op0 = Op1->getOperand(0);
582 SDValue Op1Op1 = Op1->getOperand(1);
583 bool IsLittleEndian = !Subtarget->isLittle();
585 SDValue IfSet, IfClr, Cond;
586 bool IsConstantMask = false;
589 // If Op0Op0 is an appropriate mask, try to find it's inverse in either
590 // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while
592 // IfClr will be set if we find a valid match.
593 if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {
597 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
598 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
600 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
601 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
604 IsConstantMask = true;
607 // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same
608 // thing again using this mask.
609 // IfClr will be set if we find a valid match.
610 if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
614 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
615 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
617 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
618 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
621 IsConstantMask = true;
624 // If IfClr is not yet set, try looking for a non-constant match.
625 // IfClr will be set if we find a valid match amongst the eight
627 if (!IfClr.getNode()) {
628 if (isBitwiseInverse(Op0Op0, Op1Op0)) {
632 } else if (isBitwiseInverse(Op0Op1, Op1Op0)) {
636 } else if (isBitwiseInverse(Op0Op0, Op1Op1)) {
640 } else if (isBitwiseInverse(Op0Op1, Op1Op1)) {
644 } else if (isBitwiseInverse(Op1Op0, Op0Op0)) {
648 } else if (isBitwiseInverse(Op1Op1, Op0Op0)) {
652 } else if (isBitwiseInverse(Op1Op0, Op0Op1)) {
656 } else if (isBitwiseInverse(Op1Op1, Op0Op1)) {
663 // At this point, IfClr will be set if we have a valid match.
664 if (!IfClr.getNode())
667 assert(Cond.getNode() && IfSet.getNode());
669 // Fold degenerate cases.
670 if (IsConstantMask) {
671 if (Mask.isAllOnesValue())
677 // Transform the DAG into an equivalent VSELECT.
678 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfClr, IfSet);
684 static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
685 TargetLowering::DAGCombinerInfo &DCI,
686 const MipsSubtarget *Subtarget) {
687 if (DCI.isBeforeLegalize())
690 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
692 return SDValue(N, 0);
697 static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
698 EVT ShiftTy, SelectionDAG &DAG) {
699 // Clear the upper (64 - VT.sizeInBits) bits.
700 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
704 return DAG.getConstant(0, VT);
710 // If c is power of 2, return (shl x, log2(c)).
711 if (isPowerOf2_64(C))
712 return DAG.getNode(ISD::SHL, DL, VT, X,
713 DAG.getConstant(Log2_64(C), ShiftTy));
715 unsigned Log2Ceil = Log2_64_Ceil(C);
716 uint64_t Floor = 1LL << Log2_64(C);
717 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
719 // If |c - floor_c| <= |c - ceil_c|,
720 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
721 // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
722 if (C - Floor <= Ceil - C) {
723 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
724 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
725 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
728 // If |c - floor_c| > |c - ceil_c|,
729 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
730 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
731 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
732 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
735 static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
736 const TargetLowering::DAGCombinerInfo &DCI,
737 const MipsSETargetLowering *TL) {
738 EVT VT = N->getValueType(0);
740 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
742 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
743 VT, TL->getScalarShiftAmountTy(VT), DAG);
745 return SDValue(N, 0);
748 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
750 const MipsSubtarget *Subtarget) {
751 // See if this is a vector splat immediate node.
752 APInt SplatValue, SplatUndef;
753 unsigned SplatBitSize;
755 unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
756 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
758 if (!Subtarget->hasDSP())
762 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
763 EltSize, !Subtarget->isLittle()) ||
764 (SplatBitSize != EltSize) ||
765 (SplatValue.getZExtValue() >= EltSize))
768 return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
769 DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
772 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
773 TargetLowering::DAGCombinerInfo &DCI,
774 const MipsSubtarget *Subtarget) {
775 EVT Ty = N->getValueType(0);
777 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
780 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
783 // Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
784 // constant splats into MipsISD::SHRA_DSP for DSPr2.
786 // Performs the following transformations:
787 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
788 // sign/zero-extension is completely overwritten by the new one performed by
789 // the ISD::SRA and ISD::SHL nodes.
790 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
793 // See performDSPShiftCombine for more information about the transformation
795 static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
796 TargetLowering::DAGCombinerInfo &DCI,
797 const MipsSubtarget *Subtarget) {
798 EVT Ty = N->getValueType(0);
800 if (Subtarget->hasMSA()) {
801 SDValue Op0 = N->getOperand(0);
802 SDValue Op1 = N->getOperand(1);
804 // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
805 // where $d + sizeof($c) == 32
806 // or $d + sizeof($c) <= 32 and SExt
807 // -> (MipsVExtractSExt $a, $b, $c)
808 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
809 SDValue Op0Op0 = Op0->getOperand(0);
810 ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
815 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
816 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)
819 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
820 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
822 if (TotalBits == 32 ||
823 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
825 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
826 Op0Op0->getOperand(2) };
827 DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT,
828 Op0Op0->getVTList(), Ops, Op0Op0->getNumOperands());
834 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
837 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
841 static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
842 TargetLowering::DAGCombinerInfo &DCI,
843 const MipsSubtarget *Subtarget) {
844 EVT Ty = N->getValueType(0);
846 if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
849 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
852 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
853 bool IsV216 = (Ty == MVT::v2i16);
857 case ISD::SETNE: return true;
861 case ISD::SETGE: return IsV216;
865 case ISD::SETUGE: return !IsV216;
866 default: return false;
870 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
871 EVT Ty = N->getValueType(0);
873 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
876 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
879 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
880 N->getOperand(1), N->getOperand(2));
883 static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
884 EVT Ty = N->getValueType(0);
886 if (Ty.is128BitVector() && Ty.isInteger()) {
887 // Try the following combines:
888 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
889 // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
890 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
891 // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
892 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
893 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
894 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
895 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
896 // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
897 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
899 SDValue Op0 = N->getOperand(0);
901 if (Op0->getOpcode() != ISD::SETCC)
904 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
907 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE)
909 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
914 SDValue Op1 = N->getOperand(1);
915 SDValue Op2 = N->getOperand(2);
916 SDValue Op0Op0 = Op0->getOperand(0);
917 SDValue Op0Op1 = Op0->getOperand(1);
919 if (Op1 == Op0Op0 && Op2 == Op0Op1)
920 return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
922 else if (Op1 == Op0Op1 && Op2 == Op0Op0)
923 return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
925 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
926 SDValue SetCC = N->getOperand(0);
928 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
931 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
932 SetCC.getOperand(0), SetCC.getOperand(1),
933 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
939 static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
940 const MipsSubtarget *Subtarget) {
941 EVT Ty = N->getValueType(0);
943 if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
944 // Try the following combines:
945 // (xor (or $a, $b), (build_vector allones))
946 // (xor (or $a, $b), (bitcast (build_vector allones)))
947 SDValue Op0 = N->getOperand(0);
948 SDValue Op1 = N->getOperand(1);
951 if (ISD::isBuildVectorAllOnes(Op0.getNode()))
953 else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
958 if (NotOp->getOpcode() == ISD::OR)
959 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
960 NotOp->getOperand(1));
967 MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
968 SelectionDAG &DAG = DCI.DAG;
971 switch (N->getOpcode()) {
973 return performADDECombine(N, DAG, DCI, Subtarget);
975 Val = performANDCombine(N, DAG, DCI, Subtarget);
978 Val = performORCombine(N, DAG, DCI, Subtarget);
981 return performSUBECombine(N, DAG, DCI, Subtarget);
983 return performMULCombine(N, DAG, DCI, this);
985 return performSHLCombine(N, DAG, DCI, Subtarget);
987 return performSRACombine(N, DAG, DCI, Subtarget);
989 return performSRLCombine(N, DAG, DCI, Subtarget);
991 return performVSELECTCombine(N, DAG);
993 Val = performXORCombine(N, DAG, Subtarget);
996 Val = performSETCCCombine(N, DAG);
1000 if (Val.getNode()) {
1001 DEBUG(dbgs() << "\nMipsSE DAG Combine:\n";
1002 N->printrWithDepth(dbgs(), &DAG);
1003 dbgs() << "\n=> \n";
1004 Val.getNode()->printrWithDepth(dbgs(), &DAG);
1009 return MipsTargetLowering::PerformDAGCombine(N, DCI);
1013 MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1014 MachineBasicBlock *BB) const {
1015 switch (MI->getOpcode()) {
1017 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
1018 case Mips::BPOSGE32_PSEUDO:
1019 return emitBPOSGE32(MI, BB);
1020 case Mips::SNZ_B_PSEUDO:
1021 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
1022 case Mips::SNZ_H_PSEUDO:
1023 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
1024 case Mips::SNZ_W_PSEUDO:
1025 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
1026 case Mips::SNZ_D_PSEUDO:
1027 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
1028 case Mips::SNZ_V_PSEUDO:
1029 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
1030 case Mips::SZ_B_PSEUDO:
1031 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
1032 case Mips::SZ_H_PSEUDO:
1033 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
1034 case Mips::SZ_W_PSEUDO:
1035 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
1036 case Mips::SZ_D_PSEUDO:
1037 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
1038 case Mips::SZ_V_PSEUDO:
1039 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
1040 case Mips::COPY_FW_PSEUDO:
1041 return emitCOPY_FW(MI, BB);
1042 case Mips::COPY_FD_PSEUDO:
1043 return emitCOPY_FD(MI, BB);
1044 case Mips::INSERT_FW_PSEUDO:
1045 return emitINSERT_FW(MI, BB);
1046 case Mips::INSERT_FD_PSEUDO:
1047 return emitINSERT_FD(MI, BB);
1048 case Mips::FILL_FW_PSEUDO:
1049 return emitFILL_FW(MI, BB);
1050 case Mips::FILL_FD_PSEUDO:
1051 return emitFILL_FD(MI, BB);
1052 case Mips::FEXP2_W_1_PSEUDO:
1053 return emitFEXP2_W_1(MI, BB);
1054 case Mips::FEXP2_D_1_PSEUDO:
1055 return emitFEXP2_D_1(MI, BB);
1059 bool MipsSETargetLowering::
1060 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
1061 unsigned NextStackOffset,
1062 const MipsFunctionInfo& FI) const {
1063 if (!EnableMipsTailCalls)
1066 // Return false if either the callee or caller has a byval argument.
1067 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
1070 // Return true if the callee's argument area is no larger than the
1072 return NextStackOffset <= FI.getIncomingArgSize();
1075 void MipsSETargetLowering::
1076 getOpndList(SmallVectorImpl<SDValue> &Ops,
1077 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
1078 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
1079 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
1080 // T9 should contain the address of the callee function if
1081 // -reloction-model=pic or it is an indirect call.
1082 if (IsPICCall || !GlobalOrExternal) {
1083 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
1084 RegsToPass.push_front(std::make_pair(T9Reg, Callee));
1086 Ops.push_back(Callee);
1088 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
1089 InternalLinkage, CLI, Callee, Chain);
1092 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1093 LoadSDNode &Nd = *cast<LoadSDNode>(Op);
1095 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1096 return MipsTargetLowering::lowerLOAD(Op, DAG);
1098 // Replace a double precision load with two i32 loads and a buildpair64.
1100 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1101 EVT PtrVT = Ptr.getValueType();
1103 // i32 load from lower address.
1104 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
1105 MachinePointerInfo(), Nd.isVolatile(),
1106 Nd.isNonTemporal(), Nd.isInvariant(),
1109 // i32 load from higher address.
1110 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
1111 SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
1112 MachinePointerInfo(), Nd.isVolatile(),
1113 Nd.isNonTemporal(), Nd.isInvariant(),
1114 std::min(Nd.getAlignment(), 4U));
1116 if (!Subtarget->isLittle())
1119 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1120 SDValue Ops[2] = {BP, Hi.getValue(1)};
1121 return DAG.getMergeValues(Ops, 2, DL);
1124 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1125 StoreSDNode &Nd = *cast<StoreSDNode>(Op);
1127 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1128 return MipsTargetLowering::lowerSTORE(Op, DAG);
1130 // Replace a double precision store with two extractelement64s and i32 stores.
1132 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1133 EVT PtrVT = Ptr.getValueType();
1134 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1135 Val, DAG.getConstant(0, MVT::i32));
1136 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1137 Val, DAG.getConstant(1, MVT::i32));
1139 if (!Subtarget->isLittle())
1142 // i32 store to lower address.
1143 Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
1144 Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
1147 // i32 store to higher address.
1148 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
1149 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
1150 Nd.isVolatile(), Nd.isNonTemporal(),
1151 std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo());
1154 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
1155 bool HasLo, bool HasHi,
1156 SelectionDAG &DAG) const {
1157 EVT Ty = Op.getOperand(0).getValueType();
1159 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
1160 Op.getOperand(0), Op.getOperand(1));
1164 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);
1166 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);
1168 if (!HasLo || !HasHi)
1169 return HasLo ? Lo : Hi;
1171 SDValue Vals[] = { Lo, Hi };
1172 return DAG.getMergeValues(Vals, 2, DL);
1176 static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
1177 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1178 DAG.getConstant(0, MVT::i32));
1179 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1180 DAG.getConstant(1, MVT::i32));
1181 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
1184 static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
1185 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op);
1186 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op);
1187 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1190 // This function expands mips intrinsic nodes which have 64-bit input operands
1191 // or output values.
1193 // out64 = intrinsic-node in64
1195 // lo = copy (extract-element (in64, 0))
1196 // hi = copy (extract-element (in64, 1))
1197 // mips-specific-node
1200 // out64 = merge-values (v0, v1)
1202 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1204 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
1205 SmallVector<SDValue, 3> Ops;
1208 // See if Op has a chain input.
1210 Ops.push_back(Op->getOperand(OpNo++));
1212 // The next operand is the intrinsic opcode.
1213 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
1215 // See if the next operand has type i64.
1216 SDValue Opnd = Op->getOperand(++OpNo), In64;
1218 if (Opnd.getValueType() == MVT::i64)
1219 In64 = initAccumulator(Opnd, DL, DAG);
1221 Ops.push_back(Opnd);
1223 // Push the remaining operands.
1224 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1225 Ops.push_back(Op->getOperand(OpNo));
1227 // Add In64 to the end of the list.
1229 Ops.push_back(In64);
1232 SmallVector<EVT, 2> ResTys;
1234 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1236 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1239 SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
1240 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1245 assert(Val->getValueType(1) == MVT::Other);
1246 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1247 return DAG.getMergeValues(Vals, 2, DL);
1250 // Lower an MSA copy intrinsic into the specified SelectionDAG node
1251 static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1253 SDValue Vec = Op->getOperand(1);
1254 SDValue Idx = Op->getOperand(2);
1255 EVT ResTy = Op->getValueType(0);
1256 EVT EltTy = Vec->getValueType(0).getVectorElementType();
1258 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1259 DAG.getValueType(EltTy));
1264 static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
1265 EVT ResVecTy = Op->getValueType(0);
1266 EVT ViaVecTy = ResVecTy;
1269 // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and
1270 // LaneB is the lower 32-bits. Otherwise LaneA and LaneB are alternating
1273 SDValue LaneB = Op->getOperand(2);
1275 if (ResVecTy == MVT::v2i64) {
1276 LaneA = DAG.getConstant(0, MVT::i32);
1277 ViaVecTy = MVT::v4i32;
1281 SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1282 LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
1284 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, Ops,
1285 ViaVecTy.getVectorNumElements());
1287 if (ViaVecTy != ResVecTy)
1288 Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result);
1293 static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
1294 return DAG.getConstant(Op->getConstantOperandVal(ImmOp), Op->getValueType(0));
1297 static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
1298 bool BigEndian, SelectionDAG &DAG) {
1299 EVT ViaVecTy = VecTy;
1300 SDValue SplatValueA = SplatValue;
1301 SDValue SplatValueB = SplatValue;
1302 SDLoc DL(SplatValue);
1304 if (VecTy == MVT::v2i64) {
1305 // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
1306 ViaVecTy = MVT::v4i32;
1308 SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue);
1309 SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue,
1310 DAG.getConstant(32, MVT::i32));
1311 SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB);
1314 // We currently hold the parts in little endian order. Swap them if
1317 std::swap(SplatValueA, SplatValueB);
1319 SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1320 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1321 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1322 SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1324 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, Ops,
1325 ViaVecTy.getVectorNumElements());
1327 if (VecTy != ViaVecTy)
1328 Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
1333 static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG,
1334 unsigned Opc, SDValue Imm,
1336 EVT VecTy = Op->getValueType(0);
1340 // The DAG Combiner can't constant fold bitcasted vectors yet so we must do it
1342 if (VecTy == MVT::v2i64) {
1343 if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
1344 APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();
1346 SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), MVT::i32);
1347 SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), MVT::i32);
1350 std::swap(BitImmLoOp, BitImmHiOp);
1353 DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
1354 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, BitImmLoOp,
1355 BitImmHiOp, BitImmLoOp, BitImmHiOp));
1359 if (Exp2Imm.getNode() == NULL) {
1360 // We couldnt constant fold, do a vector shift instead
1362 // Extend i32 to i64 if necessary. Sign or zero extend doesn't matter since
1363 // only values 0-63 are valid.
1364 if (VecTy == MVT::v2i64)
1365 Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm);
1367 Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG);
1370 DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, VecTy), Exp2Imm);
1373 return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
1376 static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG) {
1377 EVT ResTy = Op->getValueType(0);
1379 SDValue One = DAG.getConstant(1, ResTy);
1380 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2));
1382 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1383 DAG.getNOT(DL, Bit, ResTy));
1386 static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) {
1388 EVT ResTy = Op->getValueType(0);
1389 APInt BitImm = APInt(ResTy.getVectorElementType().getSizeInBits(), 1)
1390 << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
1391 SDValue BitMask = DAG.getConstant(~BitImm, ResTy);
1393 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1396 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1397 SelectionDAG &DAG) const {
1400 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
1403 case Intrinsic::mips_shilo:
1404 return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1405 case Intrinsic::mips_dpau_h_qbl:
1406 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1407 case Intrinsic::mips_dpau_h_qbr:
1408 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1409 case Intrinsic::mips_dpsu_h_qbl:
1410 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1411 case Intrinsic::mips_dpsu_h_qbr:
1412 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1413 case Intrinsic::mips_dpa_w_ph:
1414 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1415 case Intrinsic::mips_dps_w_ph:
1416 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1417 case Intrinsic::mips_dpax_w_ph:
1418 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1419 case Intrinsic::mips_dpsx_w_ph:
1420 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1421 case Intrinsic::mips_mulsa_w_ph:
1422 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1423 case Intrinsic::mips_mult:
1424 return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1425 case Intrinsic::mips_multu:
1426 return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1427 case Intrinsic::mips_madd:
1428 return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1429 case Intrinsic::mips_maddu:
1430 return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1431 case Intrinsic::mips_msub:
1432 return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1433 case Intrinsic::mips_msubu:
1434 return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1435 case Intrinsic::mips_addv_b:
1436 case Intrinsic::mips_addv_h:
1437 case Intrinsic::mips_addv_w:
1438 case Intrinsic::mips_addv_d:
1439 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1441 case Intrinsic::mips_addvi_b:
1442 case Intrinsic::mips_addvi_h:
1443 case Intrinsic::mips_addvi_w:
1444 case Intrinsic::mips_addvi_d:
1445 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1446 lowerMSASplatImm(Op, 2, DAG));
1447 case Intrinsic::mips_and_v:
1448 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1450 case Intrinsic::mips_andi_b:
1451 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1452 lowerMSASplatImm(Op, 2, DAG));
1453 case Intrinsic::mips_bclr_b:
1454 case Intrinsic::mips_bclr_h:
1455 case Intrinsic::mips_bclr_w:
1456 case Intrinsic::mips_bclr_d:
1457 return lowerMSABitClear(Op, DAG);
1458 case Intrinsic::mips_bclri_b:
1459 case Intrinsic::mips_bclri_h:
1460 case Intrinsic::mips_bclri_w:
1461 case Intrinsic::mips_bclri_d:
1462 return lowerMSABitClearImm(Op, DAG);
1463 case Intrinsic::mips_binsli_b:
1464 case Intrinsic::mips_binsli_h:
1465 case Intrinsic::mips_binsli_w:
1466 case Intrinsic::mips_binsli_d: {
1467 EVT VecTy = Op->getValueType(0);
1468 EVT EltTy = VecTy.getVectorElementType();
1469 APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(),
1470 Op->getConstantOperandVal(3));
1471 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1472 DAG.getConstant(Mask, VecTy, true), Op->getOperand(1),
1475 case Intrinsic::mips_binsri_b:
1476 case Intrinsic::mips_binsri_h:
1477 case Intrinsic::mips_binsri_w:
1478 case Intrinsic::mips_binsri_d: {
1479 EVT VecTy = Op->getValueType(0);
1480 EVT EltTy = VecTy.getVectorElementType();
1481 APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(),
1482 Op->getConstantOperandVal(3));
1483 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1484 DAG.getConstant(Mask, VecTy, true), Op->getOperand(1),
1487 case Intrinsic::mips_bmnz_v:
1488 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1489 Op->getOperand(2), Op->getOperand(1));
1490 case Intrinsic::mips_bmnzi_b:
1491 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1492 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2),
1494 case Intrinsic::mips_bmz_v:
1495 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1496 Op->getOperand(1), Op->getOperand(2));
1497 case Intrinsic::mips_bmzi_b:
1498 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1499 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1),
1501 case Intrinsic::mips_bneg_b:
1502 case Intrinsic::mips_bneg_h:
1503 case Intrinsic::mips_bneg_w:
1504 case Intrinsic::mips_bneg_d: {
1505 EVT VecTy = Op->getValueType(0);
1506 SDValue One = DAG.getConstant(1, VecTy);
1508 return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
1509 DAG.getNode(ISD::SHL, DL, VecTy, One,
1510 Op->getOperand(2)));
1512 case Intrinsic::mips_bnegi_b:
1513 case Intrinsic::mips_bnegi_h:
1514 case Intrinsic::mips_bnegi_w:
1515 case Intrinsic::mips_bnegi_d:
1516 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
1517 !Subtarget->isLittle());
1518 case Intrinsic::mips_bnz_b:
1519 case Intrinsic::mips_bnz_h:
1520 case Intrinsic::mips_bnz_w:
1521 case Intrinsic::mips_bnz_d:
1522 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1524 case Intrinsic::mips_bnz_v:
1525 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1527 case Intrinsic::mips_bsel_v:
1528 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1529 Op->getOperand(1), Op->getOperand(2),
1531 case Intrinsic::mips_bseli_b:
1532 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1533 Op->getOperand(1), Op->getOperand(2),
1534 lowerMSASplatImm(Op, 3, DAG));
1535 case Intrinsic::mips_bset_b:
1536 case Intrinsic::mips_bset_h:
1537 case Intrinsic::mips_bset_w:
1538 case Intrinsic::mips_bset_d: {
1539 EVT VecTy = Op->getValueType(0);
1540 SDValue One = DAG.getConstant(1, VecTy);
1542 return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
1543 DAG.getNode(ISD::SHL, DL, VecTy, One,
1544 Op->getOperand(2)));
1546 case Intrinsic::mips_bseti_b:
1547 case Intrinsic::mips_bseti_h:
1548 case Intrinsic::mips_bseti_w:
1549 case Intrinsic::mips_bseti_d:
1550 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
1551 !Subtarget->isLittle());
1552 case Intrinsic::mips_bz_b:
1553 case Intrinsic::mips_bz_h:
1554 case Intrinsic::mips_bz_w:
1555 case Intrinsic::mips_bz_d:
1556 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1558 case Intrinsic::mips_bz_v:
1559 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1561 case Intrinsic::mips_ceq_b:
1562 case Intrinsic::mips_ceq_h:
1563 case Intrinsic::mips_ceq_w:
1564 case Intrinsic::mips_ceq_d:
1565 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1566 Op->getOperand(2), ISD::SETEQ);
1567 case Intrinsic::mips_ceqi_b:
1568 case Intrinsic::mips_ceqi_h:
1569 case Intrinsic::mips_ceqi_w:
1570 case Intrinsic::mips_ceqi_d:
1571 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1572 lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ);
1573 case Intrinsic::mips_cle_s_b:
1574 case Intrinsic::mips_cle_s_h:
1575 case Intrinsic::mips_cle_s_w:
1576 case Intrinsic::mips_cle_s_d:
1577 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1578 Op->getOperand(2), ISD::SETLE);
1579 case Intrinsic::mips_clei_s_b:
1580 case Intrinsic::mips_clei_s_h:
1581 case Intrinsic::mips_clei_s_w:
1582 case Intrinsic::mips_clei_s_d:
1583 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1584 lowerMSASplatImm(Op, 2, DAG), ISD::SETLE);
1585 case Intrinsic::mips_cle_u_b:
1586 case Intrinsic::mips_cle_u_h:
1587 case Intrinsic::mips_cle_u_w:
1588 case Intrinsic::mips_cle_u_d:
1589 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1590 Op->getOperand(2), ISD::SETULE);
1591 case Intrinsic::mips_clei_u_b:
1592 case Intrinsic::mips_clei_u_h:
1593 case Intrinsic::mips_clei_u_w:
1594 case Intrinsic::mips_clei_u_d:
1595 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1596 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1597 case Intrinsic::mips_clt_s_b:
1598 case Intrinsic::mips_clt_s_h:
1599 case Intrinsic::mips_clt_s_w:
1600 case Intrinsic::mips_clt_s_d:
1601 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1602 Op->getOperand(2), ISD::SETLT);
1603 case Intrinsic::mips_clti_s_b:
1604 case Intrinsic::mips_clti_s_h:
1605 case Intrinsic::mips_clti_s_w:
1606 case Intrinsic::mips_clti_s_d:
1607 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1608 lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);
1609 case Intrinsic::mips_clt_u_b:
1610 case Intrinsic::mips_clt_u_h:
1611 case Intrinsic::mips_clt_u_w:
1612 case Intrinsic::mips_clt_u_d:
1613 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1614 Op->getOperand(2), ISD::SETULT);
1615 case Intrinsic::mips_clti_u_b:
1616 case Intrinsic::mips_clti_u_h:
1617 case Intrinsic::mips_clti_u_w:
1618 case Intrinsic::mips_clti_u_d:
1619 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1620 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1621 case Intrinsic::mips_copy_s_b:
1622 case Intrinsic::mips_copy_s_h:
1623 case Intrinsic::mips_copy_s_w:
1624 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1625 case Intrinsic::mips_copy_s_d:
1626 // Don't lower directly into VEXTRACT_SEXT_ELT since i64 might be illegal.
1627 // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type
1628 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1629 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1630 Op->getOperand(1), Op->getOperand(2));
1631 case Intrinsic::mips_copy_u_b:
1632 case Intrinsic::mips_copy_u_h:
1633 case Intrinsic::mips_copy_u_w:
1634 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1635 case Intrinsic::mips_copy_u_d:
1636 // Don't lower directly into VEXTRACT_ZEXT_ELT since i64 might be illegal.
1637 // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type
1638 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1640 // Note: When i64 is illegal, this results in copy_s.w instructions instead
1641 // of copy_u.w instructions. This makes no difference to the behaviour
1642 // since i64 is only illegal when the register file is 32-bit.
1643 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1644 Op->getOperand(1), Op->getOperand(2));
1645 case Intrinsic::mips_div_s_b:
1646 case Intrinsic::mips_div_s_h:
1647 case Intrinsic::mips_div_s_w:
1648 case Intrinsic::mips_div_s_d:
1649 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1651 case Intrinsic::mips_div_u_b:
1652 case Intrinsic::mips_div_u_h:
1653 case Intrinsic::mips_div_u_w:
1654 case Intrinsic::mips_div_u_d:
1655 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1657 case Intrinsic::mips_fadd_w:
1658 case Intrinsic::mips_fadd_d:
1659 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1661 // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1662 case Intrinsic::mips_fceq_w:
1663 case Intrinsic::mips_fceq_d:
1664 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1665 Op->getOperand(2), ISD::SETOEQ);
1666 case Intrinsic::mips_fcle_w:
1667 case Intrinsic::mips_fcle_d:
1668 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1669 Op->getOperand(2), ISD::SETOLE);
1670 case Intrinsic::mips_fclt_w:
1671 case Intrinsic::mips_fclt_d:
1672 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1673 Op->getOperand(2), ISD::SETOLT);
1674 case Intrinsic::mips_fcne_w:
1675 case Intrinsic::mips_fcne_d:
1676 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1677 Op->getOperand(2), ISD::SETONE);
1678 case Intrinsic::mips_fcor_w:
1679 case Intrinsic::mips_fcor_d:
1680 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1681 Op->getOperand(2), ISD::SETO);
1682 case Intrinsic::mips_fcueq_w:
1683 case Intrinsic::mips_fcueq_d:
1684 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1685 Op->getOperand(2), ISD::SETUEQ);
1686 case Intrinsic::mips_fcule_w:
1687 case Intrinsic::mips_fcule_d:
1688 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1689 Op->getOperand(2), ISD::SETULE);
1690 case Intrinsic::mips_fcult_w:
1691 case Intrinsic::mips_fcult_d:
1692 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1693 Op->getOperand(2), ISD::SETULT);
1694 case Intrinsic::mips_fcun_w:
1695 case Intrinsic::mips_fcun_d:
1696 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1697 Op->getOperand(2), ISD::SETUO);
1698 case Intrinsic::mips_fcune_w:
1699 case Intrinsic::mips_fcune_d:
1700 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1701 Op->getOperand(2), ISD::SETUNE);
1702 case Intrinsic::mips_fdiv_w:
1703 case Intrinsic::mips_fdiv_d:
1704 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1706 case Intrinsic::mips_ffint_u_w:
1707 case Intrinsic::mips_ffint_u_d:
1708 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1710 case Intrinsic::mips_ffint_s_w:
1711 case Intrinsic::mips_ffint_s_d:
1712 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1714 case Intrinsic::mips_fill_b:
1715 case Intrinsic::mips_fill_h:
1716 case Intrinsic::mips_fill_w:
1717 case Intrinsic::mips_fill_d: {
1718 SmallVector<SDValue, 16> Ops;
1719 EVT ResTy = Op->getValueType(0);
1721 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1722 Ops.push_back(Op->getOperand(1));
1724 // If ResTy is v2i64 then the type legalizer will break this node down into
1725 // an equivalent v4i32.
1726 return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, &Ops[0], Ops.size());
1728 case Intrinsic::mips_fexp2_w:
1729 case Intrinsic::mips_fexp2_d: {
1730 EVT ResTy = Op->getValueType(0);
1732 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1733 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1735 case Intrinsic::mips_flog2_w:
1736 case Intrinsic::mips_flog2_d:
1737 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1738 case Intrinsic::mips_fmadd_w:
1739 case Intrinsic::mips_fmadd_d:
1740 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1741 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1742 case Intrinsic::mips_fmul_w:
1743 case Intrinsic::mips_fmul_d:
1744 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1746 case Intrinsic::mips_fmsub_w:
1747 case Intrinsic::mips_fmsub_d: {
1748 EVT ResTy = Op->getValueType(0);
1749 return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
1750 DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,
1751 Op->getOperand(2), Op->getOperand(3)));
1753 case Intrinsic::mips_frint_w:
1754 case Intrinsic::mips_frint_d:
1755 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1756 case Intrinsic::mips_fsqrt_w:
1757 case Intrinsic::mips_fsqrt_d:
1758 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1759 case Intrinsic::mips_fsub_w:
1760 case Intrinsic::mips_fsub_d:
1761 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1763 case Intrinsic::mips_ftrunc_u_w:
1764 case Intrinsic::mips_ftrunc_u_d:
1765 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1767 case Intrinsic::mips_ftrunc_s_w:
1768 case Intrinsic::mips_ftrunc_s_d:
1769 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1771 case Intrinsic::mips_ilvev_b:
1772 case Intrinsic::mips_ilvev_h:
1773 case Intrinsic::mips_ilvev_w:
1774 case Intrinsic::mips_ilvev_d:
1775 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
1776 Op->getOperand(1), Op->getOperand(2));
1777 case Intrinsic::mips_ilvl_b:
1778 case Intrinsic::mips_ilvl_h:
1779 case Intrinsic::mips_ilvl_w:
1780 case Intrinsic::mips_ilvl_d:
1781 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
1782 Op->getOperand(1), Op->getOperand(2));
1783 case Intrinsic::mips_ilvod_b:
1784 case Intrinsic::mips_ilvod_h:
1785 case Intrinsic::mips_ilvod_w:
1786 case Intrinsic::mips_ilvod_d:
1787 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
1788 Op->getOperand(1), Op->getOperand(2));
1789 case Intrinsic::mips_ilvr_b:
1790 case Intrinsic::mips_ilvr_h:
1791 case Intrinsic::mips_ilvr_w:
1792 case Intrinsic::mips_ilvr_d:
1793 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
1794 Op->getOperand(1), Op->getOperand(2));
1795 case Intrinsic::mips_insert_b:
1796 case Intrinsic::mips_insert_h:
1797 case Intrinsic::mips_insert_w:
1798 case Intrinsic::mips_insert_d:
1799 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1800 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1801 case Intrinsic::mips_ldi_b:
1802 case Intrinsic::mips_ldi_h:
1803 case Intrinsic::mips_ldi_w:
1804 case Intrinsic::mips_ldi_d:
1805 return lowerMSASplatImm(Op, 1, DAG);
1806 case Intrinsic::mips_lsa: {
1807 EVT ResTy = Op->getValueType(0);
1808 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1809 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
1810 Op->getOperand(2), Op->getOperand(3)));
1812 case Intrinsic::mips_maddv_b:
1813 case Intrinsic::mips_maddv_h:
1814 case Intrinsic::mips_maddv_w:
1815 case Intrinsic::mips_maddv_d: {
1816 EVT ResTy = Op->getValueType(0);
1817 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1818 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1819 Op->getOperand(2), Op->getOperand(3)));
1821 case Intrinsic::mips_max_s_b:
1822 case Intrinsic::mips_max_s_h:
1823 case Intrinsic::mips_max_s_w:
1824 case Intrinsic::mips_max_s_d:
1825 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1826 Op->getOperand(1), Op->getOperand(2));
1827 case Intrinsic::mips_max_u_b:
1828 case Intrinsic::mips_max_u_h:
1829 case Intrinsic::mips_max_u_w:
1830 case Intrinsic::mips_max_u_d:
1831 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1832 Op->getOperand(1), Op->getOperand(2));
1833 case Intrinsic::mips_maxi_s_b:
1834 case Intrinsic::mips_maxi_s_h:
1835 case Intrinsic::mips_maxi_s_w:
1836 case Intrinsic::mips_maxi_s_d:
1837 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1838 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1839 case Intrinsic::mips_maxi_u_b:
1840 case Intrinsic::mips_maxi_u_h:
1841 case Intrinsic::mips_maxi_u_w:
1842 case Intrinsic::mips_maxi_u_d:
1843 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1844 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1845 case Intrinsic::mips_min_s_b:
1846 case Intrinsic::mips_min_s_h:
1847 case Intrinsic::mips_min_s_w:
1848 case Intrinsic::mips_min_s_d:
1849 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1850 Op->getOperand(1), Op->getOperand(2));
1851 case Intrinsic::mips_min_u_b:
1852 case Intrinsic::mips_min_u_h:
1853 case Intrinsic::mips_min_u_w:
1854 case Intrinsic::mips_min_u_d:
1855 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1856 Op->getOperand(1), Op->getOperand(2));
1857 case Intrinsic::mips_mini_s_b:
1858 case Intrinsic::mips_mini_s_h:
1859 case Intrinsic::mips_mini_s_w:
1860 case Intrinsic::mips_mini_s_d:
1861 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1862 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1863 case Intrinsic::mips_mini_u_b:
1864 case Intrinsic::mips_mini_u_h:
1865 case Intrinsic::mips_mini_u_w:
1866 case Intrinsic::mips_mini_u_d:
1867 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1868 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1869 case Intrinsic::mips_mod_s_b:
1870 case Intrinsic::mips_mod_s_h:
1871 case Intrinsic::mips_mod_s_w:
1872 case Intrinsic::mips_mod_s_d:
1873 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
1875 case Intrinsic::mips_mod_u_b:
1876 case Intrinsic::mips_mod_u_h:
1877 case Intrinsic::mips_mod_u_w:
1878 case Intrinsic::mips_mod_u_d:
1879 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
1881 case Intrinsic::mips_mulv_b:
1882 case Intrinsic::mips_mulv_h:
1883 case Intrinsic::mips_mulv_w:
1884 case Intrinsic::mips_mulv_d:
1885 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
1887 case Intrinsic::mips_msubv_b:
1888 case Intrinsic::mips_msubv_h:
1889 case Intrinsic::mips_msubv_w:
1890 case Intrinsic::mips_msubv_d: {
1891 EVT ResTy = Op->getValueType(0);
1892 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
1893 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1894 Op->getOperand(2), Op->getOperand(3)));
1896 case Intrinsic::mips_nlzc_b:
1897 case Intrinsic::mips_nlzc_h:
1898 case Intrinsic::mips_nlzc_w:
1899 case Intrinsic::mips_nlzc_d:
1900 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
1901 case Intrinsic::mips_nor_v: {
1902 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1903 Op->getOperand(1), Op->getOperand(2));
1904 return DAG.getNOT(DL, Res, Res->getValueType(0));
1906 case Intrinsic::mips_nori_b: {
1907 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1909 lowerMSASplatImm(Op, 2, DAG));
1910 return DAG.getNOT(DL, Res, Res->getValueType(0));
1912 case Intrinsic::mips_or_v:
1913 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
1915 case Intrinsic::mips_ori_b:
1916 return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1917 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1918 case Intrinsic::mips_pckev_b:
1919 case Intrinsic::mips_pckev_h:
1920 case Intrinsic::mips_pckev_w:
1921 case Intrinsic::mips_pckev_d:
1922 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
1923 Op->getOperand(1), Op->getOperand(2));
1924 case Intrinsic::mips_pckod_b:
1925 case Intrinsic::mips_pckod_h:
1926 case Intrinsic::mips_pckod_w:
1927 case Intrinsic::mips_pckod_d:
1928 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
1929 Op->getOperand(1), Op->getOperand(2));
1930 case Intrinsic::mips_pcnt_b:
1931 case Intrinsic::mips_pcnt_h:
1932 case Intrinsic::mips_pcnt_w:
1933 case Intrinsic::mips_pcnt_d:
1934 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
1935 case Intrinsic::mips_shf_b:
1936 case Intrinsic::mips_shf_h:
1937 case Intrinsic::mips_shf_w:
1938 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
1939 Op->getOperand(2), Op->getOperand(1));
1940 case Intrinsic::mips_sll_b:
1941 case Intrinsic::mips_sll_h:
1942 case Intrinsic::mips_sll_w:
1943 case Intrinsic::mips_sll_d:
1944 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
1946 case Intrinsic::mips_slli_b:
1947 case Intrinsic::mips_slli_h:
1948 case Intrinsic::mips_slli_w:
1949 case Intrinsic::mips_slli_d:
1950 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
1951 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1952 case Intrinsic::mips_splat_b:
1953 case Intrinsic::mips_splat_h:
1954 case Intrinsic::mips_splat_w:
1955 case Intrinsic::mips_splat_d:
1956 // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
1957 // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
1958 // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32.
1959 // Instead we lower to MipsISD::VSHF and match from there.
1960 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1961 lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1),
1963 case Intrinsic::mips_splati_b:
1964 case Intrinsic::mips_splati_h:
1965 case Intrinsic::mips_splati_w:
1966 case Intrinsic::mips_splati_d:
1967 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1968 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
1970 case Intrinsic::mips_sra_b:
1971 case Intrinsic::mips_sra_h:
1972 case Intrinsic::mips_sra_w:
1973 case Intrinsic::mips_sra_d:
1974 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
1976 case Intrinsic::mips_srai_b:
1977 case Intrinsic::mips_srai_h:
1978 case Intrinsic::mips_srai_w:
1979 case Intrinsic::mips_srai_d:
1980 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
1981 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1982 case Intrinsic::mips_srl_b:
1983 case Intrinsic::mips_srl_h:
1984 case Intrinsic::mips_srl_w:
1985 case Intrinsic::mips_srl_d:
1986 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
1988 case Intrinsic::mips_srli_b:
1989 case Intrinsic::mips_srli_h:
1990 case Intrinsic::mips_srli_w:
1991 case Intrinsic::mips_srli_d:
1992 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
1993 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1994 case Intrinsic::mips_subv_b:
1995 case Intrinsic::mips_subv_h:
1996 case Intrinsic::mips_subv_w:
1997 case Intrinsic::mips_subv_d:
1998 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
2000 case Intrinsic::mips_subvi_b:
2001 case Intrinsic::mips_subvi_h:
2002 case Intrinsic::mips_subvi_w:
2003 case Intrinsic::mips_subvi_d:
2004 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
2005 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2006 case Intrinsic::mips_vshf_b:
2007 case Intrinsic::mips_vshf_h:
2008 case Intrinsic::mips_vshf_w:
2009 case Intrinsic::mips_vshf_d:
2010 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2011 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
2012 case Intrinsic::mips_xor_v:
2013 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
2015 case Intrinsic::mips_xori_b:
2016 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
2017 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2021 static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
2023 SDValue ChainIn = Op->getOperand(0);
2024 SDValue Address = Op->getOperand(2);
2025 SDValue Offset = Op->getOperand(3);
2026 EVT ResTy = Op->getValueType(0);
2027 EVT PtrTy = Address->getValueType(0);
2029 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2031 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
2035 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
2036 SelectionDAG &DAG) const {
2037 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2041 case Intrinsic::mips_extp:
2042 return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
2043 case Intrinsic::mips_extpdp:
2044 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
2045 case Intrinsic::mips_extr_w:
2046 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
2047 case Intrinsic::mips_extr_r_w:
2048 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
2049 case Intrinsic::mips_extr_rs_w:
2050 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
2051 case Intrinsic::mips_extr_s_h:
2052 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
2053 case Intrinsic::mips_mthlip:
2054 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
2055 case Intrinsic::mips_mulsaq_s_w_ph:
2056 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
2057 case Intrinsic::mips_maq_s_w_phl:
2058 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
2059 case Intrinsic::mips_maq_s_w_phr:
2060 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
2061 case Intrinsic::mips_maq_sa_w_phl:
2062 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
2063 case Intrinsic::mips_maq_sa_w_phr:
2064 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
2065 case Intrinsic::mips_dpaq_s_w_ph:
2066 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
2067 case Intrinsic::mips_dpsq_s_w_ph:
2068 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
2069 case Intrinsic::mips_dpaq_sa_l_w:
2070 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
2071 case Intrinsic::mips_dpsq_sa_l_w:
2072 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
2073 case Intrinsic::mips_dpaqx_s_w_ph:
2074 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
2075 case Intrinsic::mips_dpaqx_sa_w_ph:
2076 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
2077 case Intrinsic::mips_dpsqx_s_w_ph:
2078 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
2079 case Intrinsic::mips_dpsqx_sa_w_ph:
2080 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
2081 case Intrinsic::mips_ld_b:
2082 case Intrinsic::mips_ld_h:
2083 case Intrinsic::mips_ld_w:
2084 case Intrinsic::mips_ld_d:
2085 return lowerMSALoadIntr(Op, DAG, Intr);
2089 static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
2091 SDValue ChainIn = Op->getOperand(0);
2092 SDValue Value = Op->getOperand(2);
2093 SDValue Address = Op->getOperand(3);
2094 SDValue Offset = Op->getOperand(4);
2095 EVT PtrTy = Address->getValueType(0);
2097 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2099 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
2103 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
2104 SelectionDAG &DAG) const {
2105 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2109 case Intrinsic::mips_st_b:
2110 case Intrinsic::mips_st_h:
2111 case Intrinsic::mips_st_w:
2112 case Intrinsic::mips_st_d:
2113 return lowerMSAStoreIntr(Op, DAG, Intr);
2117 /// \brief Check if the given BuildVectorSDNode is a splat.
2118 /// This method currently relies on DAG nodes being reused when equivalent,
2119 /// so it's possible for this to return false even when isConstantSplat returns
2121 static bool isSplatVector(const BuildVectorSDNode *N) {
2122 unsigned int nOps = N->getNumOperands();
2123 assert(nOps > 1 && "isSplatVector has 0 or 1 sized build vector");
2125 SDValue Operand0 = N->getOperand(0);
2127 for (unsigned int i = 1; i < nOps; ++i) {
2128 if (N->getOperand(i) != Operand0)
2135 // Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
2137 // The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
2138 // choose to sign-extend but we could have equally chosen zero-extend. The
2139 // DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
2140 // result into this node later (possibly changing it to a zero-extend in the
2142 SDValue MipsSETargetLowering::
2143 lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
2145 EVT ResTy = Op->getValueType(0);
2146 SDValue Op0 = Op->getOperand(0);
2147 EVT VecTy = Op0->getValueType(0);
2149 if (!VecTy.is128BitVector())
2152 if (ResTy.isInteger()) {
2153 SDValue Op1 = Op->getOperand(1);
2154 EVT EltTy = VecTy.getVectorElementType();
2155 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
2156 DAG.getValueType(EltTy));
2162 static bool isConstantOrUndef(const SDValue Op) {
2163 if (Op->getOpcode() == ISD::UNDEF)
2165 if (dyn_cast<ConstantSDNode>(Op))
2167 if (dyn_cast<ConstantFPSDNode>(Op))
2172 static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) {
2173 for (unsigned i = 0; i < Op->getNumOperands(); ++i)
2174 if (isConstantOrUndef(Op->getOperand(i)))
2179 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
2182 // Lowers according to the following rules:
2183 // - Constant splats are legal as-is as long as the SplatBitSize is a power of
2184 // 2 less than or equal to 64 and the value fits into a signed 10-bit
2186 // - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
2187 // is a power of 2 less than or equal to 64 and the value does not fit into a
2188 // signed 10-bit immediate
2189 // - Non-constant splats are legal as-is.
2190 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
2191 // - All others are illegal and must be expanded.
2192 SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
2193 SelectionDAG &DAG) const {
2194 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
2195 EVT ResTy = Op->getValueType(0);
2197 APInt SplatValue, SplatUndef;
2198 unsigned SplatBitSize;
2201 if (!Subtarget->hasMSA() || !ResTy.is128BitVector())
2204 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2206 !Subtarget->isLittle()) && SplatBitSize <= 64) {
2207 // We can only cope with 8, 16, 32, or 64-bit elements
2208 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2212 // If the value fits into a simm10 then we can use ldi.[bhwd]
2213 // However, if it isn't an integer type we will have to bitcast from an
2214 // integer type first.
2215 if (ResTy.isInteger() && SplatValue.isSignedIntN(10))
2220 switch (SplatBitSize) {
2224 ViaVecTy = MVT::v16i8;
2227 ViaVecTy = MVT::v8i16;
2230 ViaVecTy = MVT::v4i32;
2233 // There's no fill.d to fall back on for 64-bit values
2237 // SelectionDAG::getConstant will promote SplatValue appropriately.
2238 SDValue Result = DAG.getConstant(SplatValue, ViaVecTy);
2240 // Bitcast to the type we originally wanted
2241 if (ViaVecTy != ResTy)
2242 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
2245 } else if (isSplatVector(Node))
2247 else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
2248 // Use INSERT_VECTOR_ELT operations rather than expand to stores.
2249 // The resulting code is the same length as the expansion, but it doesn't
2250 // use memory operations
2251 EVT ResTy = Node->getValueType(0);
2253 assert(ResTy.isVector());
2255 unsigned NumElts = ResTy.getVectorNumElements();
2256 SDValue Vector = DAG.getUNDEF(ResTy);
2257 for (unsigned i = 0; i < NumElts; ++i) {
2258 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2259 Node->getOperand(i),
2260 DAG.getConstant(i, MVT::i32));
2268 // Lower VECTOR_SHUFFLE into SHF (if possible).
2270 // SHF splits the vector into blocks of four elements, then shuffles these
2271 // elements according to a <4 x i2> constant (encoded as an integer immediate).
2273 // It is therefore possible to lower into SHF when the mask takes the form:
2274 // <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
2275 // When undef's appear they are treated as if they were whatever value is
2276 // necessary in order to fit the above form.
2279 // %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
2280 // <8 x i32> <i32 3, i32 2, i32 1, i32 0,
2281 // i32 7, i32 6, i32 5, i32 4>
2283 // (SHF_H $w0, $w1, 27)
2284 // where the 27 comes from:
2285 // 3 + (2 << 2) + (1 << 4) + (0 << 6)
2286 static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
2287 SmallVector<int, 16> Indices,
2288 SelectionDAG &DAG) {
2289 int SHFIndices[4] = { -1, -1, -1, -1 };
2291 if (Indices.size() < 4)
2294 for (unsigned i = 0; i < 4; ++i) {
2295 for (unsigned j = i; j < Indices.size(); j += 4) {
2296 int Idx = Indices[j];
2298 // Convert from vector index to 4-element subvector index
2299 // If an index refers to an element outside of the subvector then give up
2302 if (Idx < 0 || Idx >= 4)
2306 // If the mask has an undef, replace it with the current index.
2307 // Note that it might still be undef if the current index is also undef
2308 if (SHFIndices[i] == -1)
2309 SHFIndices[i] = Idx;
2311 // Check that non-undef values are the same as in the mask. If they
2312 // aren't then give up
2313 if (!(Idx == -1 || Idx == SHFIndices[i]))
2318 // Calculate the immediate. Replace any remaining undefs with zero
2320 for (int i = 3; i >= 0; --i) {
2321 int Idx = SHFIndices[i];
2330 return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy,
2331 DAG.getConstant(Imm, MVT::i32), Op->getOperand(0));
2334 // Lower VECTOR_SHUFFLE into ILVEV (if possible).
2336 // ILVEV interleaves the even elements from each vector.
2338 // It is possible to lower into ILVEV when the mask takes the form:
2339 // <0, n, 2, n+2, 4, n+4, ...>
2340 // where n is the number of elements in the vector.
2342 // When undef's appear in the mask they are treated as if they were whatever
2343 // value is necessary in order to fit the above form.
2344 static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy,
2345 SmallVector<int, 16> Indices,
2346 SelectionDAG &DAG) {
2347 assert ((Indices.size() % 2) == 0);
2349 int WtIdx = ResTy.getVectorNumElements();
2351 for (unsigned i = 0; i < Indices.size(); i += 2) {
2352 if (Indices[i] != -1 && Indices[i] != WsIdx)
2354 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2360 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Op->getOperand(0),
2364 // Lower VECTOR_SHUFFLE into ILVOD (if possible).
2366 // ILVOD interleaves the odd elements from each vector.
2368 // It is possible to lower into ILVOD when the mask takes the form:
2369 // <1, n+1, 3, n+3, 5, n+5, ...>
2370 // where n is the number of elements in the vector.
2372 // When undef's appear in the mask they are treated as if they were whatever
2373 // value is necessary in order to fit the above form.
2374 static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy,
2375 SmallVector<int, 16> Indices,
2376 SelectionDAG &DAG) {
2377 assert ((Indices.size() % 2) == 0);
2379 int WtIdx = ResTy.getVectorNumElements() + 1;
2381 for (unsigned i = 0; i < Indices.size(); i += 2) {
2382 if (Indices[i] != -1 && Indices[i] != WsIdx)
2384 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2390 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Op->getOperand(0),
2394 // Lower VECTOR_SHUFFLE into ILVL (if possible).
2396 // ILVL interleaves consecutive elements from the left half of each vector.
2398 // It is possible to lower into ILVL when the mask takes the form:
2399 // <0, n, 1, n+1, 2, n+2, ...>
2400 // where n is the number of elements in the vector.
2402 // When undef's appear in the mask they are treated as if they were whatever
2403 // value is necessary in order to fit the above form.
2404 static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy,
2405 SmallVector<int, 16> Indices,
2406 SelectionDAG &DAG) {
2407 assert ((Indices.size() % 2) == 0);
2409 int WtIdx = ResTy.getVectorNumElements();
2411 for (unsigned i = 0; i < Indices.size(); i += 2) {
2412 if (Indices[i] != -1 && Indices[i] != WsIdx)
2414 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2420 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Op->getOperand(0),
2424 // Lower VECTOR_SHUFFLE into ILVR (if possible).
2426 // ILVR interleaves consecutive elements from the right half of each vector.
2428 // It is possible to lower into ILVR when the mask takes the form:
2429 // <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2430 // where n is the number of elements in the vector and x is half n.
2432 // When undef's appear in the mask they are treated as if they were whatever
2433 // value is necessary in order to fit the above form.
2434 static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
2435 SmallVector<int, 16> Indices,
2436 SelectionDAG &DAG) {
2437 assert ((Indices.size() % 2) == 0);
2438 unsigned NumElts = ResTy.getVectorNumElements();
2439 int WsIdx = NumElts / 2;
2440 int WtIdx = NumElts + NumElts / 2;
2442 for (unsigned i = 0; i < Indices.size(); i += 2) {
2443 if (Indices[i] != -1 && Indices[i] != WsIdx)
2445 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2451 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Op->getOperand(0),
2455 // Lower VECTOR_SHUFFLE into PCKEV (if possible).
2457 // PCKEV copies the even elements of each vector into the result vector.
2459 // It is possible to lower into PCKEV when the mask takes the form:
2460 // <0, 2, 4, ..., n, n+2, n+4, ...>
2461 // where n is the number of elements in the vector.
2463 // When undef's appear in the mask they are treated as if they were whatever
2464 // value is necessary in order to fit the above form.
2465 static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy,
2466 SmallVector<int, 16> Indices,
2467 SelectionDAG &DAG) {
2468 assert ((Indices.size() % 2) == 0);
2471 for (unsigned i = 0; i < Indices.size(); ++i) {
2472 if (Indices[i] != -1 && Indices[i] != Idx)
2477 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Op->getOperand(0),
2481 // Lower VECTOR_SHUFFLE into PCKOD (if possible).
2483 // PCKOD copies the odd elements of each vector into the result vector.
2485 // It is possible to lower into PCKOD when the mask takes the form:
2486 // <1, 3, 5, ..., n+1, n+3, n+5, ...>
2487 // where n is the number of elements in the vector.
2489 // When undef's appear in the mask they are treated as if they were whatever
2490 // value is necessary in order to fit the above form.
2491 static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
2492 SmallVector<int, 16> Indices,
2493 SelectionDAG &DAG) {
2494 assert ((Indices.size() % 2) == 0);
2497 for (unsigned i = 0; i < Indices.size(); ++i) {
2498 if (Indices[i] != -1 && Indices[i] != Idx)
2503 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Op->getOperand(0),
2507 // Lower VECTOR_SHUFFLE into VSHF.
2509 // This mostly consists of converting the shuffle indices in Indices into a
2510 // BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2511 // also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2512 // if the type is v8i16 and all the indices are less than 8 then the second
2513 // operand is unused and can be replaced with anything. We choose to replace it
2514 // with the used operand since this reduces the number of instructions overall.
2515 static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
2516 SmallVector<int, 16> Indices,
2517 SelectionDAG &DAG) {
2518 SmallVector<SDValue, 16> Ops;
2521 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2522 EVT MaskEltTy = MaskVecTy.getVectorElementType();
2523 bool Using1stVec = false;
2524 bool Using2ndVec = false;
2526 int ResTyNumElts = ResTy.getVectorNumElements();
2528 for (int i = 0; i < ResTyNumElts; ++i) {
2529 // Idx == -1 means UNDEF
2530 int Idx = Indices[i];
2532 if (0 <= Idx && Idx < ResTyNumElts)
2534 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2538 for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2540 Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy));
2542 SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, &Ops[0],
2545 if (Using1stVec && Using2ndVec) {
2546 Op0 = Op->getOperand(0);
2547 Op1 = Op->getOperand(1);
2548 } else if (Using1stVec)
2549 Op0 = Op1 = Op->getOperand(0);
2550 else if (Using2ndVec)
2551 Op0 = Op1 = Op->getOperand(1);
2553 llvm_unreachable("shuffle vector mask references neither vector operand?");
2555 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op0, Op1);
2558 // Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2559 // indices in the shuffle.
2560 SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2561 SelectionDAG &DAG) const {
2562 ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2563 EVT ResTy = Op->getValueType(0);
2565 if (!ResTy.is128BitVector())
2568 int ResTyNumElts = ResTy.getVectorNumElements();
2569 SmallVector<int, 16> Indices;
2571 for (int i = 0; i < ResTyNumElts; ++i)
2572 Indices.push_back(Node->getMaskElt(i));
2574 SDValue Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG);
2575 if (Result.getNode())
2577 Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG);
2578 if (Result.getNode())
2580 Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG);
2581 if (Result.getNode())
2583 Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG);
2584 if (Result.getNode())
2586 Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG);
2587 if (Result.getNode())
2589 Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG);
2590 if (Result.getNode())
2592 Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG);
2593 if (Result.getNode())
2595 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2598 MachineBasicBlock * MipsSETargetLowering::
2599 emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
2601 // bposge32_pseudo $vr0
2611 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
2613 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2614 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2615 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2616 DebugLoc DL = MI->getDebugLoc();
2617 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2618 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
2619 MachineFunction *F = BB->getParent();
2620 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2621 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2622 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2625 F->insert(It, Sink);
2627 // Transfer the remainder of BB and its successor edges to Sink.
2628 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
2630 Sink->transferSuccessorsAndUpdatePHIs(BB);
2633 BB->addSuccessor(FBB);
2634 BB->addSuccessor(TBB);
2635 FBB->addSuccessor(Sink);
2636 TBB->addSuccessor(Sink);
2638 // Insert the real bposge32 instruction to $BB.
2639 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
2642 unsigned VR2 = RegInfo.createVirtualRegister(RC);
2643 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
2644 .addReg(Mips::ZERO).addImm(0);
2645 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2648 unsigned VR1 = RegInfo.createVirtualRegister(RC);
2649 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
2650 .addReg(Mips::ZERO).addImm(1);
2652 // Insert phi function to $Sink.
2653 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2654 MI->getOperand(0).getReg())
2655 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
2657 MI->eraseFromParent(); // The pseudo instruction is gone now.
2661 MachineBasicBlock * MipsSETargetLowering::
2662 emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
2663 unsigned BranchOp) const{
2665 // vany_nonzero $rd, $ws
2676 // $rd = phi($rd1, $fbb, $rd2, $tbb)
2678 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2679 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2680 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2681 DebugLoc DL = MI->getDebugLoc();
2682 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2683 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
2684 MachineFunction *F = BB->getParent();
2685 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2686 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2687 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2690 F->insert(It, Sink);
2692 // Transfer the remainder of BB and its successor edges to Sink.
2693 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
2695 Sink->transferSuccessorsAndUpdatePHIs(BB);
2698 BB->addSuccessor(FBB);
2699 BB->addSuccessor(TBB);
2700 FBB->addSuccessor(Sink);
2701 TBB->addSuccessor(Sink);
2703 // Insert the real bnz.b instruction to $BB.
2704 BuildMI(BB, DL, TII->get(BranchOp))
2705 .addReg(MI->getOperand(1).getReg())
2709 unsigned RD1 = RegInfo.createVirtualRegister(RC);
2710 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
2711 .addReg(Mips::ZERO).addImm(0);
2712 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2715 unsigned RD2 = RegInfo.createVirtualRegister(RC);
2716 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
2717 .addReg(Mips::ZERO).addImm(1);
2719 // Insert phi function to $Sink.
2720 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2721 MI->getOperand(0).getReg())
2722 .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
2724 MI->eraseFromParent(); // The pseudo instruction is gone now.
2728 // Emit the COPY_FW pseudo instruction.
2730 // copy_fw_pseudo $fd, $ws, n
2732 // copy_u_w $rt, $ws, $n
2735 // When n is zero, the equivalent operation can be performed with (potentially)
2736 // zero instructions due to register overlaps. This optimization is never valid
2737 // for lane 1 because it would require FR=0 mode which isn't supported by MSA.
2738 MachineBasicBlock * MipsSETargetLowering::
2739 emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{
2740 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2741 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2742 DebugLoc DL = MI->getDebugLoc();
2743 unsigned Fd = MI->getOperand(0).getReg();
2744 unsigned Ws = MI->getOperand(1).getReg();
2745 unsigned Lane = MI->getOperand(2).getImm();
2748 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo);
2750 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2752 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(1);
2753 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
2756 MI->eraseFromParent(); // The pseudo instruction is gone now.
2760 // Emit the COPY_FD pseudo instruction.
2762 // copy_fd_pseudo $fd, $ws, n
2764 // splati.d $wt, $ws, $n
2765 // copy $fd, $wt:sub_64
2767 // When n is zero, the equivalent operation can be performed with (potentially)
2768 // zero instructions due to register overlaps. This optimization is always
2769 // valid because FR=1 mode which is the only supported mode in MSA.
2770 MachineBasicBlock * MipsSETargetLowering::
2771 emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{
2772 assert(Subtarget->isFP64bit());
2774 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2775 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2776 unsigned Fd = MI->getOperand(0).getReg();
2777 unsigned Ws = MI->getOperand(1).getReg();
2778 unsigned Lane = MI->getOperand(2).getImm() * 2;
2779 DebugLoc DL = MI->getDebugLoc();
2782 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
2784 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2786 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
2787 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
2790 MI->eraseFromParent(); // The pseudo instruction is gone now.
2794 // Emit the INSERT_FW pseudo instruction.
2796 // insert_fw_pseudo $wd, $wd_in, $n, $fs
2798 // subreg_to_reg $wt:sub_lo, $fs
2799 // insve_w $wd[$n], $wd_in, $wt[0]
2801 MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI,
2802 MachineBasicBlock *BB) const {
2803 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2804 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2805 DebugLoc DL = MI->getDebugLoc();
2806 unsigned Wd = MI->getOperand(0).getReg();
2807 unsigned Wd_in = MI->getOperand(1).getReg();
2808 unsigned Lane = MI->getOperand(2).getImm();
2809 unsigned Fs = MI->getOperand(3).getReg();
2810 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2812 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2815 .addImm(Mips::sub_lo);
2816 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
2821 MI->eraseFromParent(); // The pseudo instruction is gone now.
2825 // Emit the INSERT_FD pseudo instruction.
2827 // insert_fd_pseudo $wd, $fs, n
2829 // subreg_to_reg $wt:sub_64, $fs
2830 // insve_d $wd[$n], $wd_in, $wt[0]
2832 MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI,
2833 MachineBasicBlock *BB) const {
2834 assert(Subtarget->isFP64bit());
2836 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2837 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2838 DebugLoc DL = MI->getDebugLoc();
2839 unsigned Wd = MI->getOperand(0).getReg();
2840 unsigned Wd_in = MI->getOperand(1).getReg();
2841 unsigned Lane = MI->getOperand(2).getImm();
2842 unsigned Fs = MI->getOperand(3).getReg();
2843 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2845 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2848 .addImm(Mips::sub_64);
2849 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
2854 MI->eraseFromParent(); // The pseudo instruction is gone now.
2858 // Emit the FILL_FW pseudo instruction.
2860 // fill_fw_pseudo $wd, $fs
2862 // implicit_def $wt1
2863 // insert_subreg $wt2:subreg_lo, $wt1, $fs
2864 // splati.w $wd, $wt2[0]
2866 MipsSETargetLowering::emitFILL_FW(MachineInstr *MI,
2867 MachineBasicBlock *BB) const {
2868 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2869 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2870 DebugLoc DL = MI->getDebugLoc();
2871 unsigned Wd = MI->getOperand(0).getReg();
2872 unsigned Fs = MI->getOperand(1).getReg();
2873 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2874 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2876 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
2877 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
2880 .addImm(Mips::sub_lo);
2881 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
2883 MI->eraseFromParent(); // The pseudo instruction is gone now.
2887 // Emit the FILL_FD pseudo instruction.
2889 // fill_fd_pseudo $wd, $fs
2891 // implicit_def $wt1
2892 // insert_subreg $wt2:subreg_64, $wt1, $fs
2893 // splati.d $wd, $wt2[0]
2895 MipsSETargetLowering::emitFILL_FD(MachineInstr *MI,
2896 MachineBasicBlock *BB) const {
2897 assert(Subtarget->isFP64bit());
2899 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2900 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2901 DebugLoc DL = MI->getDebugLoc();
2902 unsigned Wd = MI->getOperand(0).getReg();
2903 unsigned Fs = MI->getOperand(1).getReg();
2904 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2905 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2907 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
2908 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
2911 .addImm(Mips::sub_64);
2912 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
2914 MI->eraseFromParent(); // The pseudo instruction is gone now.
2918 // Emit the FEXP2_W_1 pseudo instructions.
2920 // fexp2_w_1_pseudo $wd, $wt
2923 // fexp2.w $wd, $ws, $wt
2925 MipsSETargetLowering::emitFEXP2_W_1(MachineInstr *MI,
2926 MachineBasicBlock *BB) const {
2927 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2928 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2929 const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
2930 unsigned Ws1 = RegInfo.createVirtualRegister(RC);
2931 unsigned Ws2 = RegInfo.createVirtualRegister(RC);
2932 DebugLoc DL = MI->getDebugLoc();
2934 // Splat 1.0 into a vector
2935 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
2936 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
2938 // Emit 1.0 * fexp2(Wt)
2939 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI->getOperand(0).getReg())
2941 .addReg(MI->getOperand(1).getReg());
2943 MI->eraseFromParent(); // The pseudo instruction is gone now.
2947 // Emit the FEXP2_D_1 pseudo instructions.
2949 // fexp2_d_1_pseudo $wd, $wt
2952 // fexp2.d $wd, $ws, $wt
2954 MipsSETargetLowering::emitFEXP2_D_1(MachineInstr *MI,
2955 MachineBasicBlock *BB) const {
2956 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2957 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2958 const TargetRegisterClass *RC = &Mips::MSA128DRegClass;
2959 unsigned Ws1 = RegInfo.createVirtualRegister(RC);
2960 unsigned Ws2 = RegInfo.createVirtualRegister(RC);
2961 DebugLoc DL = MI->getDebugLoc();
2963 // Splat 1.0 into a vector
2964 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
2965 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
2967 // Emit 1.0 * fexp2(Wt)
2968 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI->getOperand(0).getReg())
2970 .addReg(MI->getOperand(1).getReg());
2972 MI->eraseFromParent(); // The pseudo instruction is gone now.