1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
13 #include "MipsSEISelLowering.h"
14 #include "MipsRegisterInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/IR/Intrinsics.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Target/TargetInstrInfo.h"
25 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
26 cl::desc("MIPS: Enable tail calls."), cl::init(false));
28 MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
29 : MipsTargetLowering(TM) {
30 // Set up the register classes
32 clearRegisterClasses();
34 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
37 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
39 if (Subtarget->hasDSP()) {
40 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
42 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
43 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
45 // Expand all builtin opcodes.
46 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
47 setOperationAction(Opc, VecTys[i], Expand);
49 setOperationAction(ISD::ADD, VecTys[i], Legal);
50 setOperationAction(ISD::SUB, VecTys[i], Legal);
51 setOperationAction(ISD::LOAD, VecTys[i], Legal);
52 setOperationAction(ISD::STORE, VecTys[i], Legal);
53 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
56 // Expand all truncating stores and extending loads.
57 unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
58 unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
60 for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
61 for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
62 setTruncStoreAction((MVT::SimpleValueType)VT0,
63 (MVT::SimpleValueType)VT1, Expand);
65 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
66 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
67 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
70 setTargetDAGCombine(ISD::SHL);
71 setTargetDAGCombine(ISD::SRA);
72 setTargetDAGCombine(ISD::SRL);
73 setTargetDAGCombine(ISD::SETCC);
74 setTargetDAGCombine(ISD::VSELECT);
77 if (Subtarget->hasDSPR2())
78 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
80 if (Subtarget->hasMSA()) {
81 MVT::SimpleValueType VecTys[4] = {MVT::v16i8, MVT::v8i16,
82 MVT::v4i32, MVT::v2i64};
84 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
85 addRegisterClass(VecTys[i], &Mips::MSA128RegClass);
87 // Expand all builtin opcodes.
88 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
89 setOperationAction(Opc, VecTys[i], Expand);
91 setOperationAction(ISD::LOAD, VecTys[i], Legal);
92 setOperationAction(ISD::STORE, VecTys[i], Legal);
93 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
97 if (!TM.Options.UseSoftFloat) {
98 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
100 // When dealing with single precision only, use libcalls
101 if (!Subtarget->isSingleFloat()) {
103 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
105 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
109 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
110 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
111 setOperationAction(ISD::MULHS, MVT::i32, Custom);
112 setOperationAction(ISD::MULHU, MVT::i32, Custom);
115 setOperationAction(ISD::MULHS, MVT::i64, Custom);
116 setOperationAction(ISD::MULHU, MVT::i64, Custom);
117 setOperationAction(ISD::MUL, MVT::i64, Custom);
120 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
121 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
123 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
124 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
125 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
126 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
127 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
128 setOperationAction(ISD::LOAD, MVT::i32, Custom);
129 setOperationAction(ISD::STORE, MVT::i32, Custom);
131 setTargetDAGCombine(ISD::ADDE);
132 setTargetDAGCombine(ISD::SUBE);
133 setTargetDAGCombine(ISD::MUL);
135 computeRegisterProperties();
138 const MipsTargetLowering *
139 llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
140 return new MipsSETargetLowering(TM);
145 MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
146 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
159 SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
160 SelectionDAG &DAG) const {
161 switch(Op.getOpcode()) {
162 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
163 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
164 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
165 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
166 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
167 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
168 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
170 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
171 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
174 return MipsTargetLowering::LowerOperation(Op, DAG);
178 // Transforms a subgraph in CurDAG if the following pattern is found:
179 // (addc multLo, Lo0), (adde multHi, Hi0),
181 // multHi/Lo: product of multiplication
182 // Lo0: initial value of Lo register
183 // Hi0: initial value of Hi register
184 // Return true if pattern matching was successful.
185 static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
186 // ADDENode's second operand must be a flag output of an ADDC node in order
187 // for the matching to be successful.
188 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
190 if (ADDCNode->getOpcode() != ISD::ADDC)
193 SDValue MultHi = ADDENode->getOperand(0);
194 SDValue MultLo = ADDCNode->getOperand(0);
195 SDNode *MultNode = MultHi.getNode();
196 unsigned MultOpc = MultHi.getOpcode();
198 // MultHi and MultLo must be generated by the same node,
199 if (MultLo.getNode() != MultNode)
202 // and it must be a multiplication.
203 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
206 // MultLo amd MultHi must be the first and second output of MultNode
208 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
211 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
212 // of the values of MultNode, in which case MultNode will be removed in later
214 // If there exist users other than ADDENode or ADDCNode, this function returns
215 // here, which will result in MultNode being mapped to a single MULT
216 // instruction node rather than a pair of MULT and MADD instructions being
218 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
223 // Initialize accumulator.
224 SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
225 ADDCNode->getOperand(1),
226 ADDENode->getOperand(1));
228 // create MipsMAdd(u) node
229 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
231 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
232 MultNode->getOperand(0),// Factor 0
233 MultNode->getOperand(1),// Factor 1
236 // replace uses of adde and addc here
237 if (!SDValue(ADDCNode, 0).use_empty()) {
238 SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
239 SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
241 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
243 if (!SDValue(ADDENode, 0).use_empty()) {
244 SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
245 SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
247 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
254 // Transforms a subgraph in CurDAG if the following pattern is found:
255 // (addc Lo0, multLo), (sube Hi0, multHi),
257 // multHi/Lo: product of multiplication
258 // Lo0: initial value of Lo register
259 // Hi0: initial value of Hi register
260 // Return true if pattern matching was successful.
261 static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
262 // SUBENode's second operand must be a flag output of an SUBC node in order
263 // for the matching to be successful.
264 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
266 if (SUBCNode->getOpcode() != ISD::SUBC)
269 SDValue MultHi = SUBENode->getOperand(1);
270 SDValue MultLo = SUBCNode->getOperand(1);
271 SDNode *MultNode = MultHi.getNode();
272 unsigned MultOpc = MultHi.getOpcode();
274 // MultHi and MultLo must be generated by the same node,
275 if (MultLo.getNode() != MultNode)
278 // and it must be a multiplication.
279 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
282 // MultLo amd MultHi must be the first and second output of MultNode
284 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
287 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
288 // of the values of MultNode, in which case MultNode will be removed in later
290 // If there exist users other than SUBENode or SUBCNode, this function returns
291 // here, which will result in MultNode being mapped to a single MULT
292 // instruction node rather than a pair of MULT and MSUB instructions being
294 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
299 // Initialize accumulator.
300 SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
301 SUBCNode->getOperand(0),
302 SUBENode->getOperand(0));
304 // create MipsSub(u) node
305 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
307 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
308 MultNode->getOperand(0),// Factor 0
309 MultNode->getOperand(1),// Factor 1
312 // replace uses of sube and subc here
313 if (!SDValue(SUBCNode, 0).use_empty()) {
314 SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
315 SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
317 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
319 if (!SDValue(SUBENode, 0).use_empty()) {
320 SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
321 SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
323 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
329 static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
330 TargetLowering::DAGCombinerInfo &DCI,
331 const MipsSubtarget *Subtarget) {
332 if (DCI.isBeforeLegalize())
335 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
337 return SDValue(N, 0);
342 static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
343 TargetLowering::DAGCombinerInfo &DCI,
344 const MipsSubtarget *Subtarget) {
345 if (DCI.isBeforeLegalize())
348 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
350 return SDValue(N, 0);
355 static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
356 EVT ShiftTy, SelectionDAG &DAG) {
357 // Clear the upper (64 - VT.sizeInBits) bits.
358 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
362 return DAG.getConstant(0, VT);
368 // If c is power of 2, return (shl x, log2(c)).
369 if (isPowerOf2_64(C))
370 return DAG.getNode(ISD::SHL, DL, VT, X,
371 DAG.getConstant(Log2_64(C), ShiftTy));
373 unsigned Log2Ceil = Log2_64_Ceil(C);
374 uint64_t Floor = 1LL << Log2_64(C);
375 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
377 // If |c - floor_c| <= |c - ceil_c|,
378 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
379 // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
380 if (C - Floor <= Ceil - C) {
381 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
382 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
383 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
386 // If |c - floor_c| > |c - ceil_c|,
387 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
388 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
389 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
390 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
393 static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
394 const TargetLowering::DAGCombinerInfo &DCI,
395 const MipsSETargetLowering *TL) {
396 EVT VT = N->getValueType(0);
398 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
400 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
401 VT, TL->getScalarShiftAmountTy(VT), DAG);
403 return SDValue(N, 0);
406 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
408 const MipsSubtarget *Subtarget) {
409 // See if this is a vector splat immediate node.
410 APInt SplatValue, SplatUndef;
411 unsigned SplatBitSize;
413 unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
414 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
417 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
418 EltSize, !Subtarget->isLittle()) ||
419 (SplatBitSize != EltSize) ||
420 (SplatValue.getZExtValue() >= EltSize))
423 return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
424 DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
427 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
428 TargetLowering::DAGCombinerInfo &DCI,
429 const MipsSubtarget *Subtarget) {
430 EVT Ty = N->getValueType(0);
432 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
435 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
438 static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
439 TargetLowering::DAGCombinerInfo &DCI,
440 const MipsSubtarget *Subtarget) {
441 EVT Ty = N->getValueType(0);
443 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
446 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
450 static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
451 TargetLowering::DAGCombinerInfo &DCI,
452 const MipsSubtarget *Subtarget) {
453 EVT Ty = N->getValueType(0);
455 if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
458 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
461 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
462 bool IsV216 = (Ty == MVT::v2i16);
466 case ISD::SETNE: return true;
470 case ISD::SETGE: return IsV216;
474 case ISD::SETUGE: return !IsV216;
475 default: return false;
479 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
480 EVT Ty = N->getValueType(0);
482 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
485 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
488 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
489 N->getOperand(1), N->getOperand(2));
492 static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
493 EVT Ty = N->getValueType(0);
495 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
498 SDValue SetCC = N->getOperand(0);
500 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
503 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
504 SetCC.getOperand(0), SetCC.getOperand(1), N->getOperand(1),
505 N->getOperand(2), SetCC.getOperand(2));
509 MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
510 SelectionDAG &DAG = DCI.DAG;
513 switch (N->getOpcode()) {
515 return performADDECombine(N, DAG, DCI, Subtarget);
517 return performSUBECombine(N, DAG, DCI, Subtarget);
519 return performMULCombine(N, DAG, DCI, this);
521 return performSHLCombine(N, DAG, DCI, Subtarget);
523 return performSRACombine(N, DAG, DCI, Subtarget);
525 return performSRLCombine(N, DAG, DCI, Subtarget);
527 return performVSELECTCombine(N, DAG);
529 Val = performSETCCCombine(N, DAG);
537 return MipsTargetLowering::PerformDAGCombine(N, DCI);
541 MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
542 MachineBasicBlock *BB) const {
543 switch (MI->getOpcode()) {
545 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
546 case Mips::BPOSGE32_PSEUDO:
547 return emitBPOSGE32(MI, BB);
551 bool MipsSETargetLowering::
552 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
553 unsigned NextStackOffset,
554 const MipsFunctionInfo& FI) const {
555 if (!EnableMipsTailCalls)
558 // Return false if either the callee or caller has a byval argument.
559 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
562 // Return true if the callee's argument area is no larger than the
564 return NextStackOffset <= FI.getIncomingArgSize();
567 void MipsSETargetLowering::
568 getOpndList(SmallVectorImpl<SDValue> &Ops,
569 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
570 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
571 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
572 // T9 should contain the address of the callee function if
573 // -reloction-model=pic or it is an indirect call.
574 if (IsPICCall || !GlobalOrExternal) {
575 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
576 RegsToPass.push_front(std::make_pair(T9Reg, Callee));
578 Ops.push_back(Callee);
580 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
581 InternalLinkage, CLI, Callee, Chain);
584 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
585 bool HasLo, bool HasHi,
586 SelectionDAG &DAG) const {
587 EVT Ty = Op.getOperand(0).getValueType();
589 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
590 Op.getOperand(0), Op.getOperand(1));
594 Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
595 DAG.getConstant(Mips::sub_lo, MVT::i32));
597 Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
598 DAG.getConstant(Mips::sub_hi, MVT::i32));
600 if (!HasLo || !HasHi)
601 return HasLo ? Lo : Hi;
603 SDValue Vals[] = { Lo, Hi };
604 return DAG.getMergeValues(Vals, 2, DL);
608 static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
609 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
610 DAG.getConstant(0, MVT::i32));
611 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
612 DAG.getConstant(1, MVT::i32));
613 return DAG.getNode(MipsISD::InsertLOHI, DL, MVT::Untyped, InLo, InHi);
616 static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
617 SDValue Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
618 DAG.getConstant(Mips::sub_lo, MVT::i32));
619 SDValue Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
620 DAG.getConstant(Mips::sub_hi, MVT::i32));
621 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
624 // This function expands mips intrinsic nodes which have 64-bit input operands
627 // out64 = intrinsic-node in64
629 // lo = copy (extract-element (in64, 0))
630 // hi = copy (extract-element (in64, 1))
631 // mips-specific-node
634 // out64 = merge-values (v0, v1)
636 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
638 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
639 SmallVector<SDValue, 3> Ops;
642 // See if Op has a chain input.
644 Ops.push_back(Op->getOperand(OpNo++));
646 // The next operand is the intrinsic opcode.
647 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
649 // See if the next operand has type i64.
650 SDValue Opnd = Op->getOperand(++OpNo), In64;
652 if (Opnd.getValueType() == MVT::i64)
653 In64 = initAccumulator(Opnd, DL, DAG);
657 // Push the remaining operands.
658 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
659 Ops.push_back(Op->getOperand(OpNo));
661 // Add In64 to the end of the list.
666 SmallVector<EVT, 2> ResTys;
668 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
670 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
673 SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
674 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
679 assert(Val->getValueType(1) == MVT::Other);
680 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
681 return DAG.getMergeValues(Vals, 2, DL);
684 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
685 SelectionDAG &DAG) const {
686 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
689 case Intrinsic::mips_shilo:
690 return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
691 case Intrinsic::mips_dpau_h_qbl:
692 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
693 case Intrinsic::mips_dpau_h_qbr:
694 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
695 case Intrinsic::mips_dpsu_h_qbl:
696 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
697 case Intrinsic::mips_dpsu_h_qbr:
698 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
699 case Intrinsic::mips_dpa_w_ph:
700 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
701 case Intrinsic::mips_dps_w_ph:
702 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
703 case Intrinsic::mips_dpax_w_ph:
704 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
705 case Intrinsic::mips_dpsx_w_ph:
706 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
707 case Intrinsic::mips_mulsa_w_ph:
708 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
709 case Intrinsic::mips_mult:
710 return lowerDSPIntr(Op, DAG, MipsISD::Mult);
711 case Intrinsic::mips_multu:
712 return lowerDSPIntr(Op, DAG, MipsISD::Multu);
713 case Intrinsic::mips_madd:
714 return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
715 case Intrinsic::mips_maddu:
716 return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
717 case Intrinsic::mips_msub:
718 return lowerDSPIntr(Op, DAG, MipsISD::MSub);
719 case Intrinsic::mips_msubu:
720 return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
724 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
725 SelectionDAG &DAG) const {
726 switch (cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue()) {
729 case Intrinsic::mips_extp:
730 return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
731 case Intrinsic::mips_extpdp:
732 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
733 case Intrinsic::mips_extr_w:
734 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
735 case Intrinsic::mips_extr_r_w:
736 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
737 case Intrinsic::mips_extr_rs_w:
738 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
739 case Intrinsic::mips_extr_s_h:
740 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
741 case Intrinsic::mips_mthlip:
742 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
743 case Intrinsic::mips_mulsaq_s_w_ph:
744 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
745 case Intrinsic::mips_maq_s_w_phl:
746 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
747 case Intrinsic::mips_maq_s_w_phr:
748 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
749 case Intrinsic::mips_maq_sa_w_phl:
750 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
751 case Intrinsic::mips_maq_sa_w_phr:
752 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
753 case Intrinsic::mips_dpaq_s_w_ph:
754 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
755 case Intrinsic::mips_dpsq_s_w_ph:
756 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
757 case Intrinsic::mips_dpaq_sa_l_w:
758 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
759 case Intrinsic::mips_dpsq_sa_l_w:
760 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
761 case Intrinsic::mips_dpaqx_s_w_ph:
762 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
763 case Intrinsic::mips_dpaqx_sa_w_ph:
764 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
765 case Intrinsic::mips_dpsqx_s_w_ph:
766 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
767 case Intrinsic::mips_dpsqx_sa_w_ph:
768 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
772 MachineBasicBlock * MipsSETargetLowering::
773 emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
775 // bposge32_pseudo $vr0
785 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
787 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
788 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
789 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
790 DebugLoc DL = MI->getDebugLoc();
791 const BasicBlock *LLVM_BB = BB->getBasicBlock();
792 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
793 MachineFunction *F = BB->getParent();
794 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
795 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
796 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
801 // Transfer the remainder of BB and its successor edges to Sink.
802 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
804 Sink->transferSuccessorsAndUpdatePHIs(BB);
807 BB->addSuccessor(FBB);
808 BB->addSuccessor(TBB);
809 FBB->addSuccessor(Sink);
810 TBB->addSuccessor(Sink);
812 // Insert the real bposge32 instruction to $BB.
813 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
816 unsigned VR2 = RegInfo.createVirtualRegister(RC);
817 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
818 .addReg(Mips::ZERO).addImm(0);
819 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
822 unsigned VR1 = RegInfo.createVirtualRegister(RC);
823 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
824 .addReg(Mips::ZERO).addImm(1);
826 // Insert phi function to $Sink.
827 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
828 MI->getOperand(0).getReg())
829 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
831 MI->eraseFromParent(); // The pseudo instruction is gone now.