1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
13 #define DEBUG_TYPE "mips-isel"
14 #include "MipsSEISelLowering.h"
15 #include "MipsRegisterInfo.h"
16 #include "MipsTargetMachine.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/IR/Intrinsics.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/Target/TargetInstrInfo.h"
28 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
29 cl::desc("MIPS: Enable tail calls."), cl::init(false));
31 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
32 cl::desc("Expand double precision loads and "
33 "stores to their single precision "
36 MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
37 : MipsTargetLowering(TM) {
38 // Set up the register classes
39 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
42 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
44 if (Subtarget->hasDSP() || Subtarget->hasMSA()) {
45 // Expand all truncating stores and extending loads.
46 unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
47 unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
49 for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
50 for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
51 setTruncStoreAction((MVT::SimpleValueType)VT0,
52 (MVT::SimpleValueType)VT1, Expand);
54 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
55 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
56 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
60 if (Subtarget->hasDSP()) {
61 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
63 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
64 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
66 // Expand all builtin opcodes.
67 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
68 setOperationAction(Opc, VecTys[i], Expand);
70 setOperationAction(ISD::ADD, VecTys[i], Legal);
71 setOperationAction(ISD::SUB, VecTys[i], Legal);
72 setOperationAction(ISD::LOAD, VecTys[i], Legal);
73 setOperationAction(ISD::STORE, VecTys[i], Legal);
74 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
77 setTargetDAGCombine(ISD::SHL);
78 setTargetDAGCombine(ISD::SRA);
79 setTargetDAGCombine(ISD::SRL);
80 setTargetDAGCombine(ISD::SETCC);
81 setTargetDAGCombine(ISD::VSELECT);
84 if (Subtarget->hasDSPR2())
85 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
87 if (Subtarget->hasMSA()) {
88 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
89 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
90 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
91 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
92 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
93 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
94 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
96 setTargetDAGCombine(ISD::AND);
97 setTargetDAGCombine(ISD::OR);
98 setTargetDAGCombine(ISD::SRA);
99 setTargetDAGCombine(ISD::VSELECT);
100 setTargetDAGCombine(ISD::XOR);
103 if (!Subtarget->mipsSEUsesSoftFloat()) {
104 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
106 // When dealing with single precision only, use libcalls
107 if (!Subtarget->isSingleFloat()) {
108 if (Subtarget->isFP64bit())
109 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
111 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
115 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
116 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
117 setOperationAction(ISD::MULHS, MVT::i32, Custom);
118 setOperationAction(ISD::MULHU, MVT::i32, Custom);
121 setOperationAction(ISD::MULHS, MVT::i64, Custom);
122 setOperationAction(ISD::MULHU, MVT::i64, Custom);
123 setOperationAction(ISD::MUL, MVT::i64, Custom);
126 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
127 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
129 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
130 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
131 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
132 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
133 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
134 setOperationAction(ISD::LOAD, MVT::i32, Custom);
135 setOperationAction(ISD::STORE, MVT::i32, Custom);
137 setTargetDAGCombine(ISD::ADDE);
138 setTargetDAGCombine(ISD::SUBE);
139 setTargetDAGCombine(ISD::MUL);
141 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
142 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
143 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
146 setOperationAction(ISD::LOAD, MVT::f64, Custom);
147 setOperationAction(ISD::STORE, MVT::f64, Custom);
150 computeRegisterProperties();
153 const MipsTargetLowering *
154 llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
155 return new MipsSETargetLowering(TM);
158 // Enable MSA support for the given integer type and Register class.
159 void MipsSETargetLowering::
160 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
161 addRegisterClass(Ty, RC);
163 // Expand all builtin opcodes.
164 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
165 setOperationAction(Opc, Ty, Expand);
167 setOperationAction(ISD::BITCAST, Ty, Legal);
168 setOperationAction(ISD::LOAD, Ty, Legal);
169 setOperationAction(ISD::STORE, Ty, Legal);
170 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
171 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
172 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
174 setOperationAction(ISD::ADD, Ty, Legal);
175 setOperationAction(ISD::AND, Ty, Legal);
176 setOperationAction(ISD::CTLZ, Ty, Legal);
177 setOperationAction(ISD::CTPOP, Ty, Legal);
178 setOperationAction(ISD::MUL, Ty, Legal);
179 setOperationAction(ISD::OR, Ty, Legal);
180 setOperationAction(ISD::SDIV, Ty, Legal);
181 setOperationAction(ISD::SREM, Ty, Legal);
182 setOperationAction(ISD::SHL, Ty, Legal);
183 setOperationAction(ISD::SRA, Ty, Legal);
184 setOperationAction(ISD::SRL, Ty, Legal);
185 setOperationAction(ISD::SUB, Ty, Legal);
186 setOperationAction(ISD::UDIV, Ty, Legal);
187 setOperationAction(ISD::UREM, Ty, Legal);
188 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
189 setOperationAction(ISD::VSELECT, Ty, Legal);
190 setOperationAction(ISD::XOR, Ty, Legal);
192 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
193 setOperationAction(ISD::FP_TO_SINT, Ty, Legal);
194 setOperationAction(ISD::FP_TO_UINT, Ty, Legal);
195 setOperationAction(ISD::SINT_TO_FP, Ty, Legal);
196 setOperationAction(ISD::UINT_TO_FP, Ty, Legal);
199 setOperationAction(ISD::SETCC, Ty, Legal);
200 setCondCodeAction(ISD::SETNE, Ty, Expand);
201 setCondCodeAction(ISD::SETGE, Ty, Expand);
202 setCondCodeAction(ISD::SETGT, Ty, Expand);
203 setCondCodeAction(ISD::SETUGE, Ty, Expand);
204 setCondCodeAction(ISD::SETUGT, Ty, Expand);
207 // Enable MSA support for the given floating-point type and Register class.
208 void MipsSETargetLowering::
209 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
210 addRegisterClass(Ty, RC);
212 // Expand all builtin opcodes.
213 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
214 setOperationAction(Opc, Ty, Expand);
216 setOperationAction(ISD::LOAD, Ty, Legal);
217 setOperationAction(ISD::STORE, Ty, Legal);
218 setOperationAction(ISD::BITCAST, Ty, Legal);
219 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
220 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
221 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
223 if (Ty != MVT::v8f16) {
224 setOperationAction(ISD::FABS, Ty, Legal);
225 setOperationAction(ISD::FADD, Ty, Legal);
226 setOperationAction(ISD::FDIV, Ty, Legal);
227 setOperationAction(ISD::FEXP2, Ty, Legal);
228 setOperationAction(ISD::FLOG2, Ty, Legal);
229 setOperationAction(ISD::FMA, Ty, Legal);
230 setOperationAction(ISD::FMUL, Ty, Legal);
231 setOperationAction(ISD::FRINT, Ty, Legal);
232 setOperationAction(ISD::FSQRT, Ty, Legal);
233 setOperationAction(ISD::FSUB, Ty, Legal);
234 setOperationAction(ISD::VSELECT, Ty, Legal);
236 setOperationAction(ISD::SETCC, Ty, Legal);
237 setCondCodeAction(ISD::SETOGE, Ty, Expand);
238 setCondCodeAction(ISD::SETOGT, Ty, Expand);
239 setCondCodeAction(ISD::SETUGE, Ty, Expand);
240 setCondCodeAction(ISD::SETUGT, Ty, Expand);
241 setCondCodeAction(ISD::SETGE, Ty, Expand);
242 setCondCodeAction(ISD::SETGT, Ty, Expand);
247 MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
250 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
263 SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
264 SelectionDAG &DAG) const {
265 switch(Op.getOpcode()) {
266 case ISD::LOAD: return lowerLOAD(Op, DAG);
267 case ISD::STORE: return lowerSTORE(Op, DAG);
268 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
269 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
270 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
271 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
272 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
273 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
274 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
276 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
277 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
278 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
279 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
280 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
281 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
284 return MipsTargetLowering::LowerOperation(Op, DAG);
288 // Transforms a subgraph in CurDAG if the following pattern is found:
289 // (addc multLo, Lo0), (adde multHi, Hi0),
291 // multHi/Lo: product of multiplication
292 // Lo0: initial value of Lo register
293 // Hi0: initial value of Hi register
294 // Return true if pattern matching was successful.
295 static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
296 // ADDENode's second operand must be a flag output of an ADDC node in order
297 // for the matching to be successful.
298 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
300 if (ADDCNode->getOpcode() != ISD::ADDC)
303 SDValue MultHi = ADDENode->getOperand(0);
304 SDValue MultLo = ADDCNode->getOperand(0);
305 SDNode *MultNode = MultHi.getNode();
306 unsigned MultOpc = MultHi.getOpcode();
308 // MultHi and MultLo must be generated by the same node,
309 if (MultLo.getNode() != MultNode)
312 // and it must be a multiplication.
313 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
316 // MultLo amd MultHi must be the first and second output of MultNode
318 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
321 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
322 // of the values of MultNode, in which case MultNode will be removed in later
324 // If there exist users other than ADDENode or ADDCNode, this function returns
325 // here, which will result in MultNode being mapped to a single MULT
326 // instruction node rather than a pair of MULT and MADD instructions being
328 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
333 // Initialize accumulator.
334 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
335 ADDCNode->getOperand(1),
336 ADDENode->getOperand(1));
338 // create MipsMAdd(u) node
339 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
341 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
342 MultNode->getOperand(0),// Factor 0
343 MultNode->getOperand(1),// Factor 1
346 // replace uses of adde and addc here
347 if (!SDValue(ADDCNode, 0).use_empty()) {
348 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
349 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
351 if (!SDValue(ADDENode, 0).use_empty()) {
352 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
353 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
360 // Transforms a subgraph in CurDAG if the following pattern is found:
361 // (addc Lo0, multLo), (sube Hi0, multHi),
363 // multHi/Lo: product of multiplication
364 // Lo0: initial value of Lo register
365 // Hi0: initial value of Hi register
366 // Return true if pattern matching was successful.
367 static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
368 // SUBENode's second operand must be a flag output of an SUBC node in order
369 // for the matching to be successful.
370 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
372 if (SUBCNode->getOpcode() != ISD::SUBC)
375 SDValue MultHi = SUBENode->getOperand(1);
376 SDValue MultLo = SUBCNode->getOperand(1);
377 SDNode *MultNode = MultHi.getNode();
378 unsigned MultOpc = MultHi.getOpcode();
380 // MultHi and MultLo must be generated by the same node,
381 if (MultLo.getNode() != MultNode)
384 // and it must be a multiplication.
385 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
388 // MultLo amd MultHi must be the first and second output of MultNode
390 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
393 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
394 // of the values of MultNode, in which case MultNode will be removed in later
396 // If there exist users other than SUBENode or SUBCNode, this function returns
397 // here, which will result in MultNode being mapped to a single MULT
398 // instruction node rather than a pair of MULT and MSUB instructions being
400 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
405 // Initialize accumulator.
406 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
407 SUBCNode->getOperand(0),
408 SUBENode->getOperand(0));
410 // create MipsSub(u) node
411 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
413 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
414 MultNode->getOperand(0),// Factor 0
415 MultNode->getOperand(1),// Factor 1
418 // replace uses of sube and subc here
419 if (!SDValue(SUBCNode, 0).use_empty()) {
420 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub);
421 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
423 if (!SDValue(SUBENode, 0).use_empty()) {
424 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub);
425 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
431 static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
432 TargetLowering::DAGCombinerInfo &DCI,
433 const MipsSubtarget *Subtarget) {
434 if (DCI.isBeforeLegalize())
437 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
439 return SDValue(N, 0);
444 // Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
446 // Performs the following transformations:
447 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
448 // sign/zero-extension is completely overwritten by the new one performed by
450 // - Removes redundant zero extensions performed by an ISD::AND.
451 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
452 TargetLowering::DAGCombinerInfo &DCI,
453 const MipsSubtarget *Subtarget) {
454 if (!Subtarget->hasMSA())
457 SDValue Op0 = N->getOperand(0);
458 SDValue Op1 = N->getOperand(1);
459 unsigned Op0Opcode = Op0->getOpcode();
461 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
462 // where $d + 1 == 2^n and n == 32
463 // or $d + 1 == 2^n and n <= 32 and ZExt
464 // -> (MipsVExtractZExt $a, $b, $c)
465 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
466 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
467 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
472 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
474 if (Log2IfPositive <= 0)
475 return SDValue(); // Mask+1 is not a power of 2
477 SDValue Op0Op2 = Op0->getOperand(2);
478 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
479 unsigned ExtendTySize = ExtendTy.getSizeInBits();
480 unsigned Log2 = Log2IfPositive;
482 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
483 Log2 == ExtendTySize) {
484 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
485 DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT,
486 Op0->getVTList(), Ops, Op0->getNumOperands());
494 // Determine if the specified node is a constant vector splat.
496 // Returns true and sets Imm if:
497 // * N is a ISD::BUILD_VECTOR representing a constant splat
499 // This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The
500 // differences are that it assumes the MSA has already been checked and the
501 // arbitrary requirement for a maximum of 32-bit integers isn't applied (and
502 // must not be in order for binsri.d to be selectable).
503 static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) {
504 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N.getNode());
509 APInt SplatValue, SplatUndef;
510 unsigned SplatBitSize;
513 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
522 // Test whether the given node is an all-ones build_vector.
523 static bool isVectorAllOnes(SDValue N) {
524 // Look through bitcasts. Endianness doesn't matter because we are looking
525 // for an all-ones value.
526 if (N->getOpcode() == ISD::BITCAST)
527 N = N->getOperand(0);
529 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
534 APInt SplatValue, SplatUndef;
535 unsigned SplatBitSize;
538 // Endianness doesn't matter in this context because we are looking for
539 // an all-ones value.
540 if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
541 return SplatValue.isAllOnesValue();
546 // Test whether N is the bitwise inverse of OfNode.
547 static bool isBitwiseInverse(SDValue N, SDValue OfNode) {
548 if (N->getOpcode() != ISD::XOR)
551 if (isVectorAllOnes(N->getOperand(0)))
552 return N->getOperand(1) == OfNode;
554 if (isVectorAllOnes(N->getOperand(1)))
555 return N->getOperand(0) == OfNode;
560 // Perform combines where ISD::OR is the root node.
562 // Performs the following transformations:
563 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
564 // where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
566 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
567 TargetLowering::DAGCombinerInfo &DCI,
568 const MipsSubtarget *Subtarget) {
569 if (!Subtarget->hasMSA())
572 EVT Ty = N->getValueType(0);
574 if (!Ty.is128BitVector())
577 SDValue Op0 = N->getOperand(0);
578 SDValue Op1 = N->getOperand(1);
580 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
581 SDValue Op0Op0 = Op0->getOperand(0);
582 SDValue Op0Op1 = Op0->getOperand(1);
583 SDValue Op1Op0 = Op1->getOperand(0);
584 SDValue Op1Op1 = Op1->getOperand(1);
585 bool IsLittleEndian = !Subtarget->isLittle();
587 SDValue IfSet, IfClr, Cond;
588 bool IsConstantMask = false;
591 // If Op0Op0 is an appropriate mask, try to find it's inverse in either
592 // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while
594 // IfClr will be set if we find a valid match.
595 if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {
599 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
600 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
602 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
603 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
606 IsConstantMask = true;
609 // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same
610 // thing again using this mask.
611 // IfClr will be set if we find a valid match.
612 if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
616 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
617 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
619 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
620 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
623 IsConstantMask = true;
626 // If IfClr is not yet set, try looking for a non-constant match.
627 // IfClr will be set if we find a valid match amongst the eight
629 if (!IfClr.getNode()) {
630 if (isBitwiseInverse(Op0Op0, Op1Op0)) {
634 } else if (isBitwiseInverse(Op0Op1, Op1Op0)) {
638 } else if (isBitwiseInverse(Op0Op0, Op1Op1)) {
642 } else if (isBitwiseInverse(Op0Op1, Op1Op1)) {
646 } else if (isBitwiseInverse(Op1Op0, Op0Op0)) {
650 } else if (isBitwiseInverse(Op1Op1, Op0Op0)) {
654 } else if (isBitwiseInverse(Op1Op0, Op0Op1)) {
658 } else if (isBitwiseInverse(Op1Op1, Op0Op1)) {
665 // At this point, IfClr will be set if we have a valid match.
666 if (!IfClr.getNode())
669 assert(Cond.getNode() && IfSet.getNode());
671 // Fold degenerate cases.
672 if (IsConstantMask) {
673 if (Mask.isAllOnesValue())
679 // Transform the DAG into an equivalent VSELECT.
680 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfClr, IfSet);
686 static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
687 TargetLowering::DAGCombinerInfo &DCI,
688 const MipsSubtarget *Subtarget) {
689 if (DCI.isBeforeLegalize())
692 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
694 return SDValue(N, 0);
699 static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
700 EVT ShiftTy, SelectionDAG &DAG) {
701 // Clear the upper (64 - VT.sizeInBits) bits.
702 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
706 return DAG.getConstant(0, VT);
712 // If c is power of 2, return (shl x, log2(c)).
713 if (isPowerOf2_64(C))
714 return DAG.getNode(ISD::SHL, DL, VT, X,
715 DAG.getConstant(Log2_64(C), ShiftTy));
717 unsigned Log2Ceil = Log2_64_Ceil(C);
718 uint64_t Floor = 1LL << Log2_64(C);
719 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
721 // If |c - floor_c| <= |c - ceil_c|,
722 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
723 // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
724 if (C - Floor <= Ceil - C) {
725 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
726 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
727 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
730 // If |c - floor_c| > |c - ceil_c|,
731 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
732 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
733 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
734 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
737 static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
738 const TargetLowering::DAGCombinerInfo &DCI,
739 const MipsSETargetLowering *TL) {
740 EVT VT = N->getValueType(0);
742 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
744 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
745 VT, TL->getScalarShiftAmountTy(VT), DAG);
747 return SDValue(N, 0);
750 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
752 const MipsSubtarget *Subtarget) {
753 // See if this is a vector splat immediate node.
754 APInt SplatValue, SplatUndef;
755 unsigned SplatBitSize;
757 unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
758 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
760 if (!Subtarget->hasDSP())
764 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
765 EltSize, !Subtarget->isLittle()) ||
766 (SplatBitSize != EltSize) ||
767 (SplatValue.getZExtValue() >= EltSize))
770 return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
771 DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
774 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
775 TargetLowering::DAGCombinerInfo &DCI,
776 const MipsSubtarget *Subtarget) {
777 EVT Ty = N->getValueType(0);
779 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
782 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
785 // Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
786 // constant splats into MipsISD::SHRA_DSP for DSPr2.
788 // Performs the following transformations:
789 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
790 // sign/zero-extension is completely overwritten by the new one performed by
791 // the ISD::SRA and ISD::SHL nodes.
792 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
795 // See performDSPShiftCombine for more information about the transformation
797 static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
798 TargetLowering::DAGCombinerInfo &DCI,
799 const MipsSubtarget *Subtarget) {
800 EVT Ty = N->getValueType(0);
802 if (Subtarget->hasMSA()) {
803 SDValue Op0 = N->getOperand(0);
804 SDValue Op1 = N->getOperand(1);
806 // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
807 // where $d + sizeof($c) == 32
808 // or $d + sizeof($c) <= 32 and SExt
809 // -> (MipsVExtractSExt $a, $b, $c)
810 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
811 SDValue Op0Op0 = Op0->getOperand(0);
812 ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
817 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
818 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)
821 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
822 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
824 if (TotalBits == 32 ||
825 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
827 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
828 Op0Op0->getOperand(2) };
829 DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT,
830 Op0Op0->getVTList(), Ops, Op0Op0->getNumOperands());
836 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
839 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
843 static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
844 TargetLowering::DAGCombinerInfo &DCI,
845 const MipsSubtarget *Subtarget) {
846 EVT Ty = N->getValueType(0);
848 if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
851 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
854 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
855 bool IsV216 = (Ty == MVT::v2i16);
859 case ISD::SETNE: return true;
863 case ISD::SETGE: return IsV216;
867 case ISD::SETUGE: return !IsV216;
868 default: return false;
872 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
873 EVT Ty = N->getValueType(0);
875 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
878 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
881 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
882 N->getOperand(1), N->getOperand(2));
885 static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
886 EVT Ty = N->getValueType(0);
888 if (Ty.is128BitVector() && Ty.isInteger()) {
889 // Try the following combines:
890 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
891 // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
892 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
893 // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
894 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
895 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
896 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
897 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
898 // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
899 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
901 SDValue Op0 = N->getOperand(0);
903 if (Op0->getOpcode() != ISD::SETCC)
906 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
909 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE)
911 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
916 SDValue Op1 = N->getOperand(1);
917 SDValue Op2 = N->getOperand(2);
918 SDValue Op0Op0 = Op0->getOperand(0);
919 SDValue Op0Op1 = Op0->getOperand(1);
921 if (Op1 == Op0Op0 && Op2 == Op0Op1)
922 return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
924 else if (Op1 == Op0Op1 && Op2 == Op0Op0)
925 return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
927 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
928 SDValue SetCC = N->getOperand(0);
930 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
933 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
934 SetCC.getOperand(0), SetCC.getOperand(1),
935 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
941 static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
942 const MipsSubtarget *Subtarget) {
943 EVT Ty = N->getValueType(0);
945 if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
946 // Try the following combines:
947 // (xor (or $a, $b), (build_vector allones))
948 // (xor (or $a, $b), (bitcast (build_vector allones)))
949 SDValue Op0 = N->getOperand(0);
950 SDValue Op1 = N->getOperand(1);
953 if (ISD::isBuildVectorAllOnes(Op0.getNode()))
955 else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
960 if (NotOp->getOpcode() == ISD::OR)
961 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
962 NotOp->getOperand(1));
969 MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
970 SelectionDAG &DAG = DCI.DAG;
973 switch (N->getOpcode()) {
975 return performADDECombine(N, DAG, DCI, Subtarget);
977 Val = performANDCombine(N, DAG, DCI, Subtarget);
980 Val = performORCombine(N, DAG, DCI, Subtarget);
983 return performSUBECombine(N, DAG, DCI, Subtarget);
985 return performMULCombine(N, DAG, DCI, this);
987 return performSHLCombine(N, DAG, DCI, Subtarget);
989 return performSRACombine(N, DAG, DCI, Subtarget);
991 return performSRLCombine(N, DAG, DCI, Subtarget);
993 return performVSELECTCombine(N, DAG);
995 Val = performXORCombine(N, DAG, Subtarget);
998 Val = performSETCCCombine(N, DAG);
1002 if (Val.getNode()) {
1003 DEBUG(dbgs() << "\nMipsSE DAG Combine:\n";
1004 N->printrWithDepth(dbgs(), &DAG);
1005 dbgs() << "\n=> \n";
1006 Val.getNode()->printrWithDepth(dbgs(), &DAG);
1011 return MipsTargetLowering::PerformDAGCombine(N, DCI);
1015 MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1016 MachineBasicBlock *BB) const {
1017 switch (MI->getOpcode()) {
1019 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
1020 case Mips::BPOSGE32_PSEUDO:
1021 return emitBPOSGE32(MI, BB);
1022 case Mips::SNZ_B_PSEUDO:
1023 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
1024 case Mips::SNZ_H_PSEUDO:
1025 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
1026 case Mips::SNZ_W_PSEUDO:
1027 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
1028 case Mips::SNZ_D_PSEUDO:
1029 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
1030 case Mips::SNZ_V_PSEUDO:
1031 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
1032 case Mips::SZ_B_PSEUDO:
1033 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
1034 case Mips::SZ_H_PSEUDO:
1035 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
1036 case Mips::SZ_W_PSEUDO:
1037 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
1038 case Mips::SZ_D_PSEUDO:
1039 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
1040 case Mips::SZ_V_PSEUDO:
1041 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
1042 case Mips::COPY_FW_PSEUDO:
1043 return emitCOPY_FW(MI, BB);
1044 case Mips::COPY_FD_PSEUDO:
1045 return emitCOPY_FD(MI, BB);
1046 case Mips::INSERT_FW_PSEUDO:
1047 return emitINSERT_FW(MI, BB);
1048 case Mips::INSERT_FD_PSEUDO:
1049 return emitINSERT_FD(MI, BB);
1050 case Mips::FILL_FW_PSEUDO:
1051 return emitFILL_FW(MI, BB);
1052 case Mips::FILL_FD_PSEUDO:
1053 return emitFILL_FD(MI, BB);
1054 case Mips::FEXP2_W_1_PSEUDO:
1055 return emitFEXP2_W_1(MI, BB);
1056 case Mips::FEXP2_D_1_PSEUDO:
1057 return emitFEXP2_D_1(MI, BB);
1061 bool MipsSETargetLowering::
1062 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
1063 unsigned NextStackOffset,
1064 const MipsFunctionInfo& FI) const {
1065 if (!EnableMipsTailCalls)
1068 // Return false if either the callee or caller has a byval argument.
1069 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
1072 // Return true if the callee's argument area is no larger than the
1074 return NextStackOffset <= FI.getIncomingArgSize();
1077 void MipsSETargetLowering::
1078 getOpndList(SmallVectorImpl<SDValue> &Ops,
1079 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
1080 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
1081 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
1082 Ops.push_back(Callee);
1083 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
1084 InternalLinkage, CLI, Callee, Chain);
1087 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1088 LoadSDNode &Nd = *cast<LoadSDNode>(Op);
1090 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1091 return MipsTargetLowering::lowerLOAD(Op, DAG);
1093 // Replace a double precision load with two i32 loads and a buildpair64.
1095 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1096 EVT PtrVT = Ptr.getValueType();
1098 // i32 load from lower address.
1099 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
1100 MachinePointerInfo(), Nd.isVolatile(),
1101 Nd.isNonTemporal(), Nd.isInvariant(),
1104 // i32 load from higher address.
1105 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
1106 SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
1107 MachinePointerInfo(), Nd.isVolatile(),
1108 Nd.isNonTemporal(), Nd.isInvariant(),
1109 std::min(Nd.getAlignment(), 4U));
1111 if (!Subtarget->isLittle())
1114 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1115 SDValue Ops[2] = {BP, Hi.getValue(1)};
1116 return DAG.getMergeValues(Ops, 2, DL);
1119 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1120 StoreSDNode &Nd = *cast<StoreSDNode>(Op);
1122 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1123 return MipsTargetLowering::lowerSTORE(Op, DAG);
1125 // Replace a double precision store with two extractelement64s and i32 stores.
1127 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1128 EVT PtrVT = Ptr.getValueType();
1129 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1130 Val, DAG.getConstant(0, MVT::i32));
1131 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1132 Val, DAG.getConstant(1, MVT::i32));
1134 if (!Subtarget->isLittle())
1137 // i32 store to lower address.
1138 Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
1139 Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
1142 // i32 store to higher address.
1143 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
1144 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
1145 Nd.isVolatile(), Nd.isNonTemporal(),
1146 std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo());
1149 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
1150 bool HasLo, bool HasHi,
1151 SelectionDAG &DAG) const {
1152 EVT Ty = Op.getOperand(0).getValueType();
1154 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
1155 Op.getOperand(0), Op.getOperand(1));
1159 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);
1161 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);
1163 if (!HasLo || !HasHi)
1164 return HasLo ? Lo : Hi;
1166 SDValue Vals[] = { Lo, Hi };
1167 return DAG.getMergeValues(Vals, 2, DL);
1171 static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
1172 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1173 DAG.getConstant(0, MVT::i32));
1174 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1175 DAG.getConstant(1, MVT::i32));
1176 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
1179 static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
1180 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op);
1181 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op);
1182 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1185 // This function expands mips intrinsic nodes which have 64-bit input operands
1186 // or output values.
1188 // out64 = intrinsic-node in64
1190 // lo = copy (extract-element (in64, 0))
1191 // hi = copy (extract-element (in64, 1))
1192 // mips-specific-node
1195 // out64 = merge-values (v0, v1)
1197 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1199 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
1200 SmallVector<SDValue, 3> Ops;
1203 // See if Op has a chain input.
1205 Ops.push_back(Op->getOperand(OpNo++));
1207 // The next operand is the intrinsic opcode.
1208 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
1210 // See if the next operand has type i64.
1211 SDValue Opnd = Op->getOperand(++OpNo), In64;
1213 if (Opnd.getValueType() == MVT::i64)
1214 In64 = initAccumulator(Opnd, DL, DAG);
1216 Ops.push_back(Opnd);
1218 // Push the remaining operands.
1219 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1220 Ops.push_back(Op->getOperand(OpNo));
1222 // Add In64 to the end of the list.
1224 Ops.push_back(In64);
1227 SmallVector<EVT, 2> ResTys;
1229 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1231 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1234 SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
1235 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1240 assert(Val->getValueType(1) == MVT::Other);
1241 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1242 return DAG.getMergeValues(Vals, 2, DL);
1245 // Lower an MSA copy intrinsic into the specified SelectionDAG node
1246 static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1248 SDValue Vec = Op->getOperand(1);
1249 SDValue Idx = Op->getOperand(2);
1250 EVT ResTy = Op->getValueType(0);
1251 EVT EltTy = Vec->getValueType(0).getVectorElementType();
1253 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1254 DAG.getValueType(EltTy));
1259 static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
1260 EVT ResVecTy = Op->getValueType(0);
1261 EVT ViaVecTy = ResVecTy;
1264 // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and
1265 // LaneB is the lower 32-bits. Otherwise LaneA and LaneB are alternating
1268 SDValue LaneB = Op->getOperand(2);
1270 if (ResVecTy == MVT::v2i64) {
1271 LaneA = DAG.getConstant(0, MVT::i32);
1272 ViaVecTy = MVT::v4i32;
1276 SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1277 LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
1279 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, Ops,
1280 ViaVecTy.getVectorNumElements());
1282 if (ViaVecTy != ResVecTy)
1283 Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result);
1288 static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
1289 return DAG.getConstant(Op->getConstantOperandVal(ImmOp), Op->getValueType(0));
1292 static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
1293 bool BigEndian, SelectionDAG &DAG) {
1294 EVT ViaVecTy = VecTy;
1295 SDValue SplatValueA = SplatValue;
1296 SDValue SplatValueB = SplatValue;
1297 SDLoc DL(SplatValue);
1299 if (VecTy == MVT::v2i64) {
1300 // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
1301 ViaVecTy = MVT::v4i32;
1303 SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue);
1304 SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue,
1305 DAG.getConstant(32, MVT::i32));
1306 SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB);
1309 // We currently hold the parts in little endian order. Swap them if
1312 std::swap(SplatValueA, SplatValueB);
1314 SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1315 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1316 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1317 SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1319 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, Ops,
1320 ViaVecTy.getVectorNumElements());
1322 if (VecTy != ViaVecTy)
1323 Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
1328 static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG,
1329 unsigned Opc, SDValue Imm,
1331 EVT VecTy = Op->getValueType(0);
1335 // The DAG Combiner can't constant fold bitcasted vectors yet so we must do it
1337 if (VecTy == MVT::v2i64) {
1338 if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
1339 APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();
1341 SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), MVT::i32);
1342 SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), MVT::i32);
1345 std::swap(BitImmLoOp, BitImmHiOp);
1348 DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
1349 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, BitImmLoOp,
1350 BitImmHiOp, BitImmLoOp, BitImmHiOp));
1354 if (Exp2Imm.getNode() == NULL) {
1355 // We couldnt constant fold, do a vector shift instead
1357 // Extend i32 to i64 if necessary. Sign or zero extend doesn't matter since
1358 // only values 0-63 are valid.
1359 if (VecTy == MVT::v2i64)
1360 Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm);
1362 Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG);
1365 DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, VecTy), Exp2Imm);
1368 return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
1371 static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG) {
1372 EVT ResTy = Op->getValueType(0);
1374 SDValue One = DAG.getConstant(1, ResTy);
1375 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2));
1377 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1378 DAG.getNOT(DL, Bit, ResTy));
1381 static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) {
1383 EVT ResTy = Op->getValueType(0);
1384 APInt BitImm = APInt(ResTy.getVectorElementType().getSizeInBits(), 1)
1385 << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
1386 SDValue BitMask = DAG.getConstant(~BitImm, ResTy);
1388 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1391 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1392 SelectionDAG &DAG) const {
1395 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
1398 case Intrinsic::mips_shilo:
1399 return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1400 case Intrinsic::mips_dpau_h_qbl:
1401 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1402 case Intrinsic::mips_dpau_h_qbr:
1403 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1404 case Intrinsic::mips_dpsu_h_qbl:
1405 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1406 case Intrinsic::mips_dpsu_h_qbr:
1407 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1408 case Intrinsic::mips_dpa_w_ph:
1409 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1410 case Intrinsic::mips_dps_w_ph:
1411 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1412 case Intrinsic::mips_dpax_w_ph:
1413 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1414 case Intrinsic::mips_dpsx_w_ph:
1415 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1416 case Intrinsic::mips_mulsa_w_ph:
1417 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1418 case Intrinsic::mips_mult:
1419 return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1420 case Intrinsic::mips_multu:
1421 return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1422 case Intrinsic::mips_madd:
1423 return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1424 case Intrinsic::mips_maddu:
1425 return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1426 case Intrinsic::mips_msub:
1427 return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1428 case Intrinsic::mips_msubu:
1429 return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1430 case Intrinsic::mips_addv_b:
1431 case Intrinsic::mips_addv_h:
1432 case Intrinsic::mips_addv_w:
1433 case Intrinsic::mips_addv_d:
1434 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1436 case Intrinsic::mips_addvi_b:
1437 case Intrinsic::mips_addvi_h:
1438 case Intrinsic::mips_addvi_w:
1439 case Intrinsic::mips_addvi_d:
1440 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1441 lowerMSASplatImm(Op, 2, DAG));
1442 case Intrinsic::mips_and_v:
1443 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1445 case Intrinsic::mips_andi_b:
1446 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1447 lowerMSASplatImm(Op, 2, DAG));
1448 case Intrinsic::mips_bclr_b:
1449 case Intrinsic::mips_bclr_h:
1450 case Intrinsic::mips_bclr_w:
1451 case Intrinsic::mips_bclr_d:
1452 return lowerMSABitClear(Op, DAG);
1453 case Intrinsic::mips_bclri_b:
1454 case Intrinsic::mips_bclri_h:
1455 case Intrinsic::mips_bclri_w:
1456 case Intrinsic::mips_bclri_d:
1457 return lowerMSABitClearImm(Op, DAG);
1458 case Intrinsic::mips_binsli_b:
1459 case Intrinsic::mips_binsli_h:
1460 case Intrinsic::mips_binsli_w:
1461 case Intrinsic::mips_binsli_d: {
1462 EVT VecTy = Op->getValueType(0);
1463 EVT EltTy = VecTy.getVectorElementType();
1464 APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(),
1465 Op->getConstantOperandVal(3));
1466 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1467 DAG.getConstant(Mask, VecTy, true), Op->getOperand(1),
1470 case Intrinsic::mips_binsri_b:
1471 case Intrinsic::mips_binsri_h:
1472 case Intrinsic::mips_binsri_w:
1473 case Intrinsic::mips_binsri_d: {
1474 EVT VecTy = Op->getValueType(0);
1475 EVT EltTy = VecTy.getVectorElementType();
1476 APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(),
1477 Op->getConstantOperandVal(3));
1478 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1479 DAG.getConstant(Mask, VecTy, true), Op->getOperand(1),
1482 case Intrinsic::mips_bmnz_v:
1483 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1484 Op->getOperand(2), Op->getOperand(1));
1485 case Intrinsic::mips_bmnzi_b:
1486 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1487 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2),
1489 case Intrinsic::mips_bmz_v:
1490 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1491 Op->getOperand(1), Op->getOperand(2));
1492 case Intrinsic::mips_bmzi_b:
1493 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1494 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1),
1496 case Intrinsic::mips_bneg_b:
1497 case Intrinsic::mips_bneg_h:
1498 case Intrinsic::mips_bneg_w:
1499 case Intrinsic::mips_bneg_d: {
1500 EVT VecTy = Op->getValueType(0);
1501 SDValue One = DAG.getConstant(1, VecTy);
1503 return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
1504 DAG.getNode(ISD::SHL, DL, VecTy, One,
1505 Op->getOperand(2)));
1507 case Intrinsic::mips_bnegi_b:
1508 case Intrinsic::mips_bnegi_h:
1509 case Intrinsic::mips_bnegi_w:
1510 case Intrinsic::mips_bnegi_d:
1511 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
1512 !Subtarget->isLittle());
1513 case Intrinsic::mips_bnz_b:
1514 case Intrinsic::mips_bnz_h:
1515 case Intrinsic::mips_bnz_w:
1516 case Intrinsic::mips_bnz_d:
1517 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1519 case Intrinsic::mips_bnz_v:
1520 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1522 case Intrinsic::mips_bsel_v:
1523 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1524 Op->getOperand(1), Op->getOperand(2),
1526 case Intrinsic::mips_bseli_b:
1527 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1528 Op->getOperand(1), Op->getOperand(2),
1529 lowerMSASplatImm(Op, 3, DAG));
1530 case Intrinsic::mips_bset_b:
1531 case Intrinsic::mips_bset_h:
1532 case Intrinsic::mips_bset_w:
1533 case Intrinsic::mips_bset_d: {
1534 EVT VecTy = Op->getValueType(0);
1535 SDValue One = DAG.getConstant(1, VecTy);
1537 return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
1538 DAG.getNode(ISD::SHL, DL, VecTy, One,
1539 Op->getOperand(2)));
1541 case Intrinsic::mips_bseti_b:
1542 case Intrinsic::mips_bseti_h:
1543 case Intrinsic::mips_bseti_w:
1544 case Intrinsic::mips_bseti_d:
1545 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
1546 !Subtarget->isLittle());
1547 case Intrinsic::mips_bz_b:
1548 case Intrinsic::mips_bz_h:
1549 case Intrinsic::mips_bz_w:
1550 case Intrinsic::mips_bz_d:
1551 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1553 case Intrinsic::mips_bz_v:
1554 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1556 case Intrinsic::mips_ceq_b:
1557 case Intrinsic::mips_ceq_h:
1558 case Intrinsic::mips_ceq_w:
1559 case Intrinsic::mips_ceq_d:
1560 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1561 Op->getOperand(2), ISD::SETEQ);
1562 case Intrinsic::mips_ceqi_b:
1563 case Intrinsic::mips_ceqi_h:
1564 case Intrinsic::mips_ceqi_w:
1565 case Intrinsic::mips_ceqi_d:
1566 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1567 lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ);
1568 case Intrinsic::mips_cle_s_b:
1569 case Intrinsic::mips_cle_s_h:
1570 case Intrinsic::mips_cle_s_w:
1571 case Intrinsic::mips_cle_s_d:
1572 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1573 Op->getOperand(2), ISD::SETLE);
1574 case Intrinsic::mips_clei_s_b:
1575 case Intrinsic::mips_clei_s_h:
1576 case Intrinsic::mips_clei_s_w:
1577 case Intrinsic::mips_clei_s_d:
1578 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1579 lowerMSASplatImm(Op, 2, DAG), ISD::SETLE);
1580 case Intrinsic::mips_cle_u_b:
1581 case Intrinsic::mips_cle_u_h:
1582 case Intrinsic::mips_cle_u_w:
1583 case Intrinsic::mips_cle_u_d:
1584 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1585 Op->getOperand(2), ISD::SETULE);
1586 case Intrinsic::mips_clei_u_b:
1587 case Intrinsic::mips_clei_u_h:
1588 case Intrinsic::mips_clei_u_w:
1589 case Intrinsic::mips_clei_u_d:
1590 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1591 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1592 case Intrinsic::mips_clt_s_b:
1593 case Intrinsic::mips_clt_s_h:
1594 case Intrinsic::mips_clt_s_w:
1595 case Intrinsic::mips_clt_s_d:
1596 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1597 Op->getOperand(2), ISD::SETLT);
1598 case Intrinsic::mips_clti_s_b:
1599 case Intrinsic::mips_clti_s_h:
1600 case Intrinsic::mips_clti_s_w:
1601 case Intrinsic::mips_clti_s_d:
1602 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1603 lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);
1604 case Intrinsic::mips_clt_u_b:
1605 case Intrinsic::mips_clt_u_h:
1606 case Intrinsic::mips_clt_u_w:
1607 case Intrinsic::mips_clt_u_d:
1608 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1609 Op->getOperand(2), ISD::SETULT);
1610 case Intrinsic::mips_clti_u_b:
1611 case Intrinsic::mips_clti_u_h:
1612 case Intrinsic::mips_clti_u_w:
1613 case Intrinsic::mips_clti_u_d:
1614 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1615 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1616 case Intrinsic::mips_copy_s_b:
1617 case Intrinsic::mips_copy_s_h:
1618 case Intrinsic::mips_copy_s_w:
1619 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1620 case Intrinsic::mips_copy_s_d:
1622 // Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64.
1623 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1625 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1626 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1627 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1628 Op->getValueType(0), Op->getOperand(1),
1631 case Intrinsic::mips_copy_u_b:
1632 case Intrinsic::mips_copy_u_h:
1633 case Intrinsic::mips_copy_u_w:
1634 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1635 case Intrinsic::mips_copy_u_d:
1637 // Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64.
1638 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1640 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1641 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1642 // Note: When i64 is illegal, this results in copy_s.w instructions
1643 // instead of copy_u.w instructions. This makes no difference to the
1644 // behaviour since i64 is only illegal when the register file is 32-bit.
1645 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1646 Op->getValueType(0), Op->getOperand(1),
1649 case Intrinsic::mips_div_s_b:
1650 case Intrinsic::mips_div_s_h:
1651 case Intrinsic::mips_div_s_w:
1652 case Intrinsic::mips_div_s_d:
1653 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1655 case Intrinsic::mips_div_u_b:
1656 case Intrinsic::mips_div_u_h:
1657 case Intrinsic::mips_div_u_w:
1658 case Intrinsic::mips_div_u_d:
1659 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1661 case Intrinsic::mips_fadd_w:
1662 case Intrinsic::mips_fadd_d:
1663 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1665 // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1666 case Intrinsic::mips_fceq_w:
1667 case Intrinsic::mips_fceq_d:
1668 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1669 Op->getOperand(2), ISD::SETOEQ);
1670 case Intrinsic::mips_fcle_w:
1671 case Intrinsic::mips_fcle_d:
1672 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1673 Op->getOperand(2), ISD::SETOLE);
1674 case Intrinsic::mips_fclt_w:
1675 case Intrinsic::mips_fclt_d:
1676 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1677 Op->getOperand(2), ISD::SETOLT);
1678 case Intrinsic::mips_fcne_w:
1679 case Intrinsic::mips_fcne_d:
1680 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1681 Op->getOperand(2), ISD::SETONE);
1682 case Intrinsic::mips_fcor_w:
1683 case Intrinsic::mips_fcor_d:
1684 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1685 Op->getOperand(2), ISD::SETO);
1686 case Intrinsic::mips_fcueq_w:
1687 case Intrinsic::mips_fcueq_d:
1688 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1689 Op->getOperand(2), ISD::SETUEQ);
1690 case Intrinsic::mips_fcule_w:
1691 case Intrinsic::mips_fcule_d:
1692 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1693 Op->getOperand(2), ISD::SETULE);
1694 case Intrinsic::mips_fcult_w:
1695 case Intrinsic::mips_fcult_d:
1696 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1697 Op->getOperand(2), ISD::SETULT);
1698 case Intrinsic::mips_fcun_w:
1699 case Intrinsic::mips_fcun_d:
1700 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1701 Op->getOperand(2), ISD::SETUO);
1702 case Intrinsic::mips_fcune_w:
1703 case Intrinsic::mips_fcune_d:
1704 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1705 Op->getOperand(2), ISD::SETUNE);
1706 case Intrinsic::mips_fdiv_w:
1707 case Intrinsic::mips_fdiv_d:
1708 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1710 case Intrinsic::mips_ffint_u_w:
1711 case Intrinsic::mips_ffint_u_d:
1712 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1714 case Intrinsic::mips_ffint_s_w:
1715 case Intrinsic::mips_ffint_s_d:
1716 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1718 case Intrinsic::mips_fill_b:
1719 case Intrinsic::mips_fill_h:
1720 case Intrinsic::mips_fill_w:
1721 case Intrinsic::mips_fill_d: {
1722 SmallVector<SDValue, 16> Ops;
1723 EVT ResTy = Op->getValueType(0);
1725 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1726 Ops.push_back(Op->getOperand(1));
1728 // If ResTy is v2i64 then the type legalizer will break this node down into
1729 // an equivalent v4i32.
1730 return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, &Ops[0], Ops.size());
1732 case Intrinsic::mips_fexp2_w:
1733 case Intrinsic::mips_fexp2_d: {
1734 EVT ResTy = Op->getValueType(0);
1736 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1737 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1739 case Intrinsic::mips_flog2_w:
1740 case Intrinsic::mips_flog2_d:
1741 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1742 case Intrinsic::mips_fmadd_w:
1743 case Intrinsic::mips_fmadd_d:
1744 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1745 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1746 case Intrinsic::mips_fmul_w:
1747 case Intrinsic::mips_fmul_d:
1748 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1750 case Intrinsic::mips_fmsub_w:
1751 case Intrinsic::mips_fmsub_d: {
1752 EVT ResTy = Op->getValueType(0);
1753 return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
1754 DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,
1755 Op->getOperand(2), Op->getOperand(3)));
1757 case Intrinsic::mips_frint_w:
1758 case Intrinsic::mips_frint_d:
1759 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1760 case Intrinsic::mips_fsqrt_w:
1761 case Intrinsic::mips_fsqrt_d:
1762 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1763 case Intrinsic::mips_fsub_w:
1764 case Intrinsic::mips_fsub_d:
1765 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1767 case Intrinsic::mips_ftrunc_u_w:
1768 case Intrinsic::mips_ftrunc_u_d:
1769 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1771 case Intrinsic::mips_ftrunc_s_w:
1772 case Intrinsic::mips_ftrunc_s_d:
1773 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1775 case Intrinsic::mips_ilvev_b:
1776 case Intrinsic::mips_ilvev_h:
1777 case Intrinsic::mips_ilvev_w:
1778 case Intrinsic::mips_ilvev_d:
1779 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
1780 Op->getOperand(1), Op->getOperand(2));
1781 case Intrinsic::mips_ilvl_b:
1782 case Intrinsic::mips_ilvl_h:
1783 case Intrinsic::mips_ilvl_w:
1784 case Intrinsic::mips_ilvl_d:
1785 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
1786 Op->getOperand(1), Op->getOperand(2));
1787 case Intrinsic::mips_ilvod_b:
1788 case Intrinsic::mips_ilvod_h:
1789 case Intrinsic::mips_ilvod_w:
1790 case Intrinsic::mips_ilvod_d:
1791 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
1792 Op->getOperand(1), Op->getOperand(2));
1793 case Intrinsic::mips_ilvr_b:
1794 case Intrinsic::mips_ilvr_h:
1795 case Intrinsic::mips_ilvr_w:
1796 case Intrinsic::mips_ilvr_d:
1797 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
1798 Op->getOperand(1), Op->getOperand(2));
1799 case Intrinsic::mips_insert_b:
1800 case Intrinsic::mips_insert_h:
1801 case Intrinsic::mips_insert_w:
1802 case Intrinsic::mips_insert_d:
1803 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1804 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1805 case Intrinsic::mips_ldi_b:
1806 case Intrinsic::mips_ldi_h:
1807 case Intrinsic::mips_ldi_w:
1808 case Intrinsic::mips_ldi_d:
1809 return lowerMSASplatImm(Op, 1, DAG);
1810 case Intrinsic::mips_lsa:
1811 case Intrinsic::mips_dlsa: {
1812 EVT ResTy = Op->getValueType(0);
1813 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1814 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
1815 Op->getOperand(2), Op->getOperand(3)));
1817 case Intrinsic::mips_maddv_b:
1818 case Intrinsic::mips_maddv_h:
1819 case Intrinsic::mips_maddv_w:
1820 case Intrinsic::mips_maddv_d: {
1821 EVT ResTy = Op->getValueType(0);
1822 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1823 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1824 Op->getOperand(2), Op->getOperand(3)));
1826 case Intrinsic::mips_max_s_b:
1827 case Intrinsic::mips_max_s_h:
1828 case Intrinsic::mips_max_s_w:
1829 case Intrinsic::mips_max_s_d:
1830 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1831 Op->getOperand(1), Op->getOperand(2));
1832 case Intrinsic::mips_max_u_b:
1833 case Intrinsic::mips_max_u_h:
1834 case Intrinsic::mips_max_u_w:
1835 case Intrinsic::mips_max_u_d:
1836 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1837 Op->getOperand(1), Op->getOperand(2));
1838 case Intrinsic::mips_maxi_s_b:
1839 case Intrinsic::mips_maxi_s_h:
1840 case Intrinsic::mips_maxi_s_w:
1841 case Intrinsic::mips_maxi_s_d:
1842 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1843 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1844 case Intrinsic::mips_maxi_u_b:
1845 case Intrinsic::mips_maxi_u_h:
1846 case Intrinsic::mips_maxi_u_w:
1847 case Intrinsic::mips_maxi_u_d:
1848 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1849 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1850 case Intrinsic::mips_min_s_b:
1851 case Intrinsic::mips_min_s_h:
1852 case Intrinsic::mips_min_s_w:
1853 case Intrinsic::mips_min_s_d:
1854 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1855 Op->getOperand(1), Op->getOperand(2));
1856 case Intrinsic::mips_min_u_b:
1857 case Intrinsic::mips_min_u_h:
1858 case Intrinsic::mips_min_u_w:
1859 case Intrinsic::mips_min_u_d:
1860 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1861 Op->getOperand(1), Op->getOperand(2));
1862 case Intrinsic::mips_mini_s_b:
1863 case Intrinsic::mips_mini_s_h:
1864 case Intrinsic::mips_mini_s_w:
1865 case Intrinsic::mips_mini_s_d:
1866 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1867 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1868 case Intrinsic::mips_mini_u_b:
1869 case Intrinsic::mips_mini_u_h:
1870 case Intrinsic::mips_mini_u_w:
1871 case Intrinsic::mips_mini_u_d:
1872 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1873 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1874 case Intrinsic::mips_mod_s_b:
1875 case Intrinsic::mips_mod_s_h:
1876 case Intrinsic::mips_mod_s_w:
1877 case Intrinsic::mips_mod_s_d:
1878 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
1880 case Intrinsic::mips_mod_u_b:
1881 case Intrinsic::mips_mod_u_h:
1882 case Intrinsic::mips_mod_u_w:
1883 case Intrinsic::mips_mod_u_d:
1884 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
1886 case Intrinsic::mips_mulv_b:
1887 case Intrinsic::mips_mulv_h:
1888 case Intrinsic::mips_mulv_w:
1889 case Intrinsic::mips_mulv_d:
1890 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
1892 case Intrinsic::mips_msubv_b:
1893 case Intrinsic::mips_msubv_h:
1894 case Intrinsic::mips_msubv_w:
1895 case Intrinsic::mips_msubv_d: {
1896 EVT ResTy = Op->getValueType(0);
1897 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
1898 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1899 Op->getOperand(2), Op->getOperand(3)));
1901 case Intrinsic::mips_nlzc_b:
1902 case Intrinsic::mips_nlzc_h:
1903 case Intrinsic::mips_nlzc_w:
1904 case Intrinsic::mips_nlzc_d:
1905 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
1906 case Intrinsic::mips_nor_v: {
1907 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1908 Op->getOperand(1), Op->getOperand(2));
1909 return DAG.getNOT(DL, Res, Res->getValueType(0));
1911 case Intrinsic::mips_nori_b: {
1912 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1914 lowerMSASplatImm(Op, 2, DAG));
1915 return DAG.getNOT(DL, Res, Res->getValueType(0));
1917 case Intrinsic::mips_or_v:
1918 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
1920 case Intrinsic::mips_ori_b:
1921 return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1922 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1923 case Intrinsic::mips_pckev_b:
1924 case Intrinsic::mips_pckev_h:
1925 case Intrinsic::mips_pckev_w:
1926 case Intrinsic::mips_pckev_d:
1927 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
1928 Op->getOperand(1), Op->getOperand(2));
1929 case Intrinsic::mips_pckod_b:
1930 case Intrinsic::mips_pckod_h:
1931 case Intrinsic::mips_pckod_w:
1932 case Intrinsic::mips_pckod_d:
1933 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
1934 Op->getOperand(1), Op->getOperand(2));
1935 case Intrinsic::mips_pcnt_b:
1936 case Intrinsic::mips_pcnt_h:
1937 case Intrinsic::mips_pcnt_w:
1938 case Intrinsic::mips_pcnt_d:
1939 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
1940 case Intrinsic::mips_shf_b:
1941 case Intrinsic::mips_shf_h:
1942 case Intrinsic::mips_shf_w:
1943 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
1944 Op->getOperand(2), Op->getOperand(1));
1945 case Intrinsic::mips_sll_b:
1946 case Intrinsic::mips_sll_h:
1947 case Intrinsic::mips_sll_w:
1948 case Intrinsic::mips_sll_d:
1949 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
1951 case Intrinsic::mips_slli_b:
1952 case Intrinsic::mips_slli_h:
1953 case Intrinsic::mips_slli_w:
1954 case Intrinsic::mips_slli_d:
1955 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
1956 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1957 case Intrinsic::mips_splat_b:
1958 case Intrinsic::mips_splat_h:
1959 case Intrinsic::mips_splat_w:
1960 case Intrinsic::mips_splat_d:
1961 // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
1962 // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
1963 // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32.
1964 // Instead we lower to MipsISD::VSHF and match from there.
1965 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1966 lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1),
1968 case Intrinsic::mips_splati_b:
1969 case Intrinsic::mips_splati_h:
1970 case Intrinsic::mips_splati_w:
1971 case Intrinsic::mips_splati_d:
1972 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1973 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
1975 case Intrinsic::mips_sra_b:
1976 case Intrinsic::mips_sra_h:
1977 case Intrinsic::mips_sra_w:
1978 case Intrinsic::mips_sra_d:
1979 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
1981 case Intrinsic::mips_srai_b:
1982 case Intrinsic::mips_srai_h:
1983 case Intrinsic::mips_srai_w:
1984 case Intrinsic::mips_srai_d:
1985 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
1986 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1987 case Intrinsic::mips_srl_b:
1988 case Intrinsic::mips_srl_h:
1989 case Intrinsic::mips_srl_w:
1990 case Intrinsic::mips_srl_d:
1991 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
1993 case Intrinsic::mips_srli_b:
1994 case Intrinsic::mips_srli_h:
1995 case Intrinsic::mips_srli_w:
1996 case Intrinsic::mips_srli_d:
1997 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
1998 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1999 case Intrinsic::mips_subv_b:
2000 case Intrinsic::mips_subv_h:
2001 case Intrinsic::mips_subv_w:
2002 case Intrinsic::mips_subv_d:
2003 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
2005 case Intrinsic::mips_subvi_b:
2006 case Intrinsic::mips_subvi_h:
2007 case Intrinsic::mips_subvi_w:
2008 case Intrinsic::mips_subvi_d:
2009 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
2010 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2011 case Intrinsic::mips_vshf_b:
2012 case Intrinsic::mips_vshf_h:
2013 case Intrinsic::mips_vshf_w:
2014 case Intrinsic::mips_vshf_d:
2015 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2016 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
2017 case Intrinsic::mips_xor_v:
2018 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
2020 case Intrinsic::mips_xori_b:
2021 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
2022 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2026 static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
2028 SDValue ChainIn = Op->getOperand(0);
2029 SDValue Address = Op->getOperand(2);
2030 SDValue Offset = Op->getOperand(3);
2031 EVT ResTy = Op->getValueType(0);
2032 EVT PtrTy = Address->getValueType(0);
2034 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2036 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
2040 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
2041 SelectionDAG &DAG) const {
2042 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2046 case Intrinsic::mips_extp:
2047 return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
2048 case Intrinsic::mips_extpdp:
2049 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
2050 case Intrinsic::mips_extr_w:
2051 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
2052 case Intrinsic::mips_extr_r_w:
2053 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
2054 case Intrinsic::mips_extr_rs_w:
2055 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
2056 case Intrinsic::mips_extr_s_h:
2057 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
2058 case Intrinsic::mips_mthlip:
2059 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
2060 case Intrinsic::mips_mulsaq_s_w_ph:
2061 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
2062 case Intrinsic::mips_maq_s_w_phl:
2063 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
2064 case Intrinsic::mips_maq_s_w_phr:
2065 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
2066 case Intrinsic::mips_maq_sa_w_phl:
2067 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
2068 case Intrinsic::mips_maq_sa_w_phr:
2069 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
2070 case Intrinsic::mips_dpaq_s_w_ph:
2071 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
2072 case Intrinsic::mips_dpsq_s_w_ph:
2073 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
2074 case Intrinsic::mips_dpaq_sa_l_w:
2075 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
2076 case Intrinsic::mips_dpsq_sa_l_w:
2077 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
2078 case Intrinsic::mips_dpaqx_s_w_ph:
2079 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
2080 case Intrinsic::mips_dpaqx_sa_w_ph:
2081 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
2082 case Intrinsic::mips_dpsqx_s_w_ph:
2083 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
2084 case Intrinsic::mips_dpsqx_sa_w_ph:
2085 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
2086 case Intrinsic::mips_ld_b:
2087 case Intrinsic::mips_ld_h:
2088 case Intrinsic::mips_ld_w:
2089 case Intrinsic::mips_ld_d:
2090 return lowerMSALoadIntr(Op, DAG, Intr);
2094 static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
2096 SDValue ChainIn = Op->getOperand(0);
2097 SDValue Value = Op->getOperand(2);
2098 SDValue Address = Op->getOperand(3);
2099 SDValue Offset = Op->getOperand(4);
2100 EVT PtrTy = Address->getValueType(0);
2102 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2104 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
2108 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
2109 SelectionDAG &DAG) const {
2110 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2114 case Intrinsic::mips_st_b:
2115 case Intrinsic::mips_st_h:
2116 case Intrinsic::mips_st_w:
2117 case Intrinsic::mips_st_d:
2118 return lowerMSAStoreIntr(Op, DAG, Intr);
2122 /// \brief Check if the given BuildVectorSDNode is a splat.
2123 /// This method currently relies on DAG nodes being reused when equivalent,
2124 /// so it's possible for this to return false even when isConstantSplat returns
2126 static bool isSplatVector(const BuildVectorSDNode *N) {
2127 unsigned int nOps = N->getNumOperands();
2128 assert(nOps > 1 && "isSplatVector has 0 or 1 sized build vector");
2130 SDValue Operand0 = N->getOperand(0);
2132 for (unsigned int i = 1; i < nOps; ++i) {
2133 if (N->getOperand(i) != Operand0)
2140 // Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
2142 // The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
2143 // choose to sign-extend but we could have equally chosen zero-extend. The
2144 // DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
2145 // result into this node later (possibly changing it to a zero-extend in the
2147 SDValue MipsSETargetLowering::
2148 lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
2150 EVT ResTy = Op->getValueType(0);
2151 SDValue Op0 = Op->getOperand(0);
2152 EVT VecTy = Op0->getValueType(0);
2154 if (!VecTy.is128BitVector())
2157 if (ResTy.isInteger()) {
2158 SDValue Op1 = Op->getOperand(1);
2159 EVT EltTy = VecTy.getVectorElementType();
2160 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
2161 DAG.getValueType(EltTy));
2167 static bool isConstantOrUndef(const SDValue Op) {
2168 if (Op->getOpcode() == ISD::UNDEF)
2170 if (dyn_cast<ConstantSDNode>(Op))
2172 if (dyn_cast<ConstantFPSDNode>(Op))
2177 static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) {
2178 for (unsigned i = 0; i < Op->getNumOperands(); ++i)
2179 if (isConstantOrUndef(Op->getOperand(i)))
2184 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
2187 // Lowers according to the following rules:
2188 // - Constant splats are legal as-is as long as the SplatBitSize is a power of
2189 // 2 less than or equal to 64 and the value fits into a signed 10-bit
2191 // - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
2192 // is a power of 2 less than or equal to 64 and the value does not fit into a
2193 // signed 10-bit immediate
2194 // - Non-constant splats are legal as-is.
2195 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
2196 // - All others are illegal and must be expanded.
2197 SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
2198 SelectionDAG &DAG) const {
2199 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
2200 EVT ResTy = Op->getValueType(0);
2202 APInt SplatValue, SplatUndef;
2203 unsigned SplatBitSize;
2206 if (!Subtarget->hasMSA() || !ResTy.is128BitVector())
2209 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2211 !Subtarget->isLittle()) && SplatBitSize <= 64) {
2212 // We can only cope with 8, 16, 32, or 64-bit elements
2213 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2217 // If the value fits into a simm10 then we can use ldi.[bhwd]
2218 // However, if it isn't an integer type we will have to bitcast from an
2219 // integer type first. Also, if there are any undefs, we must lower them
2220 // to defined values first.
2221 if (ResTy.isInteger() && !HasAnyUndefs && SplatValue.isSignedIntN(10))
2226 switch (SplatBitSize) {
2230 ViaVecTy = MVT::v16i8;
2233 ViaVecTy = MVT::v8i16;
2236 ViaVecTy = MVT::v4i32;
2239 // There's no fill.d to fall back on for 64-bit values
2243 // SelectionDAG::getConstant will promote SplatValue appropriately.
2244 SDValue Result = DAG.getConstant(SplatValue, ViaVecTy);
2246 // Bitcast to the type we originally wanted
2247 if (ViaVecTy != ResTy)
2248 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
2251 } else if (isSplatVector(Node))
2253 else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
2254 // Use INSERT_VECTOR_ELT operations rather than expand to stores.
2255 // The resulting code is the same length as the expansion, but it doesn't
2256 // use memory operations
2257 EVT ResTy = Node->getValueType(0);
2259 assert(ResTy.isVector());
2261 unsigned NumElts = ResTy.getVectorNumElements();
2262 SDValue Vector = DAG.getUNDEF(ResTy);
2263 for (unsigned i = 0; i < NumElts; ++i) {
2264 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2265 Node->getOperand(i),
2266 DAG.getConstant(i, MVT::i32));
2274 // Lower VECTOR_SHUFFLE into SHF (if possible).
2276 // SHF splits the vector into blocks of four elements, then shuffles these
2277 // elements according to a <4 x i2> constant (encoded as an integer immediate).
2279 // It is therefore possible to lower into SHF when the mask takes the form:
2280 // <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
2281 // When undef's appear they are treated as if they were whatever value is
2282 // necessary in order to fit the above form.
2285 // %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
2286 // <8 x i32> <i32 3, i32 2, i32 1, i32 0,
2287 // i32 7, i32 6, i32 5, i32 4>
2289 // (SHF_H $w0, $w1, 27)
2290 // where the 27 comes from:
2291 // 3 + (2 << 2) + (1 << 4) + (0 << 6)
2292 static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
2293 SmallVector<int, 16> Indices,
2294 SelectionDAG &DAG) {
2295 int SHFIndices[4] = { -1, -1, -1, -1 };
2297 if (Indices.size() < 4)
2300 for (unsigned i = 0; i < 4; ++i) {
2301 for (unsigned j = i; j < Indices.size(); j += 4) {
2302 int Idx = Indices[j];
2304 // Convert from vector index to 4-element subvector index
2305 // If an index refers to an element outside of the subvector then give up
2308 if (Idx < 0 || Idx >= 4)
2312 // If the mask has an undef, replace it with the current index.
2313 // Note that it might still be undef if the current index is also undef
2314 if (SHFIndices[i] == -1)
2315 SHFIndices[i] = Idx;
2317 // Check that non-undef values are the same as in the mask. If they
2318 // aren't then give up
2319 if (!(Idx == -1 || Idx == SHFIndices[i]))
2324 // Calculate the immediate. Replace any remaining undefs with zero
2326 for (int i = 3; i >= 0; --i) {
2327 int Idx = SHFIndices[i];
2336 return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy,
2337 DAG.getConstant(Imm, MVT::i32), Op->getOperand(0));
2340 // Lower VECTOR_SHUFFLE into ILVEV (if possible).
2342 // ILVEV interleaves the even elements from each vector.
2344 // It is possible to lower into ILVEV when the mask takes the form:
2345 // <0, n, 2, n+2, 4, n+4, ...>
2346 // where n is the number of elements in the vector.
2348 // When undef's appear in the mask they are treated as if they were whatever
2349 // value is necessary in order to fit the above form.
2350 static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy,
2351 SmallVector<int, 16> Indices,
2352 SelectionDAG &DAG) {
2353 assert ((Indices.size() % 2) == 0);
2355 int WtIdx = ResTy.getVectorNumElements();
2357 for (unsigned i = 0; i < Indices.size(); i += 2) {
2358 if (Indices[i] != -1 && Indices[i] != WsIdx)
2360 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2366 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Op->getOperand(0),
2370 // Lower VECTOR_SHUFFLE into ILVOD (if possible).
2372 // ILVOD interleaves the odd elements from each vector.
2374 // It is possible to lower into ILVOD when the mask takes the form:
2375 // <1, n+1, 3, n+3, 5, n+5, ...>
2376 // where n is the number of elements in the vector.
2378 // When undef's appear in the mask they are treated as if they were whatever
2379 // value is necessary in order to fit the above form.
2380 static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy,
2381 SmallVector<int, 16> Indices,
2382 SelectionDAG &DAG) {
2383 assert ((Indices.size() % 2) == 0);
2385 int WtIdx = ResTy.getVectorNumElements() + 1;
2387 for (unsigned i = 0; i < Indices.size(); i += 2) {
2388 if (Indices[i] != -1 && Indices[i] != WsIdx)
2390 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2396 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Op->getOperand(0),
2400 // Lower VECTOR_SHUFFLE into ILVL (if possible).
2402 // ILVL interleaves consecutive elements from the left half of each vector.
2404 // It is possible to lower into ILVL when the mask takes the form:
2405 // <0, n, 1, n+1, 2, n+2, ...>
2406 // where n is the number of elements in the vector.
2408 // When undef's appear in the mask they are treated as if they were whatever
2409 // value is necessary in order to fit the above form.
2410 static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy,
2411 SmallVector<int, 16> Indices,
2412 SelectionDAG &DAG) {
2413 assert ((Indices.size() % 2) == 0);
2415 int WtIdx = ResTy.getVectorNumElements();
2417 for (unsigned i = 0; i < Indices.size(); i += 2) {
2418 if (Indices[i] != -1 && Indices[i] != WsIdx)
2420 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2426 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Op->getOperand(0),
2430 // Lower VECTOR_SHUFFLE into ILVR (if possible).
2432 // ILVR interleaves consecutive elements from the right half of each vector.
2434 // It is possible to lower into ILVR when the mask takes the form:
2435 // <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2436 // where n is the number of elements in the vector and x is half n.
2438 // When undef's appear in the mask they are treated as if they were whatever
2439 // value is necessary in order to fit the above form.
2440 static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
2441 SmallVector<int, 16> Indices,
2442 SelectionDAG &DAG) {
2443 assert ((Indices.size() % 2) == 0);
2444 unsigned NumElts = ResTy.getVectorNumElements();
2445 int WsIdx = NumElts / 2;
2446 int WtIdx = NumElts + NumElts / 2;
2448 for (unsigned i = 0; i < Indices.size(); i += 2) {
2449 if (Indices[i] != -1 && Indices[i] != WsIdx)
2451 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2457 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Op->getOperand(0),
2461 // Lower VECTOR_SHUFFLE into PCKEV (if possible).
2463 // PCKEV copies the even elements of each vector into the result vector.
2465 // It is possible to lower into PCKEV when the mask takes the form:
2466 // <0, 2, 4, ..., n, n+2, n+4, ...>
2467 // where n is the number of elements in the vector.
2469 // When undef's appear in the mask they are treated as if they were whatever
2470 // value is necessary in order to fit the above form.
2471 static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy,
2472 SmallVector<int, 16> Indices,
2473 SelectionDAG &DAG) {
2474 assert ((Indices.size() % 2) == 0);
2477 for (unsigned i = 0; i < Indices.size(); ++i) {
2478 if (Indices[i] != -1 && Indices[i] != Idx)
2483 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Op->getOperand(0),
2487 // Lower VECTOR_SHUFFLE into PCKOD (if possible).
2489 // PCKOD copies the odd elements of each vector into the result vector.
2491 // It is possible to lower into PCKOD when the mask takes the form:
2492 // <1, 3, 5, ..., n+1, n+3, n+5, ...>
2493 // where n is the number of elements in the vector.
2495 // When undef's appear in the mask they are treated as if they were whatever
2496 // value is necessary in order to fit the above form.
2497 static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
2498 SmallVector<int, 16> Indices,
2499 SelectionDAG &DAG) {
2500 assert ((Indices.size() % 2) == 0);
2503 for (unsigned i = 0; i < Indices.size(); ++i) {
2504 if (Indices[i] != -1 && Indices[i] != Idx)
2509 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Op->getOperand(0),
2513 // Lower VECTOR_SHUFFLE into VSHF.
2515 // This mostly consists of converting the shuffle indices in Indices into a
2516 // BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2517 // also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2518 // if the type is v8i16 and all the indices are less than 8 then the second
2519 // operand is unused and can be replaced with anything. We choose to replace it
2520 // with the used operand since this reduces the number of instructions overall.
2521 static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
2522 SmallVector<int, 16> Indices,
2523 SelectionDAG &DAG) {
2524 SmallVector<SDValue, 16> Ops;
2527 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2528 EVT MaskEltTy = MaskVecTy.getVectorElementType();
2529 bool Using1stVec = false;
2530 bool Using2ndVec = false;
2532 int ResTyNumElts = ResTy.getVectorNumElements();
2534 for (int i = 0; i < ResTyNumElts; ++i) {
2535 // Idx == -1 means UNDEF
2536 int Idx = Indices[i];
2538 if (0 <= Idx && Idx < ResTyNumElts)
2540 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2544 for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2546 Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy));
2548 SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, &Ops[0],
2551 if (Using1stVec && Using2ndVec) {
2552 Op0 = Op->getOperand(0);
2553 Op1 = Op->getOperand(1);
2554 } else if (Using1stVec)
2555 Op0 = Op1 = Op->getOperand(0);
2556 else if (Using2ndVec)
2557 Op0 = Op1 = Op->getOperand(1);
2559 llvm_unreachable("shuffle vector mask references neither vector operand?");
2561 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op0, Op1);
2564 // Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2565 // indices in the shuffle.
2566 SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2567 SelectionDAG &DAG) const {
2568 ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2569 EVT ResTy = Op->getValueType(0);
2571 if (!ResTy.is128BitVector())
2574 int ResTyNumElts = ResTy.getVectorNumElements();
2575 SmallVector<int, 16> Indices;
2577 for (int i = 0; i < ResTyNumElts; ++i)
2578 Indices.push_back(Node->getMaskElt(i));
2580 SDValue Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG);
2581 if (Result.getNode())
2583 Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG);
2584 if (Result.getNode())
2586 Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG);
2587 if (Result.getNode())
2589 Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG);
2590 if (Result.getNode())
2592 Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG);
2593 if (Result.getNode())
2595 Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG);
2596 if (Result.getNode())
2598 Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG);
2599 if (Result.getNode())
2601 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2604 MachineBasicBlock * MipsSETargetLowering::
2605 emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
2607 // bposge32_pseudo $vr0
2617 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
2619 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2620 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2621 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2622 DebugLoc DL = MI->getDebugLoc();
2623 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2624 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
2625 MachineFunction *F = BB->getParent();
2626 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2627 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2628 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2631 F->insert(It, Sink);
2633 // Transfer the remainder of BB and its successor edges to Sink.
2634 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
2636 Sink->transferSuccessorsAndUpdatePHIs(BB);
2639 BB->addSuccessor(FBB);
2640 BB->addSuccessor(TBB);
2641 FBB->addSuccessor(Sink);
2642 TBB->addSuccessor(Sink);
2644 // Insert the real bposge32 instruction to $BB.
2645 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
2648 unsigned VR2 = RegInfo.createVirtualRegister(RC);
2649 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
2650 .addReg(Mips::ZERO).addImm(0);
2651 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2654 unsigned VR1 = RegInfo.createVirtualRegister(RC);
2655 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
2656 .addReg(Mips::ZERO).addImm(1);
2658 // Insert phi function to $Sink.
2659 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2660 MI->getOperand(0).getReg())
2661 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
2663 MI->eraseFromParent(); // The pseudo instruction is gone now.
2667 MachineBasicBlock * MipsSETargetLowering::
2668 emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
2669 unsigned BranchOp) const{
2671 // vany_nonzero $rd, $ws
2682 // $rd = phi($rd1, $fbb, $rd2, $tbb)
2684 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2685 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2686 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2687 DebugLoc DL = MI->getDebugLoc();
2688 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2689 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
2690 MachineFunction *F = BB->getParent();
2691 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2692 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2693 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2696 F->insert(It, Sink);
2698 // Transfer the remainder of BB and its successor edges to Sink.
2699 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
2701 Sink->transferSuccessorsAndUpdatePHIs(BB);
2704 BB->addSuccessor(FBB);
2705 BB->addSuccessor(TBB);
2706 FBB->addSuccessor(Sink);
2707 TBB->addSuccessor(Sink);
2709 // Insert the real bnz.b instruction to $BB.
2710 BuildMI(BB, DL, TII->get(BranchOp))
2711 .addReg(MI->getOperand(1).getReg())
2715 unsigned RD1 = RegInfo.createVirtualRegister(RC);
2716 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
2717 .addReg(Mips::ZERO).addImm(0);
2718 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2721 unsigned RD2 = RegInfo.createVirtualRegister(RC);
2722 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
2723 .addReg(Mips::ZERO).addImm(1);
2725 // Insert phi function to $Sink.
2726 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2727 MI->getOperand(0).getReg())
2728 .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
2730 MI->eraseFromParent(); // The pseudo instruction is gone now.
2734 // Emit the COPY_FW pseudo instruction.
2736 // copy_fw_pseudo $fd, $ws, n
2738 // copy_u_w $rt, $ws, $n
2741 // When n is zero, the equivalent operation can be performed with (potentially)
2742 // zero instructions due to register overlaps. This optimization is never valid
2743 // for lane 1 because it would require FR=0 mode which isn't supported by MSA.
2744 MachineBasicBlock * MipsSETargetLowering::
2745 emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{
2746 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2747 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2748 DebugLoc DL = MI->getDebugLoc();
2749 unsigned Fd = MI->getOperand(0).getReg();
2750 unsigned Ws = MI->getOperand(1).getReg();
2751 unsigned Lane = MI->getOperand(2).getImm();
2754 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo);
2756 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2758 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(1);
2759 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
2762 MI->eraseFromParent(); // The pseudo instruction is gone now.
2766 // Emit the COPY_FD pseudo instruction.
2768 // copy_fd_pseudo $fd, $ws, n
2770 // splati.d $wt, $ws, $n
2771 // copy $fd, $wt:sub_64
2773 // When n is zero, the equivalent operation can be performed with (potentially)
2774 // zero instructions due to register overlaps. This optimization is always
2775 // valid because FR=1 mode which is the only supported mode in MSA.
2776 MachineBasicBlock * MipsSETargetLowering::
2777 emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{
2778 assert(Subtarget->isFP64bit());
2780 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2781 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2782 unsigned Fd = MI->getOperand(0).getReg();
2783 unsigned Ws = MI->getOperand(1).getReg();
2784 unsigned Lane = MI->getOperand(2).getImm() * 2;
2785 DebugLoc DL = MI->getDebugLoc();
2788 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
2790 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2792 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
2793 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
2796 MI->eraseFromParent(); // The pseudo instruction is gone now.
2800 // Emit the INSERT_FW pseudo instruction.
2802 // insert_fw_pseudo $wd, $wd_in, $n, $fs
2804 // subreg_to_reg $wt:sub_lo, $fs
2805 // insve_w $wd[$n], $wd_in, $wt[0]
2807 MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI,
2808 MachineBasicBlock *BB) const {
2809 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2810 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2811 DebugLoc DL = MI->getDebugLoc();
2812 unsigned Wd = MI->getOperand(0).getReg();
2813 unsigned Wd_in = MI->getOperand(1).getReg();
2814 unsigned Lane = MI->getOperand(2).getImm();
2815 unsigned Fs = MI->getOperand(3).getReg();
2816 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2818 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2821 .addImm(Mips::sub_lo);
2822 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
2827 MI->eraseFromParent(); // The pseudo instruction is gone now.
2831 // Emit the INSERT_FD pseudo instruction.
2833 // insert_fd_pseudo $wd, $fs, n
2835 // subreg_to_reg $wt:sub_64, $fs
2836 // insve_d $wd[$n], $wd_in, $wt[0]
2838 MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI,
2839 MachineBasicBlock *BB) const {
2840 assert(Subtarget->isFP64bit());
2842 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2843 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2844 DebugLoc DL = MI->getDebugLoc();
2845 unsigned Wd = MI->getOperand(0).getReg();
2846 unsigned Wd_in = MI->getOperand(1).getReg();
2847 unsigned Lane = MI->getOperand(2).getImm();
2848 unsigned Fs = MI->getOperand(3).getReg();
2849 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2851 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2854 .addImm(Mips::sub_64);
2855 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
2860 MI->eraseFromParent(); // The pseudo instruction is gone now.
2864 // Emit the FILL_FW pseudo instruction.
2866 // fill_fw_pseudo $wd, $fs
2868 // implicit_def $wt1
2869 // insert_subreg $wt2:subreg_lo, $wt1, $fs
2870 // splati.w $wd, $wt2[0]
2872 MipsSETargetLowering::emitFILL_FW(MachineInstr *MI,
2873 MachineBasicBlock *BB) const {
2874 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2875 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2876 DebugLoc DL = MI->getDebugLoc();
2877 unsigned Wd = MI->getOperand(0).getReg();
2878 unsigned Fs = MI->getOperand(1).getReg();
2879 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2880 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2882 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
2883 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
2886 .addImm(Mips::sub_lo);
2887 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
2889 MI->eraseFromParent(); // The pseudo instruction is gone now.
2893 // Emit the FILL_FD pseudo instruction.
2895 // fill_fd_pseudo $wd, $fs
2897 // implicit_def $wt1
2898 // insert_subreg $wt2:subreg_64, $wt1, $fs
2899 // splati.d $wd, $wt2[0]
2901 MipsSETargetLowering::emitFILL_FD(MachineInstr *MI,
2902 MachineBasicBlock *BB) const {
2903 assert(Subtarget->isFP64bit());
2905 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2906 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2907 DebugLoc DL = MI->getDebugLoc();
2908 unsigned Wd = MI->getOperand(0).getReg();
2909 unsigned Fs = MI->getOperand(1).getReg();
2910 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2911 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2913 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
2914 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
2917 .addImm(Mips::sub_64);
2918 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
2920 MI->eraseFromParent(); // The pseudo instruction is gone now.
2924 // Emit the FEXP2_W_1 pseudo instructions.
2926 // fexp2_w_1_pseudo $wd, $wt
2929 // fexp2.w $wd, $ws, $wt
2931 MipsSETargetLowering::emitFEXP2_W_1(MachineInstr *MI,
2932 MachineBasicBlock *BB) const {
2933 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2934 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2935 const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
2936 unsigned Ws1 = RegInfo.createVirtualRegister(RC);
2937 unsigned Ws2 = RegInfo.createVirtualRegister(RC);
2938 DebugLoc DL = MI->getDebugLoc();
2940 // Splat 1.0 into a vector
2941 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
2942 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
2944 // Emit 1.0 * fexp2(Wt)
2945 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI->getOperand(0).getReg())
2947 .addReg(MI->getOperand(1).getReg());
2949 MI->eraseFromParent(); // The pseudo instruction is gone now.
2953 // Emit the FEXP2_D_1 pseudo instructions.
2955 // fexp2_d_1_pseudo $wd, $wt
2958 // fexp2.d $wd, $ws, $wt
2960 MipsSETargetLowering::emitFEXP2_D_1(MachineInstr *MI,
2961 MachineBasicBlock *BB) const {
2962 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2963 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2964 const TargetRegisterClass *RC = &Mips::MSA128DRegClass;
2965 unsigned Ws1 = RegInfo.createVirtualRegister(RC);
2966 unsigned Ws2 = RegInfo.createVirtualRegister(RC);
2967 DebugLoc DL = MI->getDebugLoc();
2969 // Splat 1.0 into a vector
2970 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
2971 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
2973 // Emit 1.0 * fexp2(Wt)
2974 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI->getOperand(0).getReg())
2976 .addReg(MI->getOperand(1).getReg());
2978 MI->eraseFromParent(); // The pseudo instruction is gone now.