1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
13 #include "MipsSEISelLowering.h"
14 #include "MipsRegisterInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/IR/Intrinsics.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Target/TargetInstrInfo.h"
25 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
26 cl::desc("MIPS: Enable tail calls."), cl::init(false));
28 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
29 cl::desc("Expand double precision loads and "
30 "stores to their single precision "
33 MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
34 : MipsTargetLowering(TM) {
35 // Set up the register classes
36 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
39 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
41 if (Subtarget->hasDSP() || Subtarget->hasMSA()) {
42 // Expand all truncating stores and extending loads.
43 unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
44 unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
46 for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
47 for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
48 setTruncStoreAction((MVT::SimpleValueType)VT0,
49 (MVT::SimpleValueType)VT1, Expand);
51 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
52 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
53 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
57 if (Subtarget->hasDSP()) {
58 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
60 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
61 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
63 // Expand all builtin opcodes.
64 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
65 setOperationAction(Opc, VecTys[i], Expand);
67 setOperationAction(ISD::ADD, VecTys[i], Legal);
68 setOperationAction(ISD::SUB, VecTys[i], Legal);
69 setOperationAction(ISD::LOAD, VecTys[i], Legal);
70 setOperationAction(ISD::STORE, VecTys[i], Legal);
71 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
74 setTargetDAGCombine(ISD::SHL);
75 setTargetDAGCombine(ISD::SRA);
76 setTargetDAGCombine(ISD::SRL);
77 setTargetDAGCombine(ISD::SETCC);
78 setTargetDAGCombine(ISD::VSELECT);
81 if (Subtarget->hasDSPR2())
82 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
84 if (Subtarget->hasMSA()) {
85 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
86 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
87 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
88 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
89 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
90 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
91 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
93 setTargetDAGCombine(ISD::AND);
94 setTargetDAGCombine(ISD::SRA);
95 setTargetDAGCombine(ISD::VSELECT);
96 setTargetDAGCombine(ISD::XOR);
99 if (!Subtarget->mipsSEUsesSoftFloat()) {
100 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
102 // When dealing with single precision only, use libcalls
103 if (!Subtarget->isSingleFloat()) {
104 if (Subtarget->isFP64bit())
105 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
107 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
111 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
112 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
113 setOperationAction(ISD::MULHS, MVT::i32, Custom);
114 setOperationAction(ISD::MULHU, MVT::i32, Custom);
117 setOperationAction(ISD::MULHS, MVT::i64, Custom);
118 setOperationAction(ISD::MULHU, MVT::i64, Custom);
119 setOperationAction(ISD::MUL, MVT::i64, Custom);
122 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
123 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
125 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
126 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
127 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
128 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
129 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
130 setOperationAction(ISD::LOAD, MVT::i32, Custom);
131 setOperationAction(ISD::STORE, MVT::i32, Custom);
133 setTargetDAGCombine(ISD::ADDE);
134 setTargetDAGCombine(ISD::SUBE);
135 setTargetDAGCombine(ISD::MUL);
137 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
138 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
139 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
142 setOperationAction(ISD::LOAD, MVT::f64, Custom);
143 setOperationAction(ISD::STORE, MVT::f64, Custom);
146 computeRegisterProperties();
149 const MipsTargetLowering *
150 llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
151 return new MipsSETargetLowering(TM);
154 // Enable MSA support for the given integer type and Register class.
155 void MipsSETargetLowering::
156 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
157 addRegisterClass(Ty, RC);
159 // Expand all builtin opcodes.
160 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
161 setOperationAction(Opc, Ty, Expand);
163 setOperationAction(ISD::BITCAST, Ty, Legal);
164 setOperationAction(ISD::LOAD, Ty, Legal);
165 setOperationAction(ISD::STORE, Ty, Legal);
166 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
167 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
168 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
170 setOperationAction(ISD::ADD, Ty, Legal);
171 setOperationAction(ISD::AND, Ty, Legal);
172 setOperationAction(ISD::CTLZ, Ty, Legal);
173 setOperationAction(ISD::CTPOP, Ty, Legal);
174 setOperationAction(ISD::MUL, Ty, Legal);
175 setOperationAction(ISD::OR, Ty, Legal);
176 setOperationAction(ISD::SDIV, Ty, Legal);
177 setOperationAction(ISD::SREM, Ty, Legal);
178 setOperationAction(ISD::SHL, Ty, Legal);
179 setOperationAction(ISD::SRA, Ty, Legal);
180 setOperationAction(ISD::SRL, Ty, Legal);
181 setOperationAction(ISD::SUB, Ty, Legal);
182 setOperationAction(ISD::UDIV, Ty, Legal);
183 setOperationAction(ISD::UREM, Ty, Legal);
184 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
185 setOperationAction(ISD::VSELECT, Ty, Legal);
186 setOperationAction(ISD::XOR, Ty, Legal);
188 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
189 setOperationAction(ISD::FP_TO_SINT, Ty, Legal);
190 setOperationAction(ISD::FP_TO_UINT, Ty, Legal);
191 setOperationAction(ISD::SINT_TO_FP, Ty, Legal);
192 setOperationAction(ISD::UINT_TO_FP, Ty, Legal);
195 setOperationAction(ISD::SETCC, Ty, Legal);
196 setCondCodeAction(ISD::SETNE, Ty, Expand);
197 setCondCodeAction(ISD::SETGE, Ty, Expand);
198 setCondCodeAction(ISD::SETGT, Ty, Expand);
199 setCondCodeAction(ISD::SETUGE, Ty, Expand);
200 setCondCodeAction(ISD::SETUGT, Ty, Expand);
203 // Enable MSA support for the given floating-point type and Register class.
204 void MipsSETargetLowering::
205 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
206 addRegisterClass(Ty, RC);
208 // Expand all builtin opcodes.
209 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
210 setOperationAction(Opc, Ty, Expand);
212 setOperationAction(ISD::LOAD, Ty, Legal);
213 setOperationAction(ISD::STORE, Ty, Legal);
214 setOperationAction(ISD::BITCAST, Ty, Legal);
215 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
216 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
217 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
219 if (Ty != MVT::v8f16) {
220 setOperationAction(ISD::FABS, Ty, Legal);
221 setOperationAction(ISD::FADD, Ty, Legal);
222 setOperationAction(ISD::FDIV, Ty, Legal);
223 setOperationAction(ISD::FLOG2, Ty, Legal);
224 setOperationAction(ISD::FMA, Ty, Legal);
225 setOperationAction(ISD::FMUL, Ty, Legal);
226 setOperationAction(ISD::FRINT, Ty, Legal);
227 setOperationAction(ISD::FSQRT, Ty, Legal);
228 setOperationAction(ISD::FSUB, Ty, Legal);
229 setOperationAction(ISD::VSELECT, Ty, Legal);
231 setOperationAction(ISD::SETCC, Ty, Legal);
232 setCondCodeAction(ISD::SETOGE, Ty, Expand);
233 setCondCodeAction(ISD::SETOGT, Ty, Expand);
234 setCondCodeAction(ISD::SETUGE, Ty, Expand);
235 setCondCodeAction(ISD::SETUGT, Ty, Expand);
236 setCondCodeAction(ISD::SETGE, Ty, Expand);
237 setCondCodeAction(ISD::SETGT, Ty, Expand);
242 MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
243 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
256 SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
257 SelectionDAG &DAG) const {
258 switch(Op.getOpcode()) {
259 case ISD::LOAD: return lowerLOAD(Op, DAG);
260 case ISD::STORE: return lowerSTORE(Op, DAG);
261 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
262 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
263 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
264 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
265 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
266 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
267 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
269 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
270 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
271 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
272 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
273 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
274 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
277 return MipsTargetLowering::LowerOperation(Op, DAG);
281 // Transforms a subgraph in CurDAG if the following pattern is found:
282 // (addc multLo, Lo0), (adde multHi, Hi0),
284 // multHi/Lo: product of multiplication
285 // Lo0: initial value of Lo register
286 // Hi0: initial value of Hi register
287 // Return true if pattern matching was successful.
288 static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
289 // ADDENode's second operand must be a flag output of an ADDC node in order
290 // for the matching to be successful.
291 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
293 if (ADDCNode->getOpcode() != ISD::ADDC)
296 SDValue MultHi = ADDENode->getOperand(0);
297 SDValue MultLo = ADDCNode->getOperand(0);
298 SDNode *MultNode = MultHi.getNode();
299 unsigned MultOpc = MultHi.getOpcode();
301 // MultHi and MultLo must be generated by the same node,
302 if (MultLo.getNode() != MultNode)
305 // and it must be a multiplication.
306 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
309 // MultLo amd MultHi must be the first and second output of MultNode
311 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
314 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
315 // of the values of MultNode, in which case MultNode will be removed in later
317 // If there exist users other than ADDENode or ADDCNode, this function returns
318 // here, which will result in MultNode being mapped to a single MULT
319 // instruction node rather than a pair of MULT and MADD instructions being
321 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
326 // Initialize accumulator.
327 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
328 ADDCNode->getOperand(1),
329 ADDENode->getOperand(1));
331 // create MipsMAdd(u) node
332 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
334 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
335 MultNode->getOperand(0),// Factor 0
336 MultNode->getOperand(1),// Factor 1
339 // replace uses of adde and addc here
340 if (!SDValue(ADDCNode, 0).use_empty()) {
341 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
342 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
344 if (!SDValue(ADDENode, 0).use_empty()) {
345 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
346 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
353 // Transforms a subgraph in CurDAG if the following pattern is found:
354 // (addc Lo0, multLo), (sube Hi0, multHi),
356 // multHi/Lo: product of multiplication
357 // Lo0: initial value of Lo register
358 // Hi0: initial value of Hi register
359 // Return true if pattern matching was successful.
360 static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
361 // SUBENode's second operand must be a flag output of an SUBC node in order
362 // for the matching to be successful.
363 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
365 if (SUBCNode->getOpcode() != ISD::SUBC)
368 SDValue MultHi = SUBENode->getOperand(1);
369 SDValue MultLo = SUBCNode->getOperand(1);
370 SDNode *MultNode = MultHi.getNode();
371 unsigned MultOpc = MultHi.getOpcode();
373 // MultHi and MultLo must be generated by the same node,
374 if (MultLo.getNode() != MultNode)
377 // and it must be a multiplication.
378 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
381 // MultLo amd MultHi must be the first and second output of MultNode
383 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
386 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
387 // of the values of MultNode, in which case MultNode will be removed in later
389 // If there exist users other than SUBENode or SUBCNode, this function returns
390 // here, which will result in MultNode being mapped to a single MULT
391 // instruction node rather than a pair of MULT and MSUB instructions being
393 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
398 // Initialize accumulator.
399 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
400 SUBCNode->getOperand(0),
401 SUBENode->getOperand(0));
403 // create MipsSub(u) node
404 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
406 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
407 MultNode->getOperand(0),// Factor 0
408 MultNode->getOperand(1),// Factor 1
411 // replace uses of sube and subc here
412 if (!SDValue(SUBCNode, 0).use_empty()) {
413 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub);
414 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
416 if (!SDValue(SUBENode, 0).use_empty()) {
417 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub);
418 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
424 static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
425 TargetLowering::DAGCombinerInfo &DCI,
426 const MipsSubtarget *Subtarget) {
427 if (DCI.isBeforeLegalize())
430 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
432 return SDValue(N, 0);
437 // Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
439 // Performs the following transformations:
440 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
441 // sign/zero-extension is completely overwritten by the new one performed by
443 // - Removes redundant zero extensions performed by an ISD::AND.
444 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
445 TargetLowering::DAGCombinerInfo &DCI,
446 const MipsSubtarget *Subtarget) {
447 if (!Subtarget->hasMSA())
450 SDValue Op0 = N->getOperand(0);
451 SDValue Op1 = N->getOperand(1);
452 unsigned Op0Opcode = Op0->getOpcode();
454 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
455 // where $d + 1 == 2^n and n == 32
456 // or $d + 1 == 2^n and n <= 32 and ZExt
457 // -> (MipsVExtractZExt $a, $b, $c)
458 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
459 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
460 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
465 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
467 if (Log2IfPositive <= 0)
468 return SDValue(); // Mask+1 is not a power of 2
470 SDValue Op0Op2 = Op0->getOperand(2);
471 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
472 unsigned ExtendTySize = ExtendTy.getSizeInBits();
473 unsigned Log2 = Log2IfPositive;
475 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
476 Log2 == ExtendTySize) {
477 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
478 DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT,
479 Op0->getVTList(), Ops, Op0->getNumOperands());
487 static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
488 TargetLowering::DAGCombinerInfo &DCI,
489 const MipsSubtarget *Subtarget) {
490 if (DCI.isBeforeLegalize())
493 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
495 return SDValue(N, 0);
500 static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
501 EVT ShiftTy, SelectionDAG &DAG) {
502 // Clear the upper (64 - VT.sizeInBits) bits.
503 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
507 return DAG.getConstant(0, VT);
513 // If c is power of 2, return (shl x, log2(c)).
514 if (isPowerOf2_64(C))
515 return DAG.getNode(ISD::SHL, DL, VT, X,
516 DAG.getConstant(Log2_64(C), ShiftTy));
518 unsigned Log2Ceil = Log2_64_Ceil(C);
519 uint64_t Floor = 1LL << Log2_64(C);
520 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
522 // If |c - floor_c| <= |c - ceil_c|,
523 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
524 // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
525 if (C - Floor <= Ceil - C) {
526 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
527 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
528 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
531 // If |c - floor_c| > |c - ceil_c|,
532 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
533 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
534 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
535 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
538 static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
539 const TargetLowering::DAGCombinerInfo &DCI,
540 const MipsSETargetLowering *TL) {
541 EVT VT = N->getValueType(0);
543 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
545 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
546 VT, TL->getScalarShiftAmountTy(VT), DAG);
548 return SDValue(N, 0);
551 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
553 const MipsSubtarget *Subtarget) {
554 // See if this is a vector splat immediate node.
555 APInt SplatValue, SplatUndef;
556 unsigned SplatBitSize;
558 unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
559 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
562 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
563 EltSize, !Subtarget->isLittle()) ||
564 (SplatBitSize != EltSize) ||
565 (SplatValue.getZExtValue() >= EltSize))
568 return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
569 DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
572 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
573 TargetLowering::DAGCombinerInfo &DCI,
574 const MipsSubtarget *Subtarget) {
575 EVT Ty = N->getValueType(0);
577 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
580 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
583 // Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
584 // constant splats into MipsISD::SHRA_DSP for DSPr2.
586 // Performs the following transformations:
587 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
588 // sign/zero-extension is completely overwritten by the new one performed by
589 // the ISD::SRA and ISD::SHL nodes.
590 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
593 // See performDSPShiftCombine for more information about the transformation
595 static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
596 TargetLowering::DAGCombinerInfo &DCI,
597 const MipsSubtarget *Subtarget) {
598 EVT Ty = N->getValueType(0);
600 if (Subtarget->hasMSA()) {
601 SDValue Op0 = N->getOperand(0);
602 SDValue Op1 = N->getOperand(1);
604 // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
605 // where $d + sizeof($c) == 32
606 // or $d + sizeof($c) <= 32 and SExt
607 // -> (MipsVExtractSExt $a, $b, $c)
608 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
609 SDValue Op0Op0 = Op0->getOperand(0);
610 ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
615 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
616 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)
619 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
620 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
622 if (TotalBits == 32 ||
623 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
625 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
626 Op0Op0->getOperand(2) };
627 DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT,
628 Op0Op0->getVTList(), Ops, Op0Op0->getNumOperands());
634 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
637 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
641 static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
642 TargetLowering::DAGCombinerInfo &DCI,
643 const MipsSubtarget *Subtarget) {
644 EVT Ty = N->getValueType(0);
646 if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
649 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
652 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
653 bool IsV216 = (Ty == MVT::v2i16);
657 case ISD::SETNE: return true;
661 case ISD::SETGE: return IsV216;
665 case ISD::SETUGE: return !IsV216;
666 default: return false;
670 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
671 EVT Ty = N->getValueType(0);
673 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
676 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
679 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
680 N->getOperand(1), N->getOperand(2));
683 static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
684 EVT Ty = N->getValueType(0);
686 if (Ty.is128BitVector() && Ty.isInteger()) {
687 // Try the following combines:
688 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
689 // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
690 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
691 // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
692 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
693 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
694 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
695 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
696 // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
697 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
699 SDValue Op0 = N->getOperand(0);
701 if (Op0->getOpcode() != ISD::SETCC)
704 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
707 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE)
709 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
714 SDValue Op1 = N->getOperand(1);
715 SDValue Op2 = N->getOperand(2);
716 SDValue Op0Op0 = Op0->getOperand(0);
717 SDValue Op0Op1 = Op0->getOperand(1);
719 if (Op1 == Op0Op0 && Op2 == Op0Op1)
720 return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
722 else if (Op1 == Op0Op1 && Op2 == Op0Op0)
723 return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
725 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
726 SDValue SetCC = N->getOperand(0);
728 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
731 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
732 SetCC.getOperand(0), SetCC.getOperand(1),
733 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
739 static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
740 const MipsSubtarget *Subtarget) {
741 EVT Ty = N->getValueType(0);
743 if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
744 // Try the following combines:
745 // (xor (or $a, $b), (build_vector allones))
746 // (xor (or $a, $b), (bitcast (build_vector allones)))
747 SDValue Op0 = N->getOperand(0);
748 SDValue Op1 = N->getOperand(1);
751 if (ISD::isBuildVectorAllOnes(Op0.getNode()))
753 else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
758 if (NotOp->getOpcode() == ISD::OR)
759 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
760 NotOp->getOperand(1));
767 MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
768 SelectionDAG &DAG = DCI.DAG;
771 switch (N->getOpcode()) {
773 return performADDECombine(N, DAG, DCI, Subtarget);
775 Val = performANDCombine(N, DAG, DCI, Subtarget);
778 return performSUBECombine(N, DAG, DCI, Subtarget);
780 return performMULCombine(N, DAG, DCI, this);
782 return performSHLCombine(N, DAG, DCI, Subtarget);
784 return performSRACombine(N, DAG, DCI, Subtarget);
786 return performSRLCombine(N, DAG, DCI, Subtarget);
788 return performVSELECTCombine(N, DAG);
790 Val = performXORCombine(N, DAG, Subtarget);
793 Val = performSETCCCombine(N, DAG);
800 return MipsTargetLowering::PerformDAGCombine(N, DCI);
804 MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
805 MachineBasicBlock *BB) const {
806 switch (MI->getOpcode()) {
808 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
809 case Mips::BPOSGE32_PSEUDO:
810 return emitBPOSGE32(MI, BB);
811 case Mips::SNZ_B_PSEUDO:
812 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
813 case Mips::SNZ_H_PSEUDO:
814 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
815 case Mips::SNZ_W_PSEUDO:
816 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
817 case Mips::SNZ_D_PSEUDO:
818 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
819 case Mips::SNZ_V_PSEUDO:
820 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
821 case Mips::SZ_B_PSEUDO:
822 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
823 case Mips::SZ_H_PSEUDO:
824 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
825 case Mips::SZ_W_PSEUDO:
826 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
827 case Mips::SZ_D_PSEUDO:
828 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
829 case Mips::SZ_V_PSEUDO:
830 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
831 case Mips::COPY_FW_PSEUDO:
832 return emitCOPY_FW(MI, BB);
833 case Mips::COPY_FD_PSEUDO:
834 return emitCOPY_FD(MI, BB);
835 case Mips::INSERT_FW_PSEUDO:
836 return emitINSERT_FW(MI, BB);
837 case Mips::INSERT_FD_PSEUDO:
838 return emitINSERT_FD(MI, BB);
839 case Mips::FILL_FW_PSEUDO:
840 return emitFILL_FW(MI, BB);
841 case Mips::FILL_FD_PSEUDO:
842 return emitFILL_FD(MI, BB);
846 bool MipsSETargetLowering::
847 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
848 unsigned NextStackOffset,
849 const MipsFunctionInfo& FI) const {
850 if (!EnableMipsTailCalls)
853 // Return false if either the callee or caller has a byval argument.
854 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
857 // Return true if the callee's argument area is no larger than the
859 return NextStackOffset <= FI.getIncomingArgSize();
862 void MipsSETargetLowering::
863 getOpndList(SmallVectorImpl<SDValue> &Ops,
864 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
865 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
866 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
867 // T9 should contain the address of the callee function if
868 // -reloction-model=pic or it is an indirect call.
869 if (IsPICCall || !GlobalOrExternal) {
870 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
871 RegsToPass.push_front(std::make_pair(T9Reg, Callee));
873 Ops.push_back(Callee);
875 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
876 InternalLinkage, CLI, Callee, Chain);
879 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
880 LoadSDNode &Nd = *cast<LoadSDNode>(Op);
882 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
883 return MipsTargetLowering::lowerLOAD(Op, DAG);
885 // Replace a double precision load with two i32 loads and a buildpair64.
887 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
888 EVT PtrVT = Ptr.getValueType();
890 // i32 load from lower address.
891 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
892 MachinePointerInfo(), Nd.isVolatile(),
893 Nd.isNonTemporal(), Nd.isInvariant(),
896 // i32 load from higher address.
897 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
898 SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
899 MachinePointerInfo(), Nd.isVolatile(),
900 Nd.isNonTemporal(), Nd.isInvariant(),
901 std::min(Nd.getAlignment(), 4U));
903 if (!Subtarget->isLittle())
906 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
907 SDValue Ops[2] = {BP, Hi.getValue(1)};
908 return DAG.getMergeValues(Ops, 2, DL);
911 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
912 StoreSDNode &Nd = *cast<StoreSDNode>(Op);
914 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
915 return MipsTargetLowering::lowerSTORE(Op, DAG);
917 // Replace a double precision store with two extractelement64s and i32 stores.
919 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
920 EVT PtrVT = Ptr.getValueType();
921 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
922 Val, DAG.getConstant(0, MVT::i32));
923 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
924 Val, DAG.getConstant(1, MVT::i32));
926 if (!Subtarget->isLittle())
929 // i32 store to lower address.
930 Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
931 Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
934 // i32 store to higher address.
935 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
936 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
937 Nd.isVolatile(), Nd.isNonTemporal(),
938 std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo());
941 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
942 bool HasLo, bool HasHi,
943 SelectionDAG &DAG) const {
944 EVT Ty = Op.getOperand(0).getValueType();
946 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
947 Op.getOperand(0), Op.getOperand(1));
951 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);
953 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);
955 if (!HasLo || !HasHi)
956 return HasLo ? Lo : Hi;
958 SDValue Vals[] = { Lo, Hi };
959 return DAG.getMergeValues(Vals, 2, DL);
963 static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
964 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
965 DAG.getConstant(0, MVT::i32));
966 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
967 DAG.getConstant(1, MVT::i32));
968 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
971 static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
972 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op);
973 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op);
974 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
977 // This function expands mips intrinsic nodes which have 64-bit input operands
980 // out64 = intrinsic-node in64
982 // lo = copy (extract-element (in64, 0))
983 // hi = copy (extract-element (in64, 1))
984 // mips-specific-node
987 // out64 = merge-values (v0, v1)
989 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
991 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
992 SmallVector<SDValue, 3> Ops;
995 // See if Op has a chain input.
997 Ops.push_back(Op->getOperand(OpNo++));
999 // The next operand is the intrinsic opcode.
1000 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
1002 // See if the next operand has type i64.
1003 SDValue Opnd = Op->getOperand(++OpNo), In64;
1005 if (Opnd.getValueType() == MVT::i64)
1006 In64 = initAccumulator(Opnd, DL, DAG);
1008 Ops.push_back(Opnd);
1010 // Push the remaining operands.
1011 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1012 Ops.push_back(Op->getOperand(OpNo));
1014 // Add In64 to the end of the list.
1016 Ops.push_back(In64);
1019 SmallVector<EVT, 2> ResTys;
1021 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1023 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1026 SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
1027 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1032 assert(Val->getValueType(1) == MVT::Other);
1033 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1034 return DAG.getMergeValues(Vals, 2, DL);
1037 // Lower an MSA copy intrinsic into the specified SelectionDAG node
1038 static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1040 SDValue Vec = Op->getOperand(1);
1041 SDValue Idx = Op->getOperand(2);
1042 EVT ResTy = Op->getValueType(0);
1043 EVT EltTy = Vec->getValueType(0).getVectorElementType();
1045 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1046 DAG.getValueType(EltTy));
1052 lowerMSASplatImm(SDLoc DL, EVT ResTy, SDValue ImmOp, SelectionDAG &DAG) {
1053 EVT ViaVecTy = ResTy;
1054 SmallVector<SDValue, 16> Ops;
1057 if (ViaVecTy == MVT::v2i64) {
1058 ImmHiOp = DAG.getNode(ISD::SRA, DL, MVT::i32, ImmOp,
1059 DAG.getConstant(31, MVT::i32));
1060 for (unsigned i = 0; i < ViaVecTy.getVectorNumElements(); ++i) {
1061 Ops.push_back(ImmHiOp);
1062 Ops.push_back(ImmOp);
1064 ViaVecTy = MVT::v4i32;
1066 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1067 Ops.push_back(ImmOp);
1070 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, &Ops[0],
1073 if (ResTy != ViaVecTy)
1074 Result = DAG.getNode(ISD::BITCAST, DL, ResTy, Result);
1080 lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
1081 return lowerMSASplatImm(SDLoc(Op), Op->getValueType(0),
1082 Op->getOperand(ImmOp), DAG);
1085 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1086 SelectionDAG &DAG) const {
1089 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
1092 case Intrinsic::mips_shilo:
1093 return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1094 case Intrinsic::mips_dpau_h_qbl:
1095 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1096 case Intrinsic::mips_dpau_h_qbr:
1097 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1098 case Intrinsic::mips_dpsu_h_qbl:
1099 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1100 case Intrinsic::mips_dpsu_h_qbr:
1101 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1102 case Intrinsic::mips_dpa_w_ph:
1103 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1104 case Intrinsic::mips_dps_w_ph:
1105 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1106 case Intrinsic::mips_dpax_w_ph:
1107 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1108 case Intrinsic::mips_dpsx_w_ph:
1109 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1110 case Intrinsic::mips_mulsa_w_ph:
1111 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1112 case Intrinsic::mips_mult:
1113 return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1114 case Intrinsic::mips_multu:
1115 return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1116 case Intrinsic::mips_madd:
1117 return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1118 case Intrinsic::mips_maddu:
1119 return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1120 case Intrinsic::mips_msub:
1121 return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1122 case Intrinsic::mips_msubu:
1123 return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1124 case Intrinsic::mips_addv_b:
1125 case Intrinsic::mips_addv_h:
1126 case Intrinsic::mips_addv_w:
1127 case Intrinsic::mips_addv_d:
1128 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1130 case Intrinsic::mips_addvi_b:
1131 case Intrinsic::mips_addvi_h:
1132 case Intrinsic::mips_addvi_w:
1133 case Intrinsic::mips_addvi_d:
1134 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1135 lowerMSASplatImm(Op, 2, DAG));
1136 case Intrinsic::mips_and_v:
1137 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1139 case Intrinsic::mips_andi_b:
1140 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1141 lowerMSASplatImm(Op, 2, DAG));
1142 case Intrinsic::mips_bnz_b:
1143 case Intrinsic::mips_bnz_h:
1144 case Intrinsic::mips_bnz_w:
1145 case Intrinsic::mips_bnz_d:
1146 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1148 case Intrinsic::mips_bnz_v:
1149 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1151 case Intrinsic::mips_bsel_v:
1152 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1153 Op->getOperand(1), Op->getOperand(2),
1155 case Intrinsic::mips_bseli_b:
1156 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1157 Op->getOperand(1), Op->getOperand(2),
1158 lowerMSASplatImm(Op, 3, DAG));
1159 case Intrinsic::mips_bz_b:
1160 case Intrinsic::mips_bz_h:
1161 case Intrinsic::mips_bz_w:
1162 case Intrinsic::mips_bz_d:
1163 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1165 case Intrinsic::mips_bz_v:
1166 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1168 case Intrinsic::mips_ceq_b:
1169 case Intrinsic::mips_ceq_h:
1170 case Intrinsic::mips_ceq_w:
1171 case Intrinsic::mips_ceq_d:
1172 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1173 Op->getOperand(2), ISD::SETEQ);
1174 case Intrinsic::mips_ceqi_b:
1175 case Intrinsic::mips_ceqi_h:
1176 case Intrinsic::mips_ceqi_w:
1177 case Intrinsic::mips_ceqi_d:
1178 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1179 lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ);
1180 case Intrinsic::mips_cle_s_b:
1181 case Intrinsic::mips_cle_s_h:
1182 case Intrinsic::mips_cle_s_w:
1183 case Intrinsic::mips_cle_s_d:
1184 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1185 Op->getOperand(2), ISD::SETLE);
1186 case Intrinsic::mips_clei_s_b:
1187 case Intrinsic::mips_clei_s_h:
1188 case Intrinsic::mips_clei_s_w:
1189 case Intrinsic::mips_clei_s_d:
1190 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1191 lowerMSASplatImm(Op, 2, DAG), ISD::SETLE);
1192 case Intrinsic::mips_cle_u_b:
1193 case Intrinsic::mips_cle_u_h:
1194 case Intrinsic::mips_cle_u_w:
1195 case Intrinsic::mips_cle_u_d:
1196 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1197 Op->getOperand(2), ISD::SETULE);
1198 case Intrinsic::mips_clei_u_b:
1199 case Intrinsic::mips_clei_u_h:
1200 case Intrinsic::mips_clei_u_w:
1201 case Intrinsic::mips_clei_u_d:
1202 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1203 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1204 case Intrinsic::mips_clt_s_b:
1205 case Intrinsic::mips_clt_s_h:
1206 case Intrinsic::mips_clt_s_w:
1207 case Intrinsic::mips_clt_s_d:
1208 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1209 Op->getOperand(2), ISD::SETLT);
1210 case Intrinsic::mips_clti_s_b:
1211 case Intrinsic::mips_clti_s_h:
1212 case Intrinsic::mips_clti_s_w:
1213 case Intrinsic::mips_clti_s_d:
1214 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1215 lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);
1216 case Intrinsic::mips_clt_u_b:
1217 case Intrinsic::mips_clt_u_h:
1218 case Intrinsic::mips_clt_u_w:
1219 case Intrinsic::mips_clt_u_d:
1220 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1221 Op->getOperand(2), ISD::SETULT);
1222 case Intrinsic::mips_clti_u_b:
1223 case Intrinsic::mips_clti_u_h:
1224 case Intrinsic::mips_clti_u_w:
1225 case Intrinsic::mips_clti_u_d:
1226 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1227 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1228 case Intrinsic::mips_copy_s_b:
1229 case Intrinsic::mips_copy_s_h:
1230 case Intrinsic::mips_copy_s_w:
1231 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1232 case Intrinsic::mips_copy_s_d:
1233 // Don't lower directly into VEXTRACT_SEXT_ELT since i64 might be illegal.
1234 // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type
1235 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1236 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1237 Op->getOperand(1), Op->getOperand(2));
1238 case Intrinsic::mips_copy_u_b:
1239 case Intrinsic::mips_copy_u_h:
1240 case Intrinsic::mips_copy_u_w:
1241 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1242 case Intrinsic::mips_copy_u_d:
1243 // Don't lower directly into VEXTRACT_ZEXT_ELT since i64 might be illegal.
1244 // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type
1245 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1247 // Note: When i64 is illegal, this results in copy_s.w instructions instead
1248 // of copy_u.w instructions. This makes no difference to the behaviour
1249 // since i64 is only illegal when the register file is 32-bit.
1250 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1251 Op->getOperand(1), Op->getOperand(2));
1252 case Intrinsic::mips_div_s_b:
1253 case Intrinsic::mips_div_s_h:
1254 case Intrinsic::mips_div_s_w:
1255 case Intrinsic::mips_div_s_d:
1256 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1258 case Intrinsic::mips_div_u_b:
1259 case Intrinsic::mips_div_u_h:
1260 case Intrinsic::mips_div_u_w:
1261 case Intrinsic::mips_div_u_d:
1262 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1264 case Intrinsic::mips_fadd_w:
1265 case Intrinsic::mips_fadd_d:
1266 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1268 // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1269 case Intrinsic::mips_fceq_w:
1270 case Intrinsic::mips_fceq_d:
1271 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1272 Op->getOperand(2), ISD::SETOEQ);
1273 case Intrinsic::mips_fcle_w:
1274 case Intrinsic::mips_fcle_d:
1275 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1276 Op->getOperand(2), ISD::SETOLE);
1277 case Intrinsic::mips_fclt_w:
1278 case Intrinsic::mips_fclt_d:
1279 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1280 Op->getOperand(2), ISD::SETOLT);
1281 case Intrinsic::mips_fcne_w:
1282 case Intrinsic::mips_fcne_d:
1283 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1284 Op->getOperand(2), ISD::SETONE);
1285 case Intrinsic::mips_fcor_w:
1286 case Intrinsic::mips_fcor_d:
1287 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1288 Op->getOperand(2), ISD::SETO);
1289 case Intrinsic::mips_fcueq_w:
1290 case Intrinsic::mips_fcueq_d:
1291 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1292 Op->getOperand(2), ISD::SETUEQ);
1293 case Intrinsic::mips_fcule_w:
1294 case Intrinsic::mips_fcule_d:
1295 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1296 Op->getOperand(2), ISD::SETULE);
1297 case Intrinsic::mips_fcult_w:
1298 case Intrinsic::mips_fcult_d:
1299 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1300 Op->getOperand(2), ISD::SETULT);
1301 case Intrinsic::mips_fcun_w:
1302 case Intrinsic::mips_fcun_d:
1303 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1304 Op->getOperand(2), ISD::SETUO);
1305 case Intrinsic::mips_fcune_w:
1306 case Intrinsic::mips_fcune_d:
1307 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1308 Op->getOperand(2), ISD::SETUNE);
1309 case Intrinsic::mips_fdiv_w:
1310 case Intrinsic::mips_fdiv_d:
1311 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1313 case Intrinsic::mips_ffint_u_w:
1314 case Intrinsic::mips_ffint_u_d:
1315 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1317 case Intrinsic::mips_ffint_s_w:
1318 case Intrinsic::mips_ffint_s_d:
1319 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1321 case Intrinsic::mips_fill_b:
1322 case Intrinsic::mips_fill_h:
1323 case Intrinsic::mips_fill_w:
1324 case Intrinsic::mips_fill_d: {
1325 SmallVector<SDValue, 16> Ops;
1326 EVT ResTy = Op->getValueType(0);
1328 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1329 Ops.push_back(Op->getOperand(1));
1331 // If ResTy is v2i64 then the type legalizer will break this node down into
1332 // an equivalent v4i32.
1333 return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, &Ops[0], Ops.size());
1335 case Intrinsic::mips_flog2_w:
1336 case Intrinsic::mips_flog2_d:
1337 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1338 case Intrinsic::mips_fmadd_w:
1339 case Intrinsic::mips_fmadd_d:
1340 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1341 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1342 case Intrinsic::mips_fmul_w:
1343 case Intrinsic::mips_fmul_d:
1344 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1346 case Intrinsic::mips_fmsub_w:
1347 case Intrinsic::mips_fmsub_d: {
1348 EVT ResTy = Op->getValueType(0);
1349 return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
1350 DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,
1351 Op->getOperand(2), Op->getOperand(3)));
1353 case Intrinsic::mips_frint_w:
1354 case Intrinsic::mips_frint_d:
1355 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1356 case Intrinsic::mips_fsqrt_w:
1357 case Intrinsic::mips_fsqrt_d:
1358 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1359 case Intrinsic::mips_fsub_w:
1360 case Intrinsic::mips_fsub_d:
1361 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1363 case Intrinsic::mips_ftrunc_u_w:
1364 case Intrinsic::mips_ftrunc_u_d:
1365 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1367 case Intrinsic::mips_ftrunc_s_w:
1368 case Intrinsic::mips_ftrunc_s_d:
1369 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1371 case Intrinsic::mips_ilvev_b:
1372 case Intrinsic::mips_ilvev_h:
1373 case Intrinsic::mips_ilvev_w:
1374 case Intrinsic::mips_ilvev_d:
1375 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
1376 Op->getOperand(1), Op->getOperand(2));
1377 case Intrinsic::mips_ilvl_b:
1378 case Intrinsic::mips_ilvl_h:
1379 case Intrinsic::mips_ilvl_w:
1380 case Intrinsic::mips_ilvl_d:
1381 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
1382 Op->getOperand(1), Op->getOperand(2));
1383 case Intrinsic::mips_ilvod_b:
1384 case Intrinsic::mips_ilvod_h:
1385 case Intrinsic::mips_ilvod_w:
1386 case Intrinsic::mips_ilvod_d:
1387 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
1388 Op->getOperand(1), Op->getOperand(2));
1389 case Intrinsic::mips_ilvr_b:
1390 case Intrinsic::mips_ilvr_h:
1391 case Intrinsic::mips_ilvr_w:
1392 case Intrinsic::mips_ilvr_d:
1393 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
1394 Op->getOperand(1), Op->getOperand(2));
1395 case Intrinsic::mips_insert_b:
1396 case Intrinsic::mips_insert_h:
1397 case Intrinsic::mips_insert_w:
1398 case Intrinsic::mips_insert_d:
1399 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1400 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1401 case Intrinsic::mips_ldi_b:
1402 case Intrinsic::mips_ldi_h:
1403 case Intrinsic::mips_ldi_w:
1404 case Intrinsic::mips_ldi_d:
1405 return lowerMSASplatImm(Op, 1, DAG);
1406 case Intrinsic::mips_maddv_b:
1407 case Intrinsic::mips_maddv_h:
1408 case Intrinsic::mips_maddv_w:
1409 case Intrinsic::mips_maddv_d: {
1410 EVT ResTy = Op->getValueType(0);
1411 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1412 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1413 Op->getOperand(2), Op->getOperand(3)));
1415 case Intrinsic::mips_max_s_b:
1416 case Intrinsic::mips_max_s_h:
1417 case Intrinsic::mips_max_s_w:
1418 case Intrinsic::mips_max_s_d:
1419 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1420 Op->getOperand(1), Op->getOperand(2));
1421 case Intrinsic::mips_max_u_b:
1422 case Intrinsic::mips_max_u_h:
1423 case Intrinsic::mips_max_u_w:
1424 case Intrinsic::mips_max_u_d:
1425 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1426 Op->getOperand(1), Op->getOperand(2));
1427 case Intrinsic::mips_maxi_s_b:
1428 case Intrinsic::mips_maxi_s_h:
1429 case Intrinsic::mips_maxi_s_w:
1430 case Intrinsic::mips_maxi_s_d:
1431 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1432 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1433 case Intrinsic::mips_maxi_u_b:
1434 case Intrinsic::mips_maxi_u_h:
1435 case Intrinsic::mips_maxi_u_w:
1436 case Intrinsic::mips_maxi_u_d:
1437 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1438 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1439 case Intrinsic::mips_min_s_b:
1440 case Intrinsic::mips_min_s_h:
1441 case Intrinsic::mips_min_s_w:
1442 case Intrinsic::mips_min_s_d:
1443 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1444 Op->getOperand(1), Op->getOperand(2));
1445 case Intrinsic::mips_min_u_b:
1446 case Intrinsic::mips_min_u_h:
1447 case Intrinsic::mips_min_u_w:
1448 case Intrinsic::mips_min_u_d:
1449 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1450 Op->getOperand(1), Op->getOperand(2));
1451 case Intrinsic::mips_mini_s_b:
1452 case Intrinsic::mips_mini_s_h:
1453 case Intrinsic::mips_mini_s_w:
1454 case Intrinsic::mips_mini_s_d:
1455 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1456 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1457 case Intrinsic::mips_mini_u_b:
1458 case Intrinsic::mips_mini_u_h:
1459 case Intrinsic::mips_mini_u_w:
1460 case Intrinsic::mips_mini_u_d:
1461 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1462 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1463 case Intrinsic::mips_mod_s_b:
1464 case Intrinsic::mips_mod_s_h:
1465 case Intrinsic::mips_mod_s_w:
1466 case Intrinsic::mips_mod_s_d:
1467 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
1469 case Intrinsic::mips_mod_u_b:
1470 case Intrinsic::mips_mod_u_h:
1471 case Intrinsic::mips_mod_u_w:
1472 case Intrinsic::mips_mod_u_d:
1473 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
1475 case Intrinsic::mips_mulv_b:
1476 case Intrinsic::mips_mulv_h:
1477 case Intrinsic::mips_mulv_w:
1478 case Intrinsic::mips_mulv_d:
1479 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
1481 case Intrinsic::mips_msubv_b:
1482 case Intrinsic::mips_msubv_h:
1483 case Intrinsic::mips_msubv_w:
1484 case Intrinsic::mips_msubv_d: {
1485 EVT ResTy = Op->getValueType(0);
1486 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
1487 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1488 Op->getOperand(2), Op->getOperand(3)));
1490 case Intrinsic::mips_nlzc_b:
1491 case Intrinsic::mips_nlzc_h:
1492 case Intrinsic::mips_nlzc_w:
1493 case Intrinsic::mips_nlzc_d:
1494 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
1495 case Intrinsic::mips_nor_v: {
1496 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1497 Op->getOperand(1), Op->getOperand(2));
1498 return DAG.getNOT(DL, Res, Res->getValueType(0));
1500 case Intrinsic::mips_nori_b: {
1501 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1503 lowerMSASplatImm(Op, 2, DAG));
1504 return DAG.getNOT(DL, Res, Res->getValueType(0));
1506 case Intrinsic::mips_or_v:
1507 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
1509 case Intrinsic::mips_ori_b:
1510 return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1511 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1512 case Intrinsic::mips_pckev_b:
1513 case Intrinsic::mips_pckev_h:
1514 case Intrinsic::mips_pckev_w:
1515 case Intrinsic::mips_pckev_d:
1516 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
1517 Op->getOperand(1), Op->getOperand(2));
1518 case Intrinsic::mips_pckod_b:
1519 case Intrinsic::mips_pckod_h:
1520 case Intrinsic::mips_pckod_w:
1521 case Intrinsic::mips_pckod_d:
1522 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
1523 Op->getOperand(1), Op->getOperand(2));
1524 case Intrinsic::mips_pcnt_b:
1525 case Intrinsic::mips_pcnt_h:
1526 case Intrinsic::mips_pcnt_w:
1527 case Intrinsic::mips_pcnt_d:
1528 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
1529 case Intrinsic::mips_shf_b:
1530 case Intrinsic::mips_shf_h:
1531 case Intrinsic::mips_shf_w:
1532 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
1533 Op->getOperand(2), Op->getOperand(1));
1534 case Intrinsic::mips_sll_b:
1535 case Intrinsic::mips_sll_h:
1536 case Intrinsic::mips_sll_w:
1537 case Intrinsic::mips_sll_d:
1538 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
1540 case Intrinsic::mips_slli_b:
1541 case Intrinsic::mips_slli_h:
1542 case Intrinsic::mips_slli_w:
1543 case Intrinsic::mips_slli_d:
1544 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
1545 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1546 case Intrinsic::mips_splati_b:
1547 case Intrinsic::mips_splati_h:
1548 case Intrinsic::mips_splati_w:
1549 case Intrinsic::mips_splati_d:
1550 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1551 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
1553 case Intrinsic::mips_sra_b:
1554 case Intrinsic::mips_sra_h:
1555 case Intrinsic::mips_sra_w:
1556 case Intrinsic::mips_sra_d:
1557 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
1559 case Intrinsic::mips_srai_b:
1560 case Intrinsic::mips_srai_h:
1561 case Intrinsic::mips_srai_w:
1562 case Intrinsic::mips_srai_d:
1563 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
1564 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1565 case Intrinsic::mips_srl_b:
1566 case Intrinsic::mips_srl_h:
1567 case Intrinsic::mips_srl_w:
1568 case Intrinsic::mips_srl_d:
1569 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
1571 case Intrinsic::mips_srli_b:
1572 case Intrinsic::mips_srli_h:
1573 case Intrinsic::mips_srli_w:
1574 case Intrinsic::mips_srli_d:
1575 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
1576 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1577 case Intrinsic::mips_subv_b:
1578 case Intrinsic::mips_subv_h:
1579 case Intrinsic::mips_subv_w:
1580 case Intrinsic::mips_subv_d:
1581 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
1583 case Intrinsic::mips_subvi_b:
1584 case Intrinsic::mips_subvi_h:
1585 case Intrinsic::mips_subvi_w:
1586 case Intrinsic::mips_subvi_d:
1587 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
1588 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1589 case Intrinsic::mips_vshf_b:
1590 case Intrinsic::mips_vshf_h:
1591 case Intrinsic::mips_vshf_w:
1592 case Intrinsic::mips_vshf_d:
1593 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1594 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1595 case Intrinsic::mips_xor_v:
1596 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
1598 case Intrinsic::mips_xori_b:
1599 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
1600 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1604 static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1606 SDValue ChainIn = Op->getOperand(0);
1607 SDValue Address = Op->getOperand(2);
1608 SDValue Offset = Op->getOperand(3);
1609 EVT ResTy = Op->getValueType(0);
1610 EVT PtrTy = Address->getValueType(0);
1612 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1614 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
1618 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
1619 SelectionDAG &DAG) const {
1620 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1624 case Intrinsic::mips_extp:
1625 return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
1626 case Intrinsic::mips_extpdp:
1627 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
1628 case Intrinsic::mips_extr_w:
1629 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
1630 case Intrinsic::mips_extr_r_w:
1631 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
1632 case Intrinsic::mips_extr_rs_w:
1633 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
1634 case Intrinsic::mips_extr_s_h:
1635 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
1636 case Intrinsic::mips_mthlip:
1637 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
1638 case Intrinsic::mips_mulsaq_s_w_ph:
1639 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
1640 case Intrinsic::mips_maq_s_w_phl:
1641 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
1642 case Intrinsic::mips_maq_s_w_phr:
1643 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
1644 case Intrinsic::mips_maq_sa_w_phl:
1645 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
1646 case Intrinsic::mips_maq_sa_w_phr:
1647 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
1648 case Intrinsic::mips_dpaq_s_w_ph:
1649 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
1650 case Intrinsic::mips_dpsq_s_w_ph:
1651 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
1652 case Intrinsic::mips_dpaq_sa_l_w:
1653 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
1654 case Intrinsic::mips_dpsq_sa_l_w:
1655 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
1656 case Intrinsic::mips_dpaqx_s_w_ph:
1657 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
1658 case Intrinsic::mips_dpaqx_sa_w_ph:
1659 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
1660 case Intrinsic::mips_dpsqx_s_w_ph:
1661 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
1662 case Intrinsic::mips_dpsqx_sa_w_ph:
1663 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
1664 case Intrinsic::mips_ld_b:
1665 case Intrinsic::mips_ld_h:
1666 case Intrinsic::mips_ld_w:
1667 case Intrinsic::mips_ld_d:
1668 case Intrinsic::mips_ldx_b:
1669 case Intrinsic::mips_ldx_h:
1670 case Intrinsic::mips_ldx_w:
1671 case Intrinsic::mips_ldx_d:
1672 return lowerMSALoadIntr(Op, DAG, Intr);
1676 static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1678 SDValue ChainIn = Op->getOperand(0);
1679 SDValue Value = Op->getOperand(2);
1680 SDValue Address = Op->getOperand(3);
1681 SDValue Offset = Op->getOperand(4);
1682 EVT PtrTy = Address->getValueType(0);
1684 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1686 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
1690 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
1691 SelectionDAG &DAG) const {
1692 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1696 case Intrinsic::mips_st_b:
1697 case Intrinsic::mips_st_h:
1698 case Intrinsic::mips_st_w:
1699 case Intrinsic::mips_st_d:
1700 case Intrinsic::mips_stx_b:
1701 case Intrinsic::mips_stx_h:
1702 case Intrinsic::mips_stx_w:
1703 case Intrinsic::mips_stx_d:
1704 return lowerMSAStoreIntr(Op, DAG, Intr);
1708 /// \brief Check if the given BuildVectorSDNode is a splat.
1709 /// This method currently relies on DAG nodes being reused when equivalent,
1710 /// so it's possible for this to return false even when isConstantSplat returns
1712 static bool isSplatVector(const BuildVectorSDNode *N) {
1713 unsigned int nOps = N->getNumOperands();
1714 assert(nOps > 1 && "isSplat has 0 or 1 sized build vector");
1716 SDValue Operand0 = N->getOperand(0);
1718 for (unsigned int i = 1; i < nOps; ++i) {
1719 if (N->getOperand(i) != Operand0)
1726 // Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
1728 // The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
1729 // choose to sign-extend but we could have equally chosen zero-extend. The
1730 // DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
1731 // result into this node later (possibly changing it to a zero-extend in the
1733 SDValue MipsSETargetLowering::
1734 lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
1736 EVT ResTy = Op->getValueType(0);
1737 SDValue Op0 = Op->getOperand(0);
1738 EVT VecTy = Op0->getValueType(0);
1740 if (!VecTy.is128BitVector())
1743 if (ResTy.isInteger()) {
1744 SDValue Op1 = Op->getOperand(1);
1745 EVT EltTy = VecTy.getVectorElementType();
1746 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
1747 DAG.getValueType(EltTy));
1753 static bool isConstantOrUndef(const SDValue Op) {
1754 if (Op->getOpcode() == ISD::UNDEF)
1756 if (dyn_cast<ConstantSDNode>(Op))
1758 if (dyn_cast<ConstantFPSDNode>(Op))
1763 static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) {
1764 for (unsigned i = 0; i < Op->getNumOperands(); ++i)
1765 if (isConstantOrUndef(Op->getOperand(i)))
1770 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
1773 // Lowers according to the following rules:
1774 // - Constant splats are legal as-is as long as the SplatBitSize is a power of
1775 // 2 less than or equal to 64 and the value fits into a signed 10-bit
1777 // - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
1778 // is a power of 2 less than or equal to 64 and the value does not fit into a
1779 // signed 10-bit immediate
1780 // - Non-constant splats are legal as-is.
1781 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
1782 // - All others are illegal and must be expanded.
1783 SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
1784 SelectionDAG &DAG) const {
1785 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
1786 EVT ResTy = Op->getValueType(0);
1788 APInt SplatValue, SplatUndef;
1789 unsigned SplatBitSize;
1792 if (!Subtarget->hasMSA() || !ResTy.is128BitVector())
1795 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
1797 !Subtarget->isLittle()) && SplatBitSize <= 64) {
1798 // We can only cope with 8, 16, 32, or 64-bit elements
1799 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
1803 // If the value fits into a simm10 then we can use ldi.[bhwd]
1804 if (SplatValue.isSignedIntN(10))
1809 switch (SplatBitSize) {
1813 ViaVecTy = MVT::v16i8;
1816 ViaVecTy = MVT::v8i16;
1819 ViaVecTy = MVT::v4i32;
1822 // There's no fill.d to fall back on for 64-bit values
1826 SmallVector<SDValue, 16> Ops;
1827 SDValue Constant = DAG.getConstant(SplatValue.sextOrSelf(32), MVT::i32);
1829 for (unsigned i = 0; i < ViaVecTy.getVectorNumElements(); ++i)
1830 Ops.push_back(Constant);
1832 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Node), ViaVecTy,
1833 &Ops[0], Ops.size());
1835 if (ViaVecTy != ResTy)
1836 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
1839 } else if (isSplatVector(Node))
1841 else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
1842 // Use INSERT_VECTOR_ELT operations rather than expand to stores.
1843 // The resulting code is the same length as the expansion, but it doesn't
1844 // use memory operations
1845 EVT ResTy = Node->getValueType(0);
1847 assert(ResTy.isVector());
1849 unsigned NumElts = ResTy.getVectorNumElements();
1850 SDValue Vector = DAG.getUNDEF(ResTy);
1851 for (unsigned i = 0; i < NumElts; ++i) {
1852 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
1853 Node->getOperand(i),
1854 DAG.getConstant(i, MVT::i32));
1862 // Lower VECTOR_SHUFFLE into SHF (if possible).
1864 // SHF splits the vector into blocks of four elements, then shuffles these
1865 // elements according to a <4 x i2> constant (encoded as an integer immediate).
1867 // It is therefore possible to lower into SHF when the mask takes the form:
1868 // <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
1869 // When undef's appear they are treated as if they were whatever value is
1870 // necessary in order to fit the above form.
1873 // %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
1874 // <8 x i32> <i32 3, i32 2, i32 1, i32 0,
1875 // i32 7, i32 6, i32 5, i32 4>
1877 // (SHF_H $w0, $w1, 27)
1878 // where the 27 comes from:
1879 // 3 + (2 << 2) + (1 << 4) + (0 << 6)
1880 static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
1881 SmallVector<int, 16> Indices,
1882 SelectionDAG &DAG) {
1883 int SHFIndices[4] = { -1, -1, -1, -1 };
1885 if (Indices.size() < 4)
1888 for (unsigned i = 0; i < 4; ++i) {
1889 for (unsigned j = i; j < Indices.size(); j += 4) {
1890 int Idx = Indices[j];
1892 // Convert from vector index to 4-element subvector index
1893 // If an index refers to an element outside of the subvector then give up
1896 if (Idx < 0 || Idx >= 4)
1900 // If the mask has an undef, replace it with the current index.
1901 // Note that it might still be undef if the current index is also undef
1902 if (SHFIndices[i] == -1)
1903 SHFIndices[i] = Idx;
1905 // Check that non-undef values are the same as in the mask. If they
1906 // aren't then give up
1907 if (!(Idx == -1 || Idx == SHFIndices[i]))
1912 // Calculate the immediate. Replace any remaining undefs with zero
1914 for (int i = 3; i >= 0; --i) {
1915 int Idx = SHFIndices[i];
1924 return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy,
1925 DAG.getConstant(Imm, MVT::i32), Op->getOperand(0));
1928 // Lower VECTOR_SHUFFLE into ILVEV (if possible).
1930 // ILVEV interleaves the even elements from each vector.
1932 // It is possible to lower into ILVEV when the mask takes the form:
1933 // <0, n, 2, n+2, 4, n+4, ...>
1934 // where n is the number of elements in the vector.
1936 // When undef's appear in the mask they are treated as if they were whatever
1937 // value is necessary in order to fit the above form.
1938 static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy,
1939 SmallVector<int, 16> Indices,
1940 SelectionDAG &DAG) {
1941 assert ((Indices.size() % 2) == 0);
1943 int WtIdx = ResTy.getVectorNumElements();
1945 for (unsigned i = 0; i < Indices.size(); i += 2) {
1946 if (Indices[i] != -1 && Indices[i] != WsIdx)
1948 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
1954 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Op->getOperand(0),
1958 // Lower VECTOR_SHUFFLE into ILVOD (if possible).
1960 // ILVOD interleaves the odd elements from each vector.
1962 // It is possible to lower into ILVOD when the mask takes the form:
1963 // <1, n+1, 3, n+3, 5, n+5, ...>
1964 // where n is the number of elements in the vector.
1966 // When undef's appear in the mask they are treated as if they were whatever
1967 // value is necessary in order to fit the above form.
1968 static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy,
1969 SmallVector<int, 16> Indices,
1970 SelectionDAG &DAG) {
1971 assert ((Indices.size() % 2) == 0);
1973 int WtIdx = ResTy.getVectorNumElements() + 1;
1975 for (unsigned i = 0; i < Indices.size(); i += 2) {
1976 if (Indices[i] != -1 && Indices[i] != WsIdx)
1978 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
1984 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Op->getOperand(0),
1988 // Lower VECTOR_SHUFFLE into ILVL (if possible).
1990 // ILVL interleaves consecutive elements from the left half of each vector.
1992 // It is possible to lower into ILVL when the mask takes the form:
1993 // <0, n, 1, n+1, 2, n+2, ...>
1994 // where n is the number of elements in the vector.
1996 // When undef's appear in the mask they are treated as if they were whatever
1997 // value is necessary in order to fit the above form.
1998 static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy,
1999 SmallVector<int, 16> Indices,
2000 SelectionDAG &DAG) {
2001 assert ((Indices.size() % 2) == 0);
2003 int WtIdx = ResTy.getVectorNumElements();
2005 for (unsigned i = 0; i < Indices.size(); i += 2) {
2006 if (Indices[i] != -1 && Indices[i] != WsIdx)
2008 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2014 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Op->getOperand(0),
2018 // Lower VECTOR_SHUFFLE into ILVR (if possible).
2020 // ILVR interleaves consecutive elements from the right half of each vector.
2022 // It is possible to lower into ILVR when the mask takes the form:
2023 // <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2024 // where n is the number of elements in the vector and x is half n.
2026 // When undef's appear in the mask they are treated as if they were whatever
2027 // value is necessary in order to fit the above form.
2028 static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
2029 SmallVector<int, 16> Indices,
2030 SelectionDAG &DAG) {
2031 assert ((Indices.size() % 2) == 0);
2032 unsigned NumElts = ResTy.getVectorNumElements();
2033 int WsIdx = NumElts / 2;
2034 int WtIdx = NumElts + NumElts / 2;
2036 for (unsigned i = 0; i < Indices.size(); i += 2) {
2037 if (Indices[i] != -1 && Indices[i] != WsIdx)
2039 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2045 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Op->getOperand(0),
2049 // Lower VECTOR_SHUFFLE into PCKEV (if possible).
2051 // PCKEV copies the even elements of each vector into the result vector.
2053 // It is possible to lower into PCKEV when the mask takes the form:
2054 // <0, 2, 4, ..., n, n+2, n+4, ...>
2055 // where n is the number of elements in the vector.
2057 // When undef's appear in the mask they are treated as if they were whatever
2058 // value is necessary in order to fit the above form.
2059 static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy,
2060 SmallVector<int, 16> Indices,
2061 SelectionDAG &DAG) {
2062 assert ((Indices.size() % 2) == 0);
2065 for (unsigned i = 0; i < Indices.size(); ++i) {
2066 if (Indices[i] != -1 && Indices[i] != Idx)
2071 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Op->getOperand(0),
2075 // Lower VECTOR_SHUFFLE into PCKOD (if possible).
2077 // PCKOD copies the odd elements of each vector into the result vector.
2079 // It is possible to lower into PCKOD when the mask takes the form:
2080 // <1, 3, 5, ..., n+1, n+3, n+5, ...>
2081 // where n is the number of elements in the vector.
2083 // When undef's appear in the mask they are treated as if they were whatever
2084 // value is necessary in order to fit the above form.
2085 static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
2086 SmallVector<int, 16> Indices,
2087 SelectionDAG &DAG) {
2088 assert ((Indices.size() % 2) == 0);
2091 for (unsigned i = 0; i < Indices.size(); ++i) {
2092 if (Indices[i] != -1 && Indices[i] != Idx)
2097 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Op->getOperand(0),
2101 // Lower VECTOR_SHUFFLE into VSHF.
2103 // This mostly consists of converting the shuffle indices in Indices into a
2104 // BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2105 // also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2106 // if the type is v8i16 and all the indices are less than 8 then the second
2107 // operand is unused and can be replaced with anything. We choose to replace it
2108 // with the used operand since this reduces the number of instructions overall.
2109 static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
2110 SmallVector<int, 16> Indices,
2111 SelectionDAG &DAG) {
2112 SmallVector<SDValue, 16> Ops;
2115 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2116 EVT MaskEltTy = MaskVecTy.getVectorElementType();
2117 bool Using1stVec = false;
2118 bool Using2ndVec = false;
2120 int ResTyNumElts = ResTy.getVectorNumElements();
2122 for (int i = 0; i < ResTyNumElts; ++i) {
2123 // Idx == -1 means UNDEF
2124 int Idx = Indices[i];
2126 if (0 <= Idx && Idx < ResTyNumElts)
2128 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2132 for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2134 Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy));
2136 SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, &Ops[0],
2139 if (Using1stVec && Using2ndVec) {
2140 Op0 = Op->getOperand(0);
2141 Op1 = Op->getOperand(1);
2142 } else if (Using1stVec)
2143 Op0 = Op1 = Op->getOperand(0);
2144 else if (Using2ndVec)
2145 Op0 = Op1 = Op->getOperand(1);
2147 llvm_unreachable("shuffle vector mask references neither vector operand?");
2149 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op0, Op1);
2152 // Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2153 // indices in the shuffle.
2154 SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2155 SelectionDAG &DAG) const {
2156 ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2157 EVT ResTy = Op->getValueType(0);
2159 if (!ResTy.is128BitVector())
2162 int ResTyNumElts = ResTy.getVectorNumElements();
2163 SmallVector<int, 16> Indices;
2165 for (int i = 0; i < ResTyNumElts; ++i)
2166 Indices.push_back(Node->getMaskElt(i));
2168 SDValue Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG);
2169 if (Result.getNode())
2171 Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG);
2172 if (Result.getNode())
2174 Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG);
2175 if (Result.getNode())
2177 Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG);
2178 if (Result.getNode())
2180 Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG);
2181 if (Result.getNode())
2183 Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG);
2184 if (Result.getNode())
2186 Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG);
2187 if (Result.getNode())
2189 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2192 MachineBasicBlock * MipsSETargetLowering::
2193 emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
2195 // bposge32_pseudo $vr0
2205 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
2207 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2208 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2209 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2210 DebugLoc DL = MI->getDebugLoc();
2211 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2212 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
2213 MachineFunction *F = BB->getParent();
2214 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2215 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2216 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2219 F->insert(It, Sink);
2221 // Transfer the remainder of BB and its successor edges to Sink.
2222 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
2224 Sink->transferSuccessorsAndUpdatePHIs(BB);
2227 BB->addSuccessor(FBB);
2228 BB->addSuccessor(TBB);
2229 FBB->addSuccessor(Sink);
2230 TBB->addSuccessor(Sink);
2232 // Insert the real bposge32 instruction to $BB.
2233 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
2236 unsigned VR2 = RegInfo.createVirtualRegister(RC);
2237 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
2238 .addReg(Mips::ZERO).addImm(0);
2239 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2242 unsigned VR1 = RegInfo.createVirtualRegister(RC);
2243 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
2244 .addReg(Mips::ZERO).addImm(1);
2246 // Insert phi function to $Sink.
2247 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2248 MI->getOperand(0).getReg())
2249 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
2251 MI->eraseFromParent(); // The pseudo instruction is gone now.
2255 MachineBasicBlock * MipsSETargetLowering::
2256 emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
2257 unsigned BranchOp) const{
2259 // vany_nonzero $rd, $ws
2270 // $rd = phi($rd1, $fbb, $rd2, $tbb)
2272 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2273 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2274 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2275 DebugLoc DL = MI->getDebugLoc();
2276 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2277 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
2278 MachineFunction *F = BB->getParent();
2279 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2280 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2281 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2284 F->insert(It, Sink);
2286 // Transfer the remainder of BB and its successor edges to Sink.
2287 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
2289 Sink->transferSuccessorsAndUpdatePHIs(BB);
2292 BB->addSuccessor(FBB);
2293 BB->addSuccessor(TBB);
2294 FBB->addSuccessor(Sink);
2295 TBB->addSuccessor(Sink);
2297 // Insert the real bnz.b instruction to $BB.
2298 BuildMI(BB, DL, TII->get(BranchOp))
2299 .addReg(MI->getOperand(1).getReg())
2303 unsigned RD1 = RegInfo.createVirtualRegister(RC);
2304 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
2305 .addReg(Mips::ZERO).addImm(0);
2306 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2309 unsigned RD2 = RegInfo.createVirtualRegister(RC);
2310 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
2311 .addReg(Mips::ZERO).addImm(1);
2313 // Insert phi function to $Sink.
2314 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2315 MI->getOperand(0).getReg())
2316 .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
2318 MI->eraseFromParent(); // The pseudo instruction is gone now.
2322 // Emit the COPY_FW pseudo instruction.
2324 // copy_fw_pseudo $fd, $ws, n
2326 // copy_u_w $rt, $ws, $n
2329 // When n is zero, the equivalent operation can be performed with (potentially)
2330 // zero instructions due to register overlaps. This optimization is never valid
2331 // for lane 1 because it would require FR=0 mode which isn't supported by MSA.
2332 MachineBasicBlock * MipsSETargetLowering::
2333 emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{
2334 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2335 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2336 DebugLoc DL = MI->getDebugLoc();
2337 unsigned Fd = MI->getOperand(0).getReg();
2338 unsigned Ws = MI->getOperand(1).getReg();
2339 unsigned Lane = MI->getOperand(2).getImm();
2342 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo);
2344 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2346 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(1);
2347 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
2350 MI->eraseFromParent(); // The pseudo instruction is gone now.
2354 // Emit the COPY_FD pseudo instruction.
2356 // copy_fd_pseudo $fd, $ws, n
2358 // splati.d $wt, $ws, $n
2359 // copy $fd, $wt:sub_64
2361 // When n is zero, the equivalent operation can be performed with (potentially)
2362 // zero instructions due to register overlaps. This optimization is always
2363 // valid because FR=1 mode which is the only supported mode in MSA.
2364 MachineBasicBlock * MipsSETargetLowering::
2365 emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{
2366 assert(Subtarget->isFP64bit());
2368 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2369 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2370 unsigned Fd = MI->getOperand(0).getReg();
2371 unsigned Ws = MI->getOperand(1).getReg();
2372 unsigned Lane = MI->getOperand(2).getImm() * 2;
2373 DebugLoc DL = MI->getDebugLoc();
2376 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
2378 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2380 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
2381 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
2384 MI->eraseFromParent(); // The pseudo instruction is gone now.
2388 // Emit the INSERT_FW pseudo instruction.
2390 // insert_fw_pseudo $wd, $wd_in, $n, $fs
2392 // subreg_to_reg $wt:sub_lo, $fs
2393 // insve_w $wd[$n], $wd_in, $wt[0]
2395 MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI,
2396 MachineBasicBlock *BB) const {
2397 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2398 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2399 DebugLoc DL = MI->getDebugLoc();
2400 unsigned Wd = MI->getOperand(0).getReg();
2401 unsigned Wd_in = MI->getOperand(1).getReg();
2402 unsigned Lane = MI->getOperand(2).getImm();
2403 unsigned Fs = MI->getOperand(3).getReg();
2404 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2406 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2409 .addImm(Mips::sub_lo);
2410 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
2415 MI->eraseFromParent(); // The pseudo instruction is gone now.
2419 // Emit the INSERT_FD pseudo instruction.
2421 // insert_fd_pseudo $wd, $fs, n
2423 // subreg_to_reg $wt:sub_64, $fs
2424 // insve_d $wd[$n], $wd_in, $wt[0]
2426 MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI,
2427 MachineBasicBlock *BB) const {
2428 assert(Subtarget->isFP64bit());
2430 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2431 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2432 DebugLoc DL = MI->getDebugLoc();
2433 unsigned Wd = MI->getOperand(0).getReg();
2434 unsigned Wd_in = MI->getOperand(1).getReg();
2435 unsigned Lane = MI->getOperand(2).getImm();
2436 unsigned Fs = MI->getOperand(3).getReg();
2437 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2439 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2442 .addImm(Mips::sub_64);
2443 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
2448 MI->eraseFromParent(); // The pseudo instruction is gone now.
2452 // Emit the FILL_FW pseudo instruction.
2454 // fill_fw_pseudo $wd, $fs
2456 // implicit_def $wt1
2457 // insert_subreg $wt2:subreg_lo, $wt1, $fs
2458 // splati.w $wd, $wt2[0]
2460 MipsSETargetLowering::emitFILL_FW(MachineInstr *MI,
2461 MachineBasicBlock *BB) const {
2462 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2463 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2464 DebugLoc DL = MI->getDebugLoc();
2465 unsigned Wd = MI->getOperand(0).getReg();
2466 unsigned Fs = MI->getOperand(1).getReg();
2467 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2468 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2470 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
2471 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
2474 .addImm(Mips::sub_lo);
2475 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
2477 MI->eraseFromParent(); // The pseudo instruction is gone now.
2481 // Emit the FILL_FD pseudo instruction.
2483 // fill_fd_pseudo $wd, $fs
2485 // implicit_def $wt1
2486 // insert_subreg $wt2:subreg_64, $wt1, $fs
2487 // splati.d $wd, $wt2[0]
2489 MipsSETargetLowering::emitFILL_FD(MachineInstr *MI,
2490 MachineBasicBlock *BB) const {
2491 assert(Subtarget->isFP64bit());
2493 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2494 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2495 DebugLoc DL = MI->getDebugLoc();
2496 unsigned Wd = MI->getOperand(0).getReg();
2497 unsigned Fs = MI->getOperand(1).getReg();
2498 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2499 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2501 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
2502 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
2505 .addImm(Mips::sub_64);
2506 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
2508 MI->eraseFromParent(); // The pseudo instruction is gone now.