1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
13 #include "MipsSEISelLowering.h"
14 #include "MipsRegisterInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/IR/Intrinsics.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Target/TargetInstrInfo.h"
25 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
26 cl::desc("MIPS: Enable tail calls."), cl::init(false));
28 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
29 cl::desc("Expand double precision loads and "
30 "stores to their single precision "
33 MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
34 : MipsTargetLowering(TM) {
35 // Set up the register classes
37 clearRegisterClasses();
39 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
42 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
44 if (Subtarget->hasDSP() || Subtarget->hasMSA()) {
45 // Expand all truncating stores and extending loads.
46 unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
47 unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
49 for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
50 for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
51 setTruncStoreAction((MVT::SimpleValueType)VT0,
52 (MVT::SimpleValueType)VT1, Expand);
54 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
55 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
56 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
60 if (Subtarget->hasDSP()) {
61 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
63 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
64 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
66 // Expand all builtin opcodes.
67 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
68 setOperationAction(Opc, VecTys[i], Expand);
70 setOperationAction(ISD::ADD, VecTys[i], Legal);
71 setOperationAction(ISD::SUB, VecTys[i], Legal);
72 setOperationAction(ISD::LOAD, VecTys[i], Legal);
73 setOperationAction(ISD::STORE, VecTys[i], Legal);
74 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
77 setTargetDAGCombine(ISD::SHL);
78 setTargetDAGCombine(ISD::SRA);
79 setTargetDAGCombine(ISD::SRL);
80 setTargetDAGCombine(ISD::SETCC);
81 setTargetDAGCombine(ISD::VSELECT);
84 if (Subtarget->hasDSPR2())
85 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
87 if (Subtarget->hasMSA()) {
88 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
89 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
90 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
91 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
92 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
93 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
94 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
96 setTargetDAGCombine(ISD::AND);
97 setTargetDAGCombine(ISD::SRA);
98 setTargetDAGCombine(ISD::VSELECT);
99 setTargetDAGCombine(ISD::XOR);
102 if (!Subtarget->mipsSEUsesSoftFloat()) {
103 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
105 // When dealing with single precision only, use libcalls
106 if (!Subtarget->isSingleFloat()) {
107 if (Subtarget->isFP64bit())
108 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
110 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
114 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
115 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
116 setOperationAction(ISD::MULHS, MVT::i32, Custom);
117 setOperationAction(ISD::MULHU, MVT::i32, Custom);
120 setOperationAction(ISD::MULHS, MVT::i64, Custom);
121 setOperationAction(ISD::MULHU, MVT::i64, Custom);
122 setOperationAction(ISD::MUL, MVT::i64, Custom);
125 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
126 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
128 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
129 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
130 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
131 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
132 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
133 setOperationAction(ISD::LOAD, MVT::i32, Custom);
134 setOperationAction(ISD::STORE, MVT::i32, Custom);
136 setTargetDAGCombine(ISD::ADDE);
137 setTargetDAGCombine(ISD::SUBE);
138 setTargetDAGCombine(ISD::MUL);
140 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
141 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
142 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
145 setOperationAction(ISD::LOAD, MVT::f64, Custom);
146 setOperationAction(ISD::STORE, MVT::f64, Custom);
149 computeRegisterProperties();
152 const MipsTargetLowering *
153 llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
154 return new MipsSETargetLowering(TM);
157 // Enable MSA support for the given integer type and Register class.
158 void MipsSETargetLowering::
159 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
160 addRegisterClass(Ty, RC);
162 // Expand all builtin opcodes.
163 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
164 setOperationAction(Opc, Ty, Expand);
166 setOperationAction(ISD::BITCAST, Ty, Legal);
167 setOperationAction(ISD::LOAD, Ty, Legal);
168 setOperationAction(ISD::STORE, Ty, Legal);
169 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
170 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
171 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
173 setOperationAction(ISD::ADD, Ty, Legal);
174 setOperationAction(ISD::AND, Ty, Legal);
175 setOperationAction(ISD::CTLZ, Ty, Legal);
176 setOperationAction(ISD::CTPOP, Ty, Legal);
177 setOperationAction(ISD::MUL, Ty, Legal);
178 setOperationAction(ISD::OR, Ty, Legal);
179 setOperationAction(ISD::SDIV, Ty, Legal);
180 setOperationAction(ISD::SREM, Ty, Legal);
181 setOperationAction(ISD::SHL, Ty, Legal);
182 setOperationAction(ISD::SRA, Ty, Legal);
183 setOperationAction(ISD::SRL, Ty, Legal);
184 setOperationAction(ISD::SUB, Ty, Legal);
185 setOperationAction(ISD::UDIV, Ty, Legal);
186 setOperationAction(ISD::UREM, Ty, Legal);
187 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
188 setOperationAction(ISD::VSELECT, Ty, Legal);
189 setOperationAction(ISD::XOR, Ty, Legal);
191 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
192 setOperationAction(ISD::FP_TO_SINT, Ty, Legal);
193 setOperationAction(ISD::FP_TO_UINT, Ty, Legal);
194 setOperationAction(ISD::SINT_TO_FP, Ty, Legal);
195 setOperationAction(ISD::UINT_TO_FP, Ty, Legal);
198 setOperationAction(ISD::SETCC, Ty, Legal);
199 setCondCodeAction(ISD::SETNE, Ty, Expand);
200 setCondCodeAction(ISD::SETGE, Ty, Expand);
201 setCondCodeAction(ISD::SETGT, Ty, Expand);
202 setCondCodeAction(ISD::SETUGE, Ty, Expand);
203 setCondCodeAction(ISD::SETUGT, Ty, Expand);
206 // Enable MSA support for the given floating-point type and Register class.
207 void MipsSETargetLowering::
208 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
209 addRegisterClass(Ty, RC);
211 // Expand all builtin opcodes.
212 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
213 setOperationAction(Opc, Ty, Expand);
215 setOperationAction(ISD::LOAD, Ty, Legal);
216 setOperationAction(ISD::STORE, Ty, Legal);
217 setOperationAction(ISD::BITCAST, Ty, Legal);
218 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
219 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
221 if (Ty != MVT::v8f16) {
222 setOperationAction(ISD::FABS, Ty, Legal);
223 setOperationAction(ISD::FADD, Ty, Legal);
224 setOperationAction(ISD::FDIV, Ty, Legal);
225 setOperationAction(ISD::FLOG2, Ty, Legal);
226 setOperationAction(ISD::FMUL, Ty, Legal);
227 setOperationAction(ISD::FRINT, Ty, Legal);
228 setOperationAction(ISD::FSQRT, Ty, Legal);
229 setOperationAction(ISD::FSUB, Ty, Legal);
230 setOperationAction(ISD::VSELECT, Ty, Legal);
232 setOperationAction(ISD::SETCC, Ty, Legal);
233 setCondCodeAction(ISD::SETOGE, Ty, Expand);
234 setCondCodeAction(ISD::SETOGT, Ty, Expand);
235 setCondCodeAction(ISD::SETUGE, Ty, Expand);
236 setCondCodeAction(ISD::SETUGT, Ty, Expand);
237 setCondCodeAction(ISD::SETGE, Ty, Expand);
238 setCondCodeAction(ISD::SETGT, Ty, Expand);
243 MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
244 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
257 SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
258 SelectionDAG &DAG) const {
259 switch(Op.getOpcode()) {
260 case ISD::LOAD: return lowerLOAD(Op, DAG);
261 case ISD::STORE: return lowerSTORE(Op, DAG);
262 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
263 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
264 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
265 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
266 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
267 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
268 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
270 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
271 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
272 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
273 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
274 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
275 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
278 return MipsTargetLowering::LowerOperation(Op, DAG);
282 // Transforms a subgraph in CurDAG if the following pattern is found:
283 // (addc multLo, Lo0), (adde multHi, Hi0),
285 // multHi/Lo: product of multiplication
286 // Lo0: initial value of Lo register
287 // Hi0: initial value of Hi register
288 // Return true if pattern matching was successful.
289 static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
290 // ADDENode's second operand must be a flag output of an ADDC node in order
291 // for the matching to be successful.
292 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
294 if (ADDCNode->getOpcode() != ISD::ADDC)
297 SDValue MultHi = ADDENode->getOperand(0);
298 SDValue MultLo = ADDCNode->getOperand(0);
299 SDNode *MultNode = MultHi.getNode();
300 unsigned MultOpc = MultHi.getOpcode();
302 // MultHi and MultLo must be generated by the same node,
303 if (MultLo.getNode() != MultNode)
306 // and it must be a multiplication.
307 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
310 // MultLo amd MultHi must be the first and second output of MultNode
312 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
315 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
316 // of the values of MultNode, in which case MultNode will be removed in later
318 // If there exist users other than ADDENode or ADDCNode, this function returns
319 // here, which will result in MultNode being mapped to a single MULT
320 // instruction node rather than a pair of MULT and MADD instructions being
322 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
327 // Initialize accumulator.
328 SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
329 ADDCNode->getOperand(1),
330 ADDENode->getOperand(1));
332 // create MipsMAdd(u) node
333 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
335 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
336 MultNode->getOperand(0),// Factor 0
337 MultNode->getOperand(1),// Factor 1
340 // replace uses of adde and addc here
341 if (!SDValue(ADDCNode, 0).use_empty()) {
342 SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLO, DL, MVT::i32, MAdd);
343 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
345 if (!SDValue(ADDENode, 0).use_empty()) {
346 SDValue HiOut = CurDAG->getNode(MipsISD::ExtractHI, DL, MVT::i32, MAdd);
347 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
354 // Transforms a subgraph in CurDAG if the following pattern is found:
355 // (addc Lo0, multLo), (sube Hi0, multHi),
357 // multHi/Lo: product of multiplication
358 // Lo0: initial value of Lo register
359 // Hi0: initial value of Hi register
360 // Return true if pattern matching was successful.
361 static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
362 // SUBENode's second operand must be a flag output of an SUBC node in order
363 // for the matching to be successful.
364 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
366 if (SUBCNode->getOpcode() != ISD::SUBC)
369 SDValue MultHi = SUBENode->getOperand(1);
370 SDValue MultLo = SUBCNode->getOperand(1);
371 SDNode *MultNode = MultHi.getNode();
372 unsigned MultOpc = MultHi.getOpcode();
374 // MultHi and MultLo must be generated by the same node,
375 if (MultLo.getNode() != MultNode)
378 // and it must be a multiplication.
379 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
382 // MultLo amd MultHi must be the first and second output of MultNode
384 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
387 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
388 // of the values of MultNode, in which case MultNode will be removed in later
390 // If there exist users other than SUBENode or SUBCNode, this function returns
391 // here, which will result in MultNode being mapped to a single MULT
392 // instruction node rather than a pair of MULT and MSUB instructions being
394 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
399 // Initialize accumulator.
400 SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
401 SUBCNode->getOperand(0),
402 SUBENode->getOperand(0));
404 // create MipsSub(u) node
405 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
407 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
408 MultNode->getOperand(0),// Factor 0
409 MultNode->getOperand(1),// Factor 1
412 // replace uses of sube and subc here
413 if (!SDValue(SUBCNode, 0).use_empty()) {
414 SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLO, DL, MVT::i32, MSub);
415 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
417 if (!SDValue(SUBENode, 0).use_empty()) {
418 SDValue HiOut = CurDAG->getNode(MipsISD::ExtractHI, DL, MVT::i32, MSub);
419 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
425 static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
426 TargetLowering::DAGCombinerInfo &DCI,
427 const MipsSubtarget *Subtarget) {
428 if (DCI.isBeforeLegalize())
431 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
433 return SDValue(N, 0);
438 // Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
440 // Performs the following transformations:
441 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
442 // sign/zero-extension is completely overwritten by the new one performed by
444 // - Removes redundant zero extensions performed by an ISD::AND.
445 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
446 TargetLowering::DAGCombinerInfo &DCI,
447 const MipsSubtarget *Subtarget) {
448 if (!Subtarget->hasMSA())
451 SDValue Op0 = N->getOperand(0);
452 SDValue Op1 = N->getOperand(1);
453 unsigned Op0Opcode = Op0->getOpcode();
455 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
456 // where $d + 1 == 2^n and n == 32
457 // or $d + 1 == 2^n and n <= 32 and ZExt
458 // -> (MipsVExtractZExt $a, $b, $c)
459 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
460 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
461 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
466 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
468 if (Log2IfPositive <= 0)
469 return SDValue(); // Mask+1 is not a power of 2
471 SDValue Op0Op2 = Op0->getOperand(2);
472 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
473 unsigned ExtendTySize = ExtendTy.getSizeInBits();
474 unsigned Log2 = Log2IfPositive;
476 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
477 Log2 == ExtendTySize) {
478 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
479 DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT,
480 Op0->getVTList(), Ops, Op0->getNumOperands());
488 static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
489 TargetLowering::DAGCombinerInfo &DCI,
490 const MipsSubtarget *Subtarget) {
491 if (DCI.isBeforeLegalize())
494 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
496 return SDValue(N, 0);
501 static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
502 EVT ShiftTy, SelectionDAG &DAG) {
503 // Clear the upper (64 - VT.sizeInBits) bits.
504 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
508 return DAG.getConstant(0, VT);
514 // If c is power of 2, return (shl x, log2(c)).
515 if (isPowerOf2_64(C))
516 return DAG.getNode(ISD::SHL, DL, VT, X,
517 DAG.getConstant(Log2_64(C), ShiftTy));
519 unsigned Log2Ceil = Log2_64_Ceil(C);
520 uint64_t Floor = 1LL << Log2_64(C);
521 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
523 // If |c - floor_c| <= |c - ceil_c|,
524 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
525 // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
526 if (C - Floor <= Ceil - C) {
527 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
528 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
529 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
532 // If |c - floor_c| > |c - ceil_c|,
533 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
534 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
535 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
536 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
539 static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
540 const TargetLowering::DAGCombinerInfo &DCI,
541 const MipsSETargetLowering *TL) {
542 EVT VT = N->getValueType(0);
544 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
546 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
547 VT, TL->getScalarShiftAmountTy(VT), DAG);
549 return SDValue(N, 0);
552 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
554 const MipsSubtarget *Subtarget) {
555 // See if this is a vector splat immediate node.
556 APInt SplatValue, SplatUndef;
557 unsigned SplatBitSize;
559 unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
560 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
563 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
564 EltSize, !Subtarget->isLittle()) ||
565 (SplatBitSize != EltSize) ||
566 (SplatValue.getZExtValue() >= EltSize))
569 return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
570 DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
573 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
574 TargetLowering::DAGCombinerInfo &DCI,
575 const MipsSubtarget *Subtarget) {
576 EVT Ty = N->getValueType(0);
578 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
581 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
584 // Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
585 // constant splats into MipsISD::SHRA_DSP for DSPr2.
587 // Performs the following transformations:
588 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
589 // sign/zero-extension is completely overwritten by the new one performed by
590 // the ISD::SRA and ISD::SHL nodes.
591 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
594 // See performDSPShiftCombine for more information about the transformation
596 static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
597 TargetLowering::DAGCombinerInfo &DCI,
598 const MipsSubtarget *Subtarget) {
599 EVT Ty = N->getValueType(0);
601 if (Subtarget->hasMSA()) {
602 SDValue Op0 = N->getOperand(0);
603 SDValue Op1 = N->getOperand(1);
605 // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
606 // where $d + sizeof($c) == 32
607 // or $d + sizeof($c) <= 32 and SExt
608 // -> (MipsVExtractSExt $a, $b, $c)
609 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
610 SDValue Op0Op0 = Op0->getOperand(0);
611 ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
616 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
617 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)
620 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
621 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
623 if (TotalBits == 32 ||
624 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
626 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
627 Op0Op0->getOperand(2) };
628 DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT,
629 Op0Op0->getVTList(), Ops, Op0Op0->getNumOperands());
635 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
638 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
642 static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
643 TargetLowering::DAGCombinerInfo &DCI,
644 const MipsSubtarget *Subtarget) {
645 EVT Ty = N->getValueType(0);
647 if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
650 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
653 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
654 bool IsV216 = (Ty == MVT::v2i16);
658 case ISD::SETNE: return true;
662 case ISD::SETGE: return IsV216;
666 case ISD::SETUGE: return !IsV216;
667 default: return false;
671 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
672 EVT Ty = N->getValueType(0);
674 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
677 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
680 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
681 N->getOperand(1), N->getOperand(2));
684 static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
685 EVT Ty = N->getValueType(0);
687 if (Ty.is128BitVector() && Ty.isInteger()) {
688 // Try the following combines:
689 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
690 // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
691 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
692 // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
693 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
694 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
695 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
696 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
697 // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
698 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
700 SDValue Op0 = N->getOperand(0);
702 if (Op0->getOpcode() != ISD::SETCC)
705 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
708 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE)
710 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
715 SDValue Op1 = N->getOperand(1);
716 SDValue Op2 = N->getOperand(2);
717 SDValue Op0Op0 = Op0->getOperand(0);
718 SDValue Op0Op1 = Op0->getOperand(1);
720 if (Op1 == Op0Op0 && Op2 == Op0Op1)
721 return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
723 else if (Op1 == Op0Op1 && Op2 == Op0Op0)
724 return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
726 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
727 SDValue SetCC = N->getOperand(0);
729 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
732 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
733 SetCC.getOperand(0), SetCC.getOperand(1),
734 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
740 static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
741 const MipsSubtarget *Subtarget) {
742 EVT Ty = N->getValueType(0);
744 if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
745 // Try the following combines:
746 // (xor (or $a, $b), (build_vector allones))
747 // (xor (or $a, $b), (bitcast (build_vector allones)))
748 SDValue Op0 = N->getOperand(0);
749 SDValue Op1 = N->getOperand(1);
752 if (ISD::isBuildVectorAllOnes(Op0.getNode()))
754 else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
759 if (NotOp->getOpcode() == ISD::OR)
760 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
761 NotOp->getOperand(1));
768 MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
769 SelectionDAG &DAG = DCI.DAG;
772 switch (N->getOpcode()) {
774 return performADDECombine(N, DAG, DCI, Subtarget);
776 Val = performANDCombine(N, DAG, DCI, Subtarget);
779 return performSUBECombine(N, DAG, DCI, Subtarget);
781 return performMULCombine(N, DAG, DCI, this);
783 return performSHLCombine(N, DAG, DCI, Subtarget);
785 return performSRACombine(N, DAG, DCI, Subtarget);
787 return performSRLCombine(N, DAG, DCI, Subtarget);
789 return performVSELECTCombine(N, DAG);
791 Val = performXORCombine(N, DAG, Subtarget);
794 Val = performSETCCCombine(N, DAG);
801 return MipsTargetLowering::PerformDAGCombine(N, DCI);
805 MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
806 MachineBasicBlock *BB) const {
807 switch (MI->getOpcode()) {
809 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
810 case Mips::BPOSGE32_PSEUDO:
811 return emitBPOSGE32(MI, BB);
812 case Mips::SNZ_B_PSEUDO:
813 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
814 case Mips::SNZ_H_PSEUDO:
815 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
816 case Mips::SNZ_W_PSEUDO:
817 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
818 case Mips::SNZ_D_PSEUDO:
819 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
820 case Mips::SNZ_V_PSEUDO:
821 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
822 case Mips::SZ_B_PSEUDO:
823 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
824 case Mips::SZ_H_PSEUDO:
825 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
826 case Mips::SZ_W_PSEUDO:
827 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
828 case Mips::SZ_D_PSEUDO:
829 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
830 case Mips::SZ_V_PSEUDO:
831 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
832 case Mips::COPY_FW_PSEUDO:
833 return emitCOPY_FW(MI, BB);
834 case Mips::COPY_FD_PSEUDO:
835 return emitCOPY_FD(MI, BB);
836 case Mips::INSERT_FW_PSEUDO:
837 return emitINSERT_FW(MI, BB);
838 case Mips::INSERT_FD_PSEUDO:
839 return emitINSERT_FD(MI, BB);
843 bool MipsSETargetLowering::
844 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
845 unsigned NextStackOffset,
846 const MipsFunctionInfo& FI) const {
847 if (!EnableMipsTailCalls)
850 // Return false if either the callee or caller has a byval argument.
851 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
854 // Return true if the callee's argument area is no larger than the
856 return NextStackOffset <= FI.getIncomingArgSize();
859 void MipsSETargetLowering::
860 getOpndList(SmallVectorImpl<SDValue> &Ops,
861 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
862 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
863 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
864 // T9 should contain the address of the callee function if
865 // -reloction-model=pic or it is an indirect call.
866 if (IsPICCall || !GlobalOrExternal) {
867 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
868 RegsToPass.push_front(std::make_pair(T9Reg, Callee));
870 Ops.push_back(Callee);
872 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
873 InternalLinkage, CLI, Callee, Chain);
876 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
877 LoadSDNode &Nd = *cast<LoadSDNode>(Op);
879 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
880 return MipsTargetLowering::lowerLOAD(Op, DAG);
882 // Replace a double precision load with two i32 loads and a buildpair64.
884 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
885 EVT PtrVT = Ptr.getValueType();
887 // i32 load from lower address.
888 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
889 MachinePointerInfo(), Nd.isVolatile(),
890 Nd.isNonTemporal(), Nd.isInvariant(),
893 // i32 load from higher address.
894 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
895 SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
896 MachinePointerInfo(), Nd.isVolatile(),
897 Nd.isNonTemporal(), Nd.isInvariant(),
898 std::min(Nd.getAlignment(), 4U));
900 if (!Subtarget->isLittle())
903 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
904 SDValue Ops[2] = {BP, Hi.getValue(1)};
905 return DAG.getMergeValues(Ops, 2, DL);
908 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
909 StoreSDNode &Nd = *cast<StoreSDNode>(Op);
911 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
912 return MipsTargetLowering::lowerSTORE(Op, DAG);
914 // Replace a double precision store with two extractelement64s and i32 stores.
916 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
917 EVT PtrVT = Ptr.getValueType();
918 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
919 Val, DAG.getConstant(0, MVT::i32));
920 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
921 Val, DAG.getConstant(1, MVT::i32));
923 if (!Subtarget->isLittle())
926 // i32 store to lower address.
927 Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
928 Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
931 // i32 store to higher address.
932 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
933 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
934 Nd.isVolatile(), Nd.isNonTemporal(),
935 std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo());
938 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
939 bool HasLo, bool HasHi,
940 SelectionDAG &DAG) const {
941 EVT Ty = Op.getOperand(0).getValueType();
943 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
944 Op.getOperand(0), Op.getOperand(1));
948 Lo = DAG.getNode(MipsISD::ExtractLO, DL, Ty, Mult);
950 Hi = DAG.getNode(MipsISD::ExtractHI, DL, Ty, Mult);
952 if (!HasLo || !HasHi)
953 return HasLo ? Lo : Hi;
955 SDValue Vals[] = { Lo, Hi };
956 return DAG.getMergeValues(Vals, 2, DL);
960 static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
961 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
962 DAG.getConstant(0, MVT::i32));
963 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
964 DAG.getConstant(1, MVT::i32));
965 return DAG.getNode(MipsISD::InsertLOHI, DL, MVT::Untyped, InLo, InHi);
968 static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
969 SDValue Lo = DAG.getNode(MipsISD::ExtractLO, DL, MVT::i32, Op);
970 SDValue Hi = DAG.getNode(MipsISD::ExtractHI, DL, MVT::i32, Op);
971 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
974 // This function expands mips intrinsic nodes which have 64-bit input operands
977 // out64 = intrinsic-node in64
979 // lo = copy (extract-element (in64, 0))
980 // hi = copy (extract-element (in64, 1))
981 // mips-specific-node
984 // out64 = merge-values (v0, v1)
986 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
988 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
989 SmallVector<SDValue, 3> Ops;
992 // See if Op has a chain input.
994 Ops.push_back(Op->getOperand(OpNo++));
996 // The next operand is the intrinsic opcode.
997 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
999 // See if the next operand has type i64.
1000 SDValue Opnd = Op->getOperand(++OpNo), In64;
1002 if (Opnd.getValueType() == MVT::i64)
1003 In64 = initAccumulator(Opnd, DL, DAG);
1005 Ops.push_back(Opnd);
1007 // Push the remaining operands.
1008 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1009 Ops.push_back(Op->getOperand(OpNo));
1011 // Add In64 to the end of the list.
1013 Ops.push_back(In64);
1016 SmallVector<EVT, 2> ResTys;
1018 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1020 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1023 SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
1024 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1029 assert(Val->getValueType(1) == MVT::Other);
1030 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1031 return DAG.getMergeValues(Vals, 2, DL);
1034 // Lower an MSA copy intrinsic into the specified SelectionDAG node
1035 static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1037 SDValue Vec = Op->getOperand(1);
1038 SDValue Idx = Op->getOperand(2);
1039 EVT ResTy = Op->getValueType(0);
1040 EVT EltTy = Vec->getValueType(0).getVectorElementType();
1042 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1043 DAG.getValueType(EltTy));
1049 lowerMSASplatImm(SDLoc DL, EVT ResTy, SDValue ImmOp, SelectionDAG &DAG) {
1050 EVT ViaVecTy = ResTy;
1051 SmallVector<SDValue, 16> Ops;
1054 if (ViaVecTy == MVT::v2i64) {
1055 ImmHiOp = DAG.getNode(ISD::SRA, DL, MVT::i32, ImmOp,
1056 DAG.getConstant(31, MVT::i32));
1057 for (unsigned i = 0; i < ViaVecTy.getVectorNumElements(); ++i) {
1058 Ops.push_back(ImmHiOp);
1059 Ops.push_back(ImmOp);
1061 ViaVecTy = MVT::v4i32;
1063 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1064 Ops.push_back(ImmOp);
1067 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, &Ops[0],
1070 if (ResTy != ViaVecTy)
1071 Result = DAG.getNode(ISD::BITCAST, DL, ResTy, Result);
1077 lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
1078 return lowerMSASplatImm(SDLoc(Op), Op->getValueType(0),
1079 Op->getOperand(ImmOp), DAG);
1082 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1083 SelectionDAG &DAG) const {
1086 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
1089 case Intrinsic::mips_shilo:
1090 return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1091 case Intrinsic::mips_dpau_h_qbl:
1092 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1093 case Intrinsic::mips_dpau_h_qbr:
1094 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1095 case Intrinsic::mips_dpsu_h_qbl:
1096 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1097 case Intrinsic::mips_dpsu_h_qbr:
1098 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1099 case Intrinsic::mips_dpa_w_ph:
1100 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1101 case Intrinsic::mips_dps_w_ph:
1102 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1103 case Intrinsic::mips_dpax_w_ph:
1104 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1105 case Intrinsic::mips_dpsx_w_ph:
1106 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1107 case Intrinsic::mips_mulsa_w_ph:
1108 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1109 case Intrinsic::mips_mult:
1110 return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1111 case Intrinsic::mips_multu:
1112 return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1113 case Intrinsic::mips_madd:
1114 return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1115 case Intrinsic::mips_maddu:
1116 return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1117 case Intrinsic::mips_msub:
1118 return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1119 case Intrinsic::mips_msubu:
1120 return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1121 case Intrinsic::mips_addv_b:
1122 case Intrinsic::mips_addv_h:
1123 case Intrinsic::mips_addv_w:
1124 case Intrinsic::mips_addv_d:
1125 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1127 case Intrinsic::mips_addvi_b:
1128 case Intrinsic::mips_addvi_h:
1129 case Intrinsic::mips_addvi_w:
1130 case Intrinsic::mips_addvi_d:
1131 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1132 lowerMSASplatImm(Op, 2, DAG));
1133 case Intrinsic::mips_and_v:
1134 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1136 case Intrinsic::mips_andi_b:
1137 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1138 lowerMSASplatImm(Op, 2, DAG));
1139 case Intrinsic::mips_bnz_b:
1140 case Intrinsic::mips_bnz_h:
1141 case Intrinsic::mips_bnz_w:
1142 case Intrinsic::mips_bnz_d:
1143 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1145 case Intrinsic::mips_bnz_v:
1146 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1148 case Intrinsic::mips_bsel_v:
1149 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1150 Op->getOperand(1), Op->getOperand(2),
1152 case Intrinsic::mips_bseli_b:
1153 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1154 Op->getOperand(1), Op->getOperand(2),
1155 lowerMSASplatImm(Op, 3, DAG));
1156 case Intrinsic::mips_bz_b:
1157 case Intrinsic::mips_bz_h:
1158 case Intrinsic::mips_bz_w:
1159 case Intrinsic::mips_bz_d:
1160 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1162 case Intrinsic::mips_bz_v:
1163 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1165 case Intrinsic::mips_ceq_b:
1166 case Intrinsic::mips_ceq_h:
1167 case Intrinsic::mips_ceq_w:
1168 case Intrinsic::mips_ceq_d:
1169 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1170 Op->getOperand(2), ISD::SETEQ);
1171 case Intrinsic::mips_ceqi_b:
1172 case Intrinsic::mips_ceqi_h:
1173 case Intrinsic::mips_ceqi_w:
1174 case Intrinsic::mips_ceqi_d:
1175 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1176 lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ);
1177 case Intrinsic::mips_cle_s_b:
1178 case Intrinsic::mips_cle_s_h:
1179 case Intrinsic::mips_cle_s_w:
1180 case Intrinsic::mips_cle_s_d:
1181 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1182 Op->getOperand(2), ISD::SETLE);
1183 case Intrinsic::mips_clei_s_b:
1184 case Intrinsic::mips_clei_s_h:
1185 case Intrinsic::mips_clei_s_w:
1186 case Intrinsic::mips_clei_s_d:
1187 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1188 lowerMSASplatImm(Op, 2, DAG), ISD::SETLE);
1189 case Intrinsic::mips_cle_u_b:
1190 case Intrinsic::mips_cle_u_h:
1191 case Intrinsic::mips_cle_u_w:
1192 case Intrinsic::mips_cle_u_d:
1193 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1194 Op->getOperand(2), ISD::SETULE);
1195 case Intrinsic::mips_clei_u_b:
1196 case Intrinsic::mips_clei_u_h:
1197 case Intrinsic::mips_clei_u_w:
1198 case Intrinsic::mips_clei_u_d:
1199 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1200 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1201 case Intrinsic::mips_clt_s_b:
1202 case Intrinsic::mips_clt_s_h:
1203 case Intrinsic::mips_clt_s_w:
1204 case Intrinsic::mips_clt_s_d:
1205 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1206 Op->getOperand(2), ISD::SETLT);
1207 case Intrinsic::mips_clti_s_b:
1208 case Intrinsic::mips_clti_s_h:
1209 case Intrinsic::mips_clti_s_w:
1210 case Intrinsic::mips_clti_s_d:
1211 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1212 lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);
1213 case Intrinsic::mips_clt_u_b:
1214 case Intrinsic::mips_clt_u_h:
1215 case Intrinsic::mips_clt_u_w:
1216 case Intrinsic::mips_clt_u_d:
1217 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1218 Op->getOperand(2), ISD::SETULT);
1219 case Intrinsic::mips_clti_u_b:
1220 case Intrinsic::mips_clti_u_h:
1221 case Intrinsic::mips_clti_u_w:
1222 case Intrinsic::mips_clti_u_d:
1223 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1224 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1225 case Intrinsic::mips_copy_s_b:
1226 case Intrinsic::mips_copy_s_h:
1227 case Intrinsic::mips_copy_s_w:
1228 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1229 case Intrinsic::mips_copy_s_d:
1230 // Don't lower directly into VEXTRACT_SEXT_ELT since i64 might be illegal.
1231 // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type
1232 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1233 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1234 Op->getOperand(1), Op->getOperand(2));
1235 case Intrinsic::mips_copy_u_b:
1236 case Intrinsic::mips_copy_u_h:
1237 case Intrinsic::mips_copy_u_w:
1238 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1239 case Intrinsic::mips_copy_u_d:
1240 // Don't lower directly into VEXTRACT_ZEXT_ELT since i64 might be illegal.
1241 // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type
1242 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1244 // Note: When i64 is illegal, this results in copy_s.w instructions instead
1245 // of copy_u.w instructions. This makes no difference to the behaviour
1246 // since i64 is only illegal when the register file is 32-bit.
1247 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1248 Op->getOperand(1), Op->getOperand(2));
1249 case Intrinsic::mips_div_s_b:
1250 case Intrinsic::mips_div_s_h:
1251 case Intrinsic::mips_div_s_w:
1252 case Intrinsic::mips_div_s_d:
1253 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1255 case Intrinsic::mips_div_u_b:
1256 case Intrinsic::mips_div_u_h:
1257 case Intrinsic::mips_div_u_w:
1258 case Intrinsic::mips_div_u_d:
1259 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1261 case Intrinsic::mips_fadd_w:
1262 case Intrinsic::mips_fadd_d:
1263 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1265 // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1266 case Intrinsic::mips_fceq_w:
1267 case Intrinsic::mips_fceq_d:
1268 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1269 Op->getOperand(2), ISD::SETOEQ);
1270 case Intrinsic::mips_fcle_w:
1271 case Intrinsic::mips_fcle_d:
1272 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1273 Op->getOperand(2), ISD::SETOLE);
1274 case Intrinsic::mips_fclt_w:
1275 case Intrinsic::mips_fclt_d:
1276 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1277 Op->getOperand(2), ISD::SETOLT);
1278 case Intrinsic::mips_fcne_w:
1279 case Intrinsic::mips_fcne_d:
1280 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1281 Op->getOperand(2), ISD::SETONE);
1282 case Intrinsic::mips_fcor_w:
1283 case Intrinsic::mips_fcor_d:
1284 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1285 Op->getOperand(2), ISD::SETO);
1286 case Intrinsic::mips_fcueq_w:
1287 case Intrinsic::mips_fcueq_d:
1288 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1289 Op->getOperand(2), ISD::SETUEQ);
1290 case Intrinsic::mips_fcule_w:
1291 case Intrinsic::mips_fcule_d:
1292 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1293 Op->getOperand(2), ISD::SETULE);
1294 case Intrinsic::mips_fcult_w:
1295 case Intrinsic::mips_fcult_d:
1296 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1297 Op->getOperand(2), ISD::SETULT);
1298 case Intrinsic::mips_fcun_w:
1299 case Intrinsic::mips_fcun_d:
1300 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1301 Op->getOperand(2), ISD::SETUO);
1302 case Intrinsic::mips_fcune_w:
1303 case Intrinsic::mips_fcune_d:
1304 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1305 Op->getOperand(2), ISD::SETUNE);
1306 case Intrinsic::mips_fdiv_w:
1307 case Intrinsic::mips_fdiv_d:
1308 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1310 case Intrinsic::mips_ffint_u_w:
1311 case Intrinsic::mips_ffint_u_d:
1312 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1314 case Intrinsic::mips_ffint_s_w:
1315 case Intrinsic::mips_ffint_s_d:
1316 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1318 case Intrinsic::mips_fill_b:
1319 case Intrinsic::mips_fill_h:
1320 case Intrinsic::mips_fill_w:
1321 case Intrinsic::mips_fill_d: {
1322 SmallVector<SDValue, 16> Ops;
1323 EVT ResTy = Op->getValueType(0);
1325 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1326 Ops.push_back(Op->getOperand(1));
1328 // If ResTy is v2i64 then the type legalizer will break this node down into
1329 // an equivalent v4i32.
1330 return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, &Ops[0], Ops.size());
1332 case Intrinsic::mips_flog2_w:
1333 case Intrinsic::mips_flog2_d:
1334 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1335 case Intrinsic::mips_fmul_w:
1336 case Intrinsic::mips_fmul_d:
1337 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1339 case Intrinsic::mips_frint_w:
1340 case Intrinsic::mips_frint_d:
1341 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1342 case Intrinsic::mips_fsqrt_w:
1343 case Intrinsic::mips_fsqrt_d:
1344 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1345 case Intrinsic::mips_fsub_w:
1346 case Intrinsic::mips_fsub_d:
1347 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1349 case Intrinsic::mips_ftrunc_u_w:
1350 case Intrinsic::mips_ftrunc_u_d:
1351 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1353 case Intrinsic::mips_ftrunc_s_w:
1354 case Intrinsic::mips_ftrunc_s_d:
1355 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1357 case Intrinsic::mips_ilvev_b:
1358 case Intrinsic::mips_ilvev_h:
1359 case Intrinsic::mips_ilvev_w:
1360 case Intrinsic::mips_ilvev_d:
1361 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
1362 Op->getOperand(1), Op->getOperand(2));
1363 case Intrinsic::mips_ilvl_b:
1364 case Intrinsic::mips_ilvl_h:
1365 case Intrinsic::mips_ilvl_w:
1366 case Intrinsic::mips_ilvl_d:
1367 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
1368 Op->getOperand(1), Op->getOperand(2));
1369 case Intrinsic::mips_ilvod_b:
1370 case Intrinsic::mips_ilvod_h:
1371 case Intrinsic::mips_ilvod_w:
1372 case Intrinsic::mips_ilvod_d:
1373 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
1374 Op->getOperand(1), Op->getOperand(2));
1375 case Intrinsic::mips_ilvr_b:
1376 case Intrinsic::mips_ilvr_h:
1377 case Intrinsic::mips_ilvr_w:
1378 case Intrinsic::mips_ilvr_d:
1379 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
1380 Op->getOperand(1), Op->getOperand(2));
1381 case Intrinsic::mips_insert_b:
1382 case Intrinsic::mips_insert_h:
1383 case Intrinsic::mips_insert_w:
1384 case Intrinsic::mips_insert_d:
1385 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1386 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1387 case Intrinsic::mips_ldi_b:
1388 case Intrinsic::mips_ldi_h:
1389 case Intrinsic::mips_ldi_w:
1390 case Intrinsic::mips_ldi_d:
1391 return lowerMSASplatImm(Op, 1, DAG);
1392 case Intrinsic::mips_max_s_b:
1393 case Intrinsic::mips_max_s_h:
1394 case Intrinsic::mips_max_s_w:
1395 case Intrinsic::mips_max_s_d:
1396 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1397 Op->getOperand(1), Op->getOperand(2));
1398 case Intrinsic::mips_max_u_b:
1399 case Intrinsic::mips_max_u_h:
1400 case Intrinsic::mips_max_u_w:
1401 case Intrinsic::mips_max_u_d:
1402 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1403 Op->getOperand(1), Op->getOperand(2));
1404 case Intrinsic::mips_maxi_s_b:
1405 case Intrinsic::mips_maxi_s_h:
1406 case Intrinsic::mips_maxi_s_w:
1407 case Intrinsic::mips_maxi_s_d:
1408 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1409 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1410 case Intrinsic::mips_maxi_u_b:
1411 case Intrinsic::mips_maxi_u_h:
1412 case Intrinsic::mips_maxi_u_w:
1413 case Intrinsic::mips_maxi_u_d:
1414 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1415 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1416 case Intrinsic::mips_min_s_b:
1417 case Intrinsic::mips_min_s_h:
1418 case Intrinsic::mips_min_s_w:
1419 case Intrinsic::mips_min_s_d:
1420 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1421 Op->getOperand(1), Op->getOperand(2));
1422 case Intrinsic::mips_min_u_b:
1423 case Intrinsic::mips_min_u_h:
1424 case Intrinsic::mips_min_u_w:
1425 case Intrinsic::mips_min_u_d:
1426 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1427 Op->getOperand(1), Op->getOperand(2));
1428 case Intrinsic::mips_mini_s_b:
1429 case Intrinsic::mips_mini_s_h:
1430 case Intrinsic::mips_mini_s_w:
1431 case Intrinsic::mips_mini_s_d:
1432 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1433 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1434 case Intrinsic::mips_mini_u_b:
1435 case Intrinsic::mips_mini_u_h:
1436 case Intrinsic::mips_mini_u_w:
1437 case Intrinsic::mips_mini_u_d:
1438 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1439 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1440 case Intrinsic::mips_mod_s_b:
1441 case Intrinsic::mips_mod_s_h:
1442 case Intrinsic::mips_mod_s_w:
1443 case Intrinsic::mips_mod_s_d:
1444 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
1446 case Intrinsic::mips_mod_u_b:
1447 case Intrinsic::mips_mod_u_h:
1448 case Intrinsic::mips_mod_u_w:
1449 case Intrinsic::mips_mod_u_d:
1450 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
1452 case Intrinsic::mips_mulv_b:
1453 case Intrinsic::mips_mulv_h:
1454 case Intrinsic::mips_mulv_w:
1455 case Intrinsic::mips_mulv_d:
1456 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
1458 case Intrinsic::mips_nlzc_b:
1459 case Intrinsic::mips_nlzc_h:
1460 case Intrinsic::mips_nlzc_w:
1461 case Intrinsic::mips_nlzc_d:
1462 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
1463 case Intrinsic::mips_nor_v: {
1464 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1465 Op->getOperand(1), Op->getOperand(2));
1466 return DAG.getNOT(DL, Res, Res->getValueType(0));
1468 case Intrinsic::mips_nori_b: {
1469 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1471 lowerMSASplatImm(Op, 2, DAG));
1472 return DAG.getNOT(DL, Res, Res->getValueType(0));
1474 case Intrinsic::mips_or_v:
1475 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
1477 case Intrinsic::mips_ori_b:
1478 return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1479 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1480 case Intrinsic::mips_pckev_b:
1481 case Intrinsic::mips_pckev_h:
1482 case Intrinsic::mips_pckev_w:
1483 case Intrinsic::mips_pckev_d:
1484 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
1485 Op->getOperand(1), Op->getOperand(2));
1486 case Intrinsic::mips_pckod_b:
1487 case Intrinsic::mips_pckod_h:
1488 case Intrinsic::mips_pckod_w:
1489 case Intrinsic::mips_pckod_d:
1490 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
1491 Op->getOperand(1), Op->getOperand(2));
1492 case Intrinsic::mips_pcnt_b:
1493 case Intrinsic::mips_pcnt_h:
1494 case Intrinsic::mips_pcnt_w:
1495 case Intrinsic::mips_pcnt_d:
1496 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
1497 case Intrinsic::mips_shf_b:
1498 case Intrinsic::mips_shf_h:
1499 case Intrinsic::mips_shf_w:
1500 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
1501 Op->getOperand(2), Op->getOperand(1));
1502 case Intrinsic::mips_sll_b:
1503 case Intrinsic::mips_sll_h:
1504 case Intrinsic::mips_sll_w:
1505 case Intrinsic::mips_sll_d:
1506 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
1508 case Intrinsic::mips_slli_b:
1509 case Intrinsic::mips_slli_h:
1510 case Intrinsic::mips_slli_w:
1511 case Intrinsic::mips_slli_d:
1512 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
1513 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1514 case Intrinsic::mips_splati_b:
1515 case Intrinsic::mips_splati_h:
1516 case Intrinsic::mips_splati_w:
1517 case Intrinsic::mips_splati_d:
1518 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1519 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
1521 case Intrinsic::mips_sra_b:
1522 case Intrinsic::mips_sra_h:
1523 case Intrinsic::mips_sra_w:
1524 case Intrinsic::mips_sra_d:
1525 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
1527 case Intrinsic::mips_srai_b:
1528 case Intrinsic::mips_srai_h:
1529 case Intrinsic::mips_srai_w:
1530 case Intrinsic::mips_srai_d:
1531 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
1532 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1533 case Intrinsic::mips_srl_b:
1534 case Intrinsic::mips_srl_h:
1535 case Intrinsic::mips_srl_w:
1536 case Intrinsic::mips_srl_d:
1537 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
1539 case Intrinsic::mips_srli_b:
1540 case Intrinsic::mips_srli_h:
1541 case Intrinsic::mips_srli_w:
1542 case Intrinsic::mips_srli_d:
1543 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
1544 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1545 case Intrinsic::mips_subv_b:
1546 case Intrinsic::mips_subv_h:
1547 case Intrinsic::mips_subv_w:
1548 case Intrinsic::mips_subv_d:
1549 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
1551 case Intrinsic::mips_subvi_b:
1552 case Intrinsic::mips_subvi_h:
1553 case Intrinsic::mips_subvi_w:
1554 case Intrinsic::mips_subvi_d:
1555 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
1556 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1557 case Intrinsic::mips_vshf_b:
1558 case Intrinsic::mips_vshf_h:
1559 case Intrinsic::mips_vshf_w:
1560 case Intrinsic::mips_vshf_d:
1561 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1562 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1563 case Intrinsic::mips_xor_v:
1564 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
1566 case Intrinsic::mips_xori_b:
1567 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
1568 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1572 static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1574 SDValue ChainIn = Op->getOperand(0);
1575 SDValue Address = Op->getOperand(2);
1576 SDValue Offset = Op->getOperand(3);
1577 EVT ResTy = Op->getValueType(0);
1578 EVT PtrTy = Address->getValueType(0);
1580 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1582 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
1586 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
1587 SelectionDAG &DAG) const {
1588 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1592 case Intrinsic::mips_extp:
1593 return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
1594 case Intrinsic::mips_extpdp:
1595 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
1596 case Intrinsic::mips_extr_w:
1597 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
1598 case Intrinsic::mips_extr_r_w:
1599 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
1600 case Intrinsic::mips_extr_rs_w:
1601 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
1602 case Intrinsic::mips_extr_s_h:
1603 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
1604 case Intrinsic::mips_mthlip:
1605 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
1606 case Intrinsic::mips_mulsaq_s_w_ph:
1607 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
1608 case Intrinsic::mips_maq_s_w_phl:
1609 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
1610 case Intrinsic::mips_maq_s_w_phr:
1611 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
1612 case Intrinsic::mips_maq_sa_w_phl:
1613 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
1614 case Intrinsic::mips_maq_sa_w_phr:
1615 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
1616 case Intrinsic::mips_dpaq_s_w_ph:
1617 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
1618 case Intrinsic::mips_dpsq_s_w_ph:
1619 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
1620 case Intrinsic::mips_dpaq_sa_l_w:
1621 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
1622 case Intrinsic::mips_dpsq_sa_l_w:
1623 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
1624 case Intrinsic::mips_dpaqx_s_w_ph:
1625 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
1626 case Intrinsic::mips_dpaqx_sa_w_ph:
1627 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
1628 case Intrinsic::mips_dpsqx_s_w_ph:
1629 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
1630 case Intrinsic::mips_dpsqx_sa_w_ph:
1631 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
1632 case Intrinsic::mips_ld_b:
1633 case Intrinsic::mips_ld_h:
1634 case Intrinsic::mips_ld_w:
1635 case Intrinsic::mips_ld_d:
1636 case Intrinsic::mips_ldx_b:
1637 case Intrinsic::mips_ldx_h:
1638 case Intrinsic::mips_ldx_w:
1639 case Intrinsic::mips_ldx_d:
1640 return lowerMSALoadIntr(Op, DAG, Intr);
1644 static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1646 SDValue ChainIn = Op->getOperand(0);
1647 SDValue Value = Op->getOperand(2);
1648 SDValue Address = Op->getOperand(3);
1649 SDValue Offset = Op->getOperand(4);
1650 EVT PtrTy = Address->getValueType(0);
1652 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1654 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
1658 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
1659 SelectionDAG &DAG) const {
1660 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1664 case Intrinsic::mips_st_b:
1665 case Intrinsic::mips_st_h:
1666 case Intrinsic::mips_st_w:
1667 case Intrinsic::mips_st_d:
1668 case Intrinsic::mips_stx_b:
1669 case Intrinsic::mips_stx_h:
1670 case Intrinsic::mips_stx_w:
1671 case Intrinsic::mips_stx_d:
1672 return lowerMSAStoreIntr(Op, DAG, Intr);
1676 /// \brief Check if the given BuildVectorSDNode is a splat.
1677 /// This method currently relies on DAG nodes being reused when equivalent,
1678 /// so it's possible for this to return false even when isConstantSplat returns
1680 static bool isSplatVector(const BuildVectorSDNode *N) {
1681 unsigned int nOps = N->getNumOperands();
1682 assert(nOps > 1 && "isSplat has 0 or 1 sized build vector");
1684 SDValue Operand0 = N->getOperand(0);
1686 for (unsigned int i = 1; i < nOps; ++i) {
1687 if (N->getOperand(i) != Operand0)
1694 // Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
1696 // The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
1697 // choose to sign-extend but we could have equally chosen zero-extend. The
1698 // DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
1699 // result into this node later (possibly changing it to a zero-extend in the
1701 SDValue MipsSETargetLowering::
1702 lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
1704 EVT ResTy = Op->getValueType(0);
1705 SDValue Op0 = Op->getOperand(0);
1706 EVT VecTy = Op0->getValueType(0);
1708 if (!VecTy.is128BitVector())
1711 if (ResTy.isInteger()) {
1712 SDValue Op1 = Op->getOperand(1);
1713 EVT EltTy = VecTy.getVectorElementType();
1714 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
1715 DAG.getValueType(EltTy));
1721 static bool isConstantOrUndef(const SDValue Op) {
1722 if (Op->getOpcode() == ISD::UNDEF)
1724 if (dyn_cast<ConstantSDNode>(Op))
1726 if (dyn_cast<ConstantFPSDNode>(Op))
1731 static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) {
1732 for (unsigned i = 0; i < Op->getNumOperands(); ++i)
1733 if (isConstantOrUndef(Op->getOperand(i)))
1738 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
1741 // Lowers according to the following rules:
1742 // - Constant splats are legal as-is as long as the SplatBitSize is a power of
1743 // 2 less than or equal to 64 and the value fits into a signed 10-bit
1745 // - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
1746 // is a power of 2 less than or equal to 64 and the value does not fit into a
1747 // signed 10-bit immediate
1748 // - Non-constant splats are legal as-is.
1749 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
1750 // - All others are illegal and must be expanded.
1751 SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
1752 SelectionDAG &DAG) const {
1753 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
1754 EVT ResTy = Op->getValueType(0);
1756 APInt SplatValue, SplatUndef;
1757 unsigned SplatBitSize;
1760 if (!Subtarget->hasMSA() || !ResTy.is128BitVector())
1763 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
1765 !Subtarget->isLittle()) && SplatBitSize <= 64) {
1766 // We can only cope with 8, 16, 32, or 64-bit elements
1767 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
1771 // If the value fits into a simm10 then we can use ldi.[bhwd]
1772 if (SplatValue.isSignedIntN(10))
1777 switch (SplatBitSize) {
1781 ViaVecTy = MVT::v16i8;
1784 ViaVecTy = MVT::v8i16;
1787 ViaVecTy = MVT::v4i32;
1790 // There's no fill.d to fall back on for 64-bit values
1794 SmallVector<SDValue, 16> Ops;
1795 SDValue Constant = DAG.getConstant(SplatValue.sextOrSelf(32), MVT::i32);
1797 for (unsigned i = 0; i < ViaVecTy.getVectorNumElements(); ++i)
1798 Ops.push_back(Constant);
1800 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Node), ViaVecTy,
1801 &Ops[0], Ops.size());
1803 if (ViaVecTy != ResTy)
1804 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
1807 } else if (isSplatVector(Node))
1809 else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
1810 // Use INSERT_VECTOR_ELT operations rather than expand to stores.
1811 // The resulting code is the same length as the expansion, but it doesn't
1812 // use memory operations
1813 EVT ResTy = Node->getValueType(0);
1815 assert(ResTy.isVector());
1817 unsigned NumElts = ResTy.getVectorNumElements();
1818 SDValue Vector = DAG.getUNDEF(ResTy);
1819 for (unsigned i = 0; i < NumElts; ++i) {
1820 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
1821 Node->getOperand(i),
1822 DAG.getConstant(i, MVT::i32));
1830 // Lower VECTOR_SHUFFLE into SHF (if possible).
1832 // SHF splits the vector into blocks of four elements, then shuffles these
1833 // elements according to a <4 x i2> constant (encoded as an integer immediate).
1835 // It is therefore possible to lower into SHF when the mask takes the form:
1836 // <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
1837 // When undef's appear they are treated as if they were whatever value is
1838 // necessary in order to fit the above form.
1841 // %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
1842 // <8 x i32> <i32 3, i32 2, i32 1, i32 0,
1843 // i32 7, i32 6, i32 5, i32 4>
1845 // (SHF_H $w0, $w1, 27)
1846 // where the 27 comes from:
1847 // 3 + (2 << 2) + (1 << 4) + (0 << 6)
1848 static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
1849 SmallVector<int, 16> Indices,
1850 SelectionDAG &DAG) {
1851 int SHFIndices[4] = { -1, -1, -1, -1 };
1853 if (Indices.size() < 4)
1856 for (unsigned i = 0; i < 4; ++i) {
1857 for (unsigned j = i; j < Indices.size(); j += 4) {
1858 int Idx = Indices[j];
1860 // Convert from vector index to 4-element subvector index
1861 // If an index refers to an element outside of the subvector then give up
1864 if (Idx < 0 || Idx >= 4)
1868 // If the mask has an undef, replace it with the current index.
1869 // Note that it might still be undef if the current index is also undef
1870 if (SHFIndices[i] == -1)
1871 SHFIndices[i] = Idx;
1873 // Check that non-undef values are the same as in the mask. If they
1874 // aren't then give up
1875 if (!(Idx == -1 || Idx == SHFIndices[i]))
1880 // Calculate the immediate. Replace any remaining undefs with zero
1882 for (int i = 3; i >= 0; --i) {
1883 int Idx = SHFIndices[i];
1892 return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy,
1893 DAG.getConstant(Imm, MVT::i32), Op->getOperand(0));
1896 // Lower VECTOR_SHUFFLE into ILVEV (if possible).
1898 // ILVEV interleaves the even elements from each vector.
1900 // It is possible to lower into ILVEV when the mask takes the form:
1901 // <0, n, 2, n+2, 4, n+4, ...>
1902 // where n is the number of elements in the vector.
1904 // When undef's appear in the mask they are treated as if they were whatever
1905 // value is necessary in order to fit the above form.
1906 static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy,
1907 SmallVector<int, 16> Indices,
1908 SelectionDAG &DAG) {
1909 assert ((Indices.size() % 2) == 0);
1911 int WtIdx = ResTy.getVectorNumElements();
1913 for (unsigned i = 0; i < Indices.size(); i += 2) {
1914 if (Indices[i] != -1 && Indices[i] != WsIdx)
1916 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
1922 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Op->getOperand(0),
1926 // Lower VECTOR_SHUFFLE into ILVOD (if possible).
1928 // ILVOD interleaves the odd elements from each vector.
1930 // It is possible to lower into ILVOD when the mask takes the form:
1931 // <1, n+1, 3, n+3, 5, n+5, ...>
1932 // where n is the number of elements in the vector.
1934 // When undef's appear in the mask they are treated as if they were whatever
1935 // value is necessary in order to fit the above form.
1936 static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy,
1937 SmallVector<int, 16> Indices,
1938 SelectionDAG &DAG) {
1939 assert ((Indices.size() % 2) == 0);
1941 int WtIdx = ResTy.getVectorNumElements() + 1;
1943 for (unsigned i = 0; i < Indices.size(); i += 2) {
1944 if (Indices[i] != -1 && Indices[i] != WsIdx)
1946 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
1952 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Op->getOperand(0),
1956 // Lower VECTOR_SHUFFLE into ILVL (if possible).
1958 // ILVL interleaves consecutive elements from the left half of each vector.
1960 // It is possible to lower into ILVL when the mask takes the form:
1961 // <0, n, 1, n+1, 2, n+2, ...>
1962 // where n is the number of elements in the vector.
1964 // When undef's appear in the mask they are treated as if they were whatever
1965 // value is necessary in order to fit the above form.
1966 static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy,
1967 SmallVector<int, 16> Indices,
1968 SelectionDAG &DAG) {
1969 assert ((Indices.size() % 2) == 0);
1971 int WtIdx = ResTy.getVectorNumElements();
1973 for (unsigned i = 0; i < Indices.size(); i += 2) {
1974 if (Indices[i] != -1 && Indices[i] != WsIdx)
1976 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
1982 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Op->getOperand(0),
1986 // Lower VECTOR_SHUFFLE into ILVR (if possible).
1988 // ILVR interleaves consecutive elements from the right half of each vector.
1990 // It is possible to lower into ILVR when the mask takes the form:
1991 // <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
1992 // where n is the number of elements in the vector and x is half n.
1994 // When undef's appear in the mask they are treated as if they were whatever
1995 // value is necessary in order to fit the above form.
1996 static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
1997 SmallVector<int, 16> Indices,
1998 SelectionDAG &DAG) {
1999 assert ((Indices.size() % 2) == 0);
2000 unsigned NumElts = ResTy.getVectorNumElements();
2001 int WsIdx = NumElts / 2;
2002 int WtIdx = NumElts + NumElts / 2;
2004 for (unsigned i = 0; i < Indices.size(); i += 2) {
2005 if (Indices[i] != -1 && Indices[i] != WsIdx)
2007 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2013 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Op->getOperand(0),
2017 // Lower VECTOR_SHUFFLE into PCKEV (if possible).
2019 // PCKEV copies the even elements of each vector into the result vector.
2021 // It is possible to lower into PCKEV when the mask takes the form:
2022 // <0, 2, 4, ..., n, n+2, n+4, ...>
2023 // where n is the number of elements in the vector.
2025 // When undef's appear in the mask they are treated as if they were whatever
2026 // value is necessary in order to fit the above form.
2027 static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy,
2028 SmallVector<int, 16> Indices,
2029 SelectionDAG &DAG) {
2030 assert ((Indices.size() % 2) == 0);
2033 for (unsigned i = 0; i < Indices.size(); ++i) {
2034 if (Indices[i] != -1 && Indices[i] != Idx)
2039 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Op->getOperand(0),
2043 // Lower VECTOR_SHUFFLE into PCKOD (if possible).
2045 // PCKOD copies the odd elements of each vector into the result vector.
2047 // It is possible to lower into PCKOD when the mask takes the form:
2048 // <1, 3, 5, ..., n+1, n+3, n+5, ...>
2049 // where n is the number of elements in the vector.
2051 // When undef's appear in the mask they are treated as if they were whatever
2052 // value is necessary in order to fit the above form.
2053 static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
2054 SmallVector<int, 16> Indices,
2055 SelectionDAG &DAG) {
2056 assert ((Indices.size() % 2) == 0);
2059 for (unsigned i = 0; i < Indices.size(); ++i) {
2060 if (Indices[i] != -1 && Indices[i] != Idx)
2065 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Op->getOperand(0),
2069 // Lower VECTOR_SHUFFLE into VSHF.
2071 // This mostly consists of converting the shuffle indices in Indices into a
2072 // BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2073 // also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2074 // if the type is v8i16 and all the indices are less than 8 then the second
2075 // operand is unused and can be replaced with anything. We choose to replace it
2076 // with the used operand since this reduces the number of instructions overall.
2077 static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
2078 SmallVector<int, 16> Indices,
2079 SelectionDAG &DAG) {
2080 SmallVector<SDValue, 16> Ops;
2083 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2084 EVT MaskEltTy = MaskVecTy.getVectorElementType();
2085 bool Using1stVec = false;
2086 bool Using2ndVec = false;
2088 int ResTyNumElts = ResTy.getVectorNumElements();
2090 for (int i = 0; i < ResTyNumElts; ++i) {
2091 // Idx == -1 means UNDEF
2092 int Idx = Indices[i];
2094 if (0 <= Idx && Idx < ResTyNumElts)
2096 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2100 for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2102 Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy));
2104 SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, &Ops[0],
2107 if (Using1stVec && Using2ndVec) {
2108 Op0 = Op->getOperand(0);
2109 Op1 = Op->getOperand(1);
2110 } else if (Using1stVec)
2111 Op0 = Op1 = Op->getOperand(0);
2112 else if (Using2ndVec)
2113 Op0 = Op1 = Op->getOperand(1);
2115 llvm_unreachable("shuffle vector mask references neither vector operand?");
2117 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op0, Op1);
2120 // Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2121 // indices in the shuffle.
2122 SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2123 SelectionDAG &DAG) const {
2124 ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2125 EVT ResTy = Op->getValueType(0);
2127 if (!ResTy.is128BitVector())
2130 int ResTyNumElts = ResTy.getVectorNumElements();
2131 SmallVector<int, 16> Indices;
2133 for (int i = 0; i < ResTyNumElts; ++i)
2134 Indices.push_back(Node->getMaskElt(i));
2136 SDValue Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG);
2137 if (Result.getNode())
2139 Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG);
2140 if (Result.getNode())
2142 Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG);
2143 if (Result.getNode())
2145 Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG);
2146 if (Result.getNode())
2148 Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG);
2149 if (Result.getNode())
2151 Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG);
2152 if (Result.getNode())
2154 Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG);
2155 if (Result.getNode())
2157 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2160 MachineBasicBlock * MipsSETargetLowering::
2161 emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
2163 // bposge32_pseudo $vr0
2173 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
2175 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2176 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2177 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2178 DebugLoc DL = MI->getDebugLoc();
2179 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2180 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
2181 MachineFunction *F = BB->getParent();
2182 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2183 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2184 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2187 F->insert(It, Sink);
2189 // Transfer the remainder of BB and its successor edges to Sink.
2190 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
2192 Sink->transferSuccessorsAndUpdatePHIs(BB);
2195 BB->addSuccessor(FBB);
2196 BB->addSuccessor(TBB);
2197 FBB->addSuccessor(Sink);
2198 TBB->addSuccessor(Sink);
2200 // Insert the real bposge32 instruction to $BB.
2201 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
2204 unsigned VR2 = RegInfo.createVirtualRegister(RC);
2205 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
2206 .addReg(Mips::ZERO).addImm(0);
2207 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2210 unsigned VR1 = RegInfo.createVirtualRegister(RC);
2211 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
2212 .addReg(Mips::ZERO).addImm(1);
2214 // Insert phi function to $Sink.
2215 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2216 MI->getOperand(0).getReg())
2217 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
2219 MI->eraseFromParent(); // The pseudo instruction is gone now.
2223 MachineBasicBlock * MipsSETargetLowering::
2224 emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
2225 unsigned BranchOp) const{
2227 // vany_nonzero $rd, $ws
2238 // $rd = phi($rd1, $fbb, $rd2, $tbb)
2240 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2241 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2242 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2243 DebugLoc DL = MI->getDebugLoc();
2244 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2245 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
2246 MachineFunction *F = BB->getParent();
2247 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2248 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2249 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2252 F->insert(It, Sink);
2254 // Transfer the remainder of BB and its successor edges to Sink.
2255 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
2257 Sink->transferSuccessorsAndUpdatePHIs(BB);
2260 BB->addSuccessor(FBB);
2261 BB->addSuccessor(TBB);
2262 FBB->addSuccessor(Sink);
2263 TBB->addSuccessor(Sink);
2265 // Insert the real bnz.b instruction to $BB.
2266 BuildMI(BB, DL, TII->get(BranchOp))
2267 .addReg(MI->getOperand(1).getReg())
2271 unsigned RD1 = RegInfo.createVirtualRegister(RC);
2272 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
2273 .addReg(Mips::ZERO).addImm(0);
2274 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2277 unsigned RD2 = RegInfo.createVirtualRegister(RC);
2278 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
2279 .addReg(Mips::ZERO).addImm(1);
2281 // Insert phi function to $Sink.
2282 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2283 MI->getOperand(0).getReg())
2284 .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
2286 MI->eraseFromParent(); // The pseudo instruction is gone now.
2290 // Emit the COPY_FW pseudo instruction.
2292 // copy_fw_pseudo $fd, $ws, n
2294 // copy_u_w $rt, $ws, $n
2297 // When n is zero, the equivalent operation can be performed with (potentially)
2298 // zero instructions due to register overlaps. This optimization is never valid
2299 // for lane 1 because it would require FR=0 mode which isn't supported by MSA.
2300 MachineBasicBlock * MipsSETargetLowering::
2301 emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{
2302 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2303 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2304 DebugLoc DL = MI->getDebugLoc();
2305 unsigned Fd = MI->getOperand(0).getReg();
2306 unsigned Ws = MI->getOperand(1).getReg();
2307 unsigned Lane = MI->getOperand(2).getImm();
2310 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo);
2312 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2314 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(1);
2315 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
2318 MI->eraseFromParent(); // The pseudo instruction is gone now.
2322 // Emit the COPY_FD pseudo instruction.
2324 // copy_fd_pseudo $fd, $ws, n
2326 // splati.d $wt, $ws, $n
2327 // copy $fd, $wt:sub_64
2329 // When n is zero, the equivalent operation can be performed with (potentially)
2330 // zero instructions due to register overlaps. This optimization is always
2331 // valid because FR=1 mode which is the only supported mode in MSA.
2332 MachineBasicBlock * MipsSETargetLowering::
2333 emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{
2334 assert(Subtarget->isFP64bit());
2336 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2337 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2338 unsigned Fd = MI->getOperand(0).getReg();
2339 unsigned Ws = MI->getOperand(1).getReg();
2340 unsigned Lane = MI->getOperand(2).getImm() * 2;
2341 DebugLoc DL = MI->getDebugLoc();
2344 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
2346 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2348 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
2349 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
2352 MI->eraseFromParent(); // The pseudo instruction is gone now.
2356 // Emit the INSERT_FW pseudo instruction.
2358 // insert_fw_pseudo $wd, $wd_in, $n, $fs
2360 // subreg_to_reg $wt:sub_lo, $fs
2361 // insve_w $wd[$n], $wd_in, $wt[0]
2362 MachineBasicBlock * MipsSETargetLowering::
2363 emitINSERT_FW(MachineInstr *MI, MachineBasicBlock *BB) const{
2364 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2365 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2366 DebugLoc DL = MI->getDebugLoc();
2367 unsigned Wd = MI->getOperand(0).getReg();
2368 unsigned Wd_in = MI->getOperand(1).getReg();
2369 unsigned Lane = MI->getOperand(2).getImm();
2370 unsigned Fs = MI->getOperand(3).getReg();
2371 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2373 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2374 .addImm(0).addReg(Fs).addImm(Mips::sub_lo);
2375 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
2376 .addReg(Wd_in).addImm(Lane).addReg(Wt);
2378 MI->eraseFromParent(); // The pseudo instruction is gone now.
2382 // Emit the INSERT_FD pseudo instruction.
2384 // insert_fd_pseudo $wd, $fs, n
2386 // subreg_to_reg $wt:sub_64, $fs
2387 // insve_d $wd[$n], $wd_in, $wt[0]
2388 MachineBasicBlock * MipsSETargetLowering::
2389 emitINSERT_FD(MachineInstr *MI, MachineBasicBlock *BB) const{
2390 assert(Subtarget->isFP64bit());
2392 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2393 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2394 DebugLoc DL = MI->getDebugLoc();
2395 unsigned Wd = MI->getOperand(0).getReg();
2396 unsigned Wd_in = MI->getOperand(1).getReg();
2397 unsigned Lane = MI->getOperand(2).getImm();
2398 unsigned Fs = MI->getOperand(3).getReg();
2399 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2401 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2402 .addImm(0).addReg(Fs).addImm(Mips::sub_64);
2403 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
2404 .addReg(Wd_in).addImm(Lane).addReg(Wt);
2406 MI->eraseFromParent(); // The pseudo instruction is gone now.