1 //===-- MipsSEISelLowering.h - MipsSE DAG Lowering Interface ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
14 #ifndef MipsSEISELLOWERING_H
15 #define MipsSEISELLOWERING_H
17 #include "MipsISelLowering.h"
18 #include "MipsRegisterInfo.h"
21 class MipsSETargetLowering : public MipsTargetLowering {
23 explicit MipsSETargetLowering(MipsTargetMachine &TM);
25 void addMSAType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
27 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
29 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
31 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
33 virtual MachineBasicBlock *
34 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
36 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
41 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
42 if (VT == MVT::Untyped)
43 return Subtarget->hasDSP() ? &Mips::ACC64DSPRegClass :
46 return TargetLowering::getRepRegClassFor(VT);
51 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
52 unsigned NextStackOffset,
53 const MipsFunctionInfo& FI) const;
56 getOpndList(SmallVectorImpl<SDValue> &Ops,
57 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
58 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
59 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
61 SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
62 SelectionDAG &DAG) const;
64 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
65 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
66 SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
68 MachineBasicBlock *emitBPOSGE32(MachineInstr *MI,
69 MachineBasicBlock *BB) const;
70 MachineBasicBlock *emitMSACBranchPseudo(MachineInstr *MI,
71 MachineBasicBlock *BB,
72 unsigned BranchOp) const;
76 #endif // MipsSEISELLOWERING_H