1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsSEInstrInfo.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsTargetMachine.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/TargetRegistry.h"
27 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
28 cl::desc("Expand double precision loads and "
29 "stores to their single precision "
32 MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm)
34 tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J),
35 RI(*tm.getSubtargetImpl(), *this),
36 IsN64(tm.getSubtarget<MipsSubtarget>().isABI_N64()) {}
38 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
42 /// isLoadFromStackSlot - If the specified machine instruction is a direct
43 /// load from a stack slot, return the virtual or physical register number of
44 /// the destination along with the FrameIndex of the loaded stack slot. If
45 /// not, return 0. This predicate must return 0 if the instruction has
46 /// any side effects other than loading from the stack slot.
47 unsigned MipsSEInstrInfo::
48 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
50 unsigned Opc = MI->getOpcode();
52 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) ||
53 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) ||
54 (Opc == Mips::LDC1) || (Opc == Mips::LDC164) ||
55 (Opc == Mips::LDC164_P8)) {
56 if ((MI->getOperand(1).isFI()) && // is a stack slot
57 (MI->getOperand(2).isImm()) && // the imm is zero
58 (isZeroImm(MI->getOperand(2)))) {
59 FrameIndex = MI->getOperand(1).getIndex();
60 return MI->getOperand(0).getReg();
67 /// isStoreToStackSlot - If the specified machine instruction is a direct
68 /// store to a stack slot, return the virtual or physical register number of
69 /// the source reg along with the FrameIndex of the loaded stack slot. If
70 /// not, return 0. This predicate must return 0 if the instruction has
71 /// any side effects other than storing to the stack slot.
72 unsigned MipsSEInstrInfo::
73 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
75 unsigned Opc = MI->getOpcode();
77 if ((Opc == Mips::SW) || (Opc == Mips::SW_P8) || (Opc == Mips::SD) ||
78 (Opc == Mips::SD_P8) || (Opc == Mips::SWC1) || (Opc == Mips::SWC1_P8) ||
79 (Opc == Mips::SDC1) || (Opc == Mips::SDC164) ||
80 (Opc == Mips::SDC164_P8)) {
81 if ((MI->getOperand(1).isFI()) && // is a stack slot
82 (MI->getOperand(2).isImm()) && // the imm is zero
83 (isZeroImm(MI->getOperand(2)))) {
84 FrameIndex = MI->getOperand(1).getIndex();
85 return MI->getOperand(0).getReg();
91 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator I, DebugLoc DL,
93 unsigned DestReg, unsigned SrcReg,
95 unsigned Opc = 0, ZeroReg = 0;
97 if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
98 if (Mips::CPURegsRegClass.contains(SrcReg))
99 Opc = Mips::OR, ZeroReg = Mips::ZERO;
100 else if (Mips::CCRRegClass.contains(SrcReg))
102 else if (Mips::FGR32RegClass.contains(SrcReg))
104 else if (Mips::HIRegsRegClass.contains(SrcReg))
105 Opc = Mips::MFHI, SrcReg = 0;
106 else if (Mips::LORegsRegClass.contains(SrcReg))
107 Opc = Mips::MFLO, SrcReg = 0;
108 else if (Mips::HIRegsDSPRegClass.contains(SrcReg))
109 Opc = Mips::MFHI_DSP;
110 else if (Mips::LORegsDSPRegClass.contains(SrcReg))
111 Opc = Mips::MFLO_DSP;
112 else if (Mips::DSPCCRegClass.contains(SrcReg)) {
113 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
114 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
118 else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg.
119 if (Mips::CCRRegClass.contains(DestReg))
121 else if (Mips::FGR32RegClass.contains(DestReg))
123 else if (Mips::HIRegsRegClass.contains(DestReg))
124 Opc = Mips::MTHI, DestReg = 0;
125 else if (Mips::LORegsRegClass.contains(DestReg))
126 Opc = Mips::MTLO, DestReg = 0;
127 else if (Mips::HIRegsDSPRegClass.contains(DestReg))
128 Opc = Mips::MTHI_DSP;
129 else if (Mips::LORegsDSPRegClass.contains(DestReg))
130 Opc = Mips::MTLO_DSP;
131 else if (Mips::DSPCCRegClass.contains(DestReg)) {
132 BuildMI(MBB, I, DL, get(Mips::WRDSP))
133 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
134 .addReg(DestReg, RegState::ImplicitDefine);
138 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
140 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
141 Opc = Mips::FMOV_D32;
142 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
143 Opc = Mips::FMOV_D64;
144 else if (Mips::CCRRegClass.contains(DestReg, SrcReg))
145 Opc = Mips::MOVCCRToCCR;
146 else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.
147 if (Mips::CPU64RegsRegClass.contains(SrcReg))
148 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
149 else if (Mips::HIRegs64RegClass.contains(SrcReg))
150 Opc = Mips::MFHI64, SrcReg = 0;
151 else if (Mips::LORegs64RegClass.contains(SrcReg))
152 Opc = Mips::MFLO64, SrcReg = 0;
153 else if (Mips::FGR64RegClass.contains(SrcReg))
156 else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
157 if (Mips::HIRegs64RegClass.contains(DestReg))
158 Opc = Mips::MTHI64, DestReg = 0;
159 else if (Mips::LORegs64RegClass.contains(DestReg))
160 Opc = Mips::MTLO64, DestReg = 0;
161 else if (Mips::FGR64RegClass.contains(DestReg))
165 assert(Opc && "Cannot copy registers");
167 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
170 MIB.addReg(DestReg, RegState::Define);
173 MIB.addReg(SrcReg, getKillRegState(KillSrc));
179 void MipsSEInstrInfo::
180 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
181 unsigned SrcReg, bool isKill, int FI,
182 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
183 int64_t Offset) const {
185 if (I != MBB.end()) DL = I->getDebugLoc();
186 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
190 if (Mips::CPURegsRegClass.hasSubClassEq(RC))
191 Opc = IsN64 ? Mips::SW_P8 : Mips::SW;
192 else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
193 Opc = IsN64 ? Mips::SD_P8 : Mips::SD;
194 else if (Mips::ACRegsRegClass.hasSubClassEq(RC))
195 Opc = IsN64 ? Mips::STORE_AC64_P8 : Mips::STORE_AC64;
196 else if (Mips::ACRegsDSPRegClass.hasSubClassEq(RC))
197 Opc = IsN64 ? Mips::STORE_AC_DSP_P8 : Mips::STORE_AC_DSP;
198 else if (Mips::ACRegs128RegClass.hasSubClassEq(RC))
199 Opc = IsN64 ? Mips::STORE_AC128_P8 : Mips::STORE_AC128;
200 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
201 Opc = IsN64 ? Mips::STORE_CCOND_DSP_P8 : Mips::STORE_CCOND_DSP;
202 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
203 Opc = IsN64 ? Mips::SWC1_P8 : Mips::SWC1;
204 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
206 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
207 Opc = IsN64 ? Mips::SDC164_P8 : Mips::SDC164;
209 assert(Opc && "Register class not handled!");
210 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
211 .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
214 void MipsSEInstrInfo::
215 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
216 unsigned DestReg, int FI, const TargetRegisterClass *RC,
217 const TargetRegisterInfo *TRI, int64_t Offset) const {
219 if (I != MBB.end()) DL = I->getDebugLoc();
220 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
223 if (Mips::CPURegsRegClass.hasSubClassEq(RC))
224 Opc = IsN64 ? Mips::LW_P8 : Mips::LW;
225 else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
226 Opc = IsN64 ? Mips::LD_P8 : Mips::LD;
227 else if (Mips::ACRegsRegClass.hasSubClassEq(RC))
228 Opc = IsN64 ? Mips::LOAD_AC64_P8 : Mips::LOAD_AC64;
229 else if (Mips::ACRegsDSPRegClass.hasSubClassEq(RC))
230 Opc = IsN64 ? Mips::LOAD_AC_DSP_P8 : Mips::LOAD_AC_DSP;
231 else if (Mips::ACRegs128RegClass.hasSubClassEq(RC))
232 Opc = IsN64 ? Mips::LOAD_AC128_P8 : Mips::LOAD_AC128;
233 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
234 Opc = IsN64 ? Mips::LOAD_CCOND_DSP_P8 : Mips::LOAD_CCOND_DSP;
235 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
236 Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1;
237 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
239 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
240 Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164;
242 assert(Opc && "Register class not handled!");
243 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
247 bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
248 MachineBasicBlock &MBB = *MI->getParent();
250 switch(MI->getDesc().getOpcode()) {
254 expandRetRA(MBB, MI, Mips::RET);
256 case Mips::PseudoCVT_S_W:
257 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false, false, false);
259 case Mips::PseudoCVT_D32_W:
260 expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, true, false, false);
262 case Mips::PseudoCVT_S_L:
263 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, false, true, true);
265 case Mips::PseudoCVT_D64_W:
266 expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true, false, true);
268 case Mips::PseudoCVT_D64_L:
269 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, false, false, true);
271 case Mips::BuildPairF64:
272 expandBuildPairF64(MBB, MI);
274 case Mips::ExtractElementF64:
275 expandExtractElementF64(MBB, MI);
277 case Mips::PseudoLDC1:
278 expandDPLoadStore(MBB, MI, Mips::LDC1, Mips::LWC1);
280 case Mips::PseudoSDC1:
281 expandDPLoadStore(MBB, MI, Mips::SDC1, Mips::SWC1);
283 case Mips::MIPSeh_return32:
284 case Mips::MIPSeh_return64:
285 expandEhReturn(MBB, MI);
293 /// getOppositeBranchOpc - Return the inverse of the specified
294 /// opcode, e.g. turning BEQ to BNE.
295 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
297 default: llvm_unreachable("Illegal opcode!");
298 case Mips::BEQ: return Mips::BNE;
299 case Mips::BNE: return Mips::BEQ;
300 case Mips::BGTZ: return Mips::BLEZ;
301 case Mips::BGEZ: return Mips::BLTZ;
302 case Mips::BLTZ: return Mips::BGEZ;
303 case Mips::BLEZ: return Mips::BGTZ;
304 case Mips::BEQ64: return Mips::BNE64;
305 case Mips::BNE64: return Mips::BEQ64;
306 case Mips::BGTZ64: return Mips::BLEZ64;
307 case Mips::BGEZ64: return Mips::BLTZ64;
308 case Mips::BLTZ64: return Mips::BGEZ64;
309 case Mips::BLEZ64: return Mips::BGTZ64;
310 case Mips::BC1T: return Mips::BC1F;
311 case Mips::BC1F: return Mips::BC1T;
315 /// Adjust SP by Amount bytes.
316 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
317 MachineBasicBlock &MBB,
318 MachineBasicBlock::iterator I) const {
319 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
320 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
321 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
322 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
324 if (isInt<16>(Amount))// addi sp, sp, amount
325 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
326 else { // Expand immediate that doesn't fit in 16-bit.
327 unsigned Reg = loadImmediate(Amount, MBB, I, DL, 0);
328 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill);
332 /// This function generates the sequence of instructions needed to get the
333 /// result of adding register REG and immediate IMM.
335 MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
336 MachineBasicBlock::iterator II, DebugLoc DL,
337 unsigned *NewImm) const {
338 MipsAnalyzeImmediate AnalyzeImm;
339 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
340 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
341 unsigned Size = STI.isABI_N64() ? 64 : 32;
342 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
343 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
344 const TargetRegisterClass *RC = STI.isABI_N64() ?
345 &Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass;
346 bool LastInstrIsADDiu = NewImm;
348 const MipsAnalyzeImmediate::InstSeq &Seq =
349 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
350 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
352 assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
354 // The first instruction can be a LUi, which is different from other
355 // instructions (ADDiu, ORI and SLL) in that it does not have a register
357 unsigned Reg = RegInfo.createVirtualRegister(RC);
359 if (Inst->Opc == LUi)
360 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
362 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
363 .addImm(SignExtend64<16>(Inst->ImmOpnd));
365 // Build the remaining instructions in Seq.
366 for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
367 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
368 .addImm(SignExtend64<16>(Inst->ImmOpnd));
370 if (LastInstrIsADDiu)
371 *NewImm = Inst->ImmOpnd;
376 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
377 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
378 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ ||
379 Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 ||
380 Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
381 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B ||
386 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
387 MachineBasicBlock::iterator I,
388 unsigned Opc) const {
389 BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mips::RA);
392 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
393 MachineBasicBlock::iterator I,
394 unsigned CvtOpc, unsigned MovOpc,
395 bool DstIsLarger, bool SrcIsLarger,
397 const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
398 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
399 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
400 unsigned KillSrc = getKillRegState(Src.isKill());
401 DebugLoc DL = I->getDebugLoc();
402 unsigned SubIdx = (IsI64 ? Mips::sub_32 : Mips::sub_fpeven);
405 TmpReg = getRegisterInfo().getSubReg(DstReg, SubIdx);
408 DstReg = getRegisterInfo().getSubReg(DstReg, SubIdx);
410 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
411 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
414 void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
415 MachineBasicBlock::iterator I) const {
416 unsigned DstReg = I->getOperand(0).getReg();
417 unsigned SrcReg = I->getOperand(1).getReg();
418 unsigned N = I->getOperand(2).getImm();
419 const MCInstrDesc& Mfc1Tdd = get(Mips::MFC1);
420 DebugLoc dl = I->getDebugLoc();
422 assert(N < 2 && "Invalid immediate");
423 unsigned SubIdx = N ? Mips::sub_fpodd : Mips::sub_fpeven;
424 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
426 BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg);
429 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
430 MachineBasicBlock::iterator I) const {
431 unsigned DstReg = I->getOperand(0).getReg();
432 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
433 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
434 DebugLoc dl = I->getDebugLoc();
435 const TargetRegisterInfo &TRI = getRegisterInfo();
439 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpeven))
441 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpodd))
445 /// Add 4 to the displacement of operand MO.
446 static void fixDisp(MachineOperand &MO) {
447 switch (MO.getType()) {
449 llvm_unreachable("Unhandled operand type.");
450 case MachineOperand::MO_Immediate:
451 MO.setImm(MO.getImm() + 4);
453 case MachineOperand::MO_GlobalAddress:
454 case MachineOperand::MO_ConstantPoolIndex:
455 case MachineOperand::MO_BlockAddress:
456 case MachineOperand::MO_TargetIndex:
457 case MachineOperand::MO_ExternalSymbol:
458 MO.setOffset(MO.getOffset() + 4);
463 void MipsSEInstrInfo::expandDPLoadStore(MachineBasicBlock &MBB,
464 MachineBasicBlock::iterator I,
465 unsigned OpcD, unsigned OpcS) const {
466 // If NoDPLoadStore is false, just change the opcode.
467 if (!NoDPLoadStore) {
468 genInstrWithNewOpc(OpcD, I);
472 // Expand a double precision FP load or store to two single precision
475 const TargetRegisterInfo &TRI = getRegisterInfo();
476 const MachineOperand &ValReg = I->getOperand(0);
477 unsigned LoReg = TRI.getSubReg(ValReg.getReg(), Mips::sub_fpeven);
478 unsigned HiReg = TRI.getSubReg(ValReg.getReg(), Mips::sub_fpodd);
480 if (!TM.getSubtarget<MipsSubtarget>().isLittle())
481 std::swap(LoReg, HiReg);
483 // Create an instruction which loads from or stores to the lower memory
485 MachineInstrBuilder MIB = genInstrWithNewOpc(OpcS, I);
486 MIB->getOperand(0).setReg(LoReg);
488 // Create an instruction which loads from or stores to the higher memory
490 MIB = genInstrWithNewOpc(OpcS, I);
491 MIB->getOperand(0).setReg(HiReg);
492 fixDisp(MIB->getOperand(2));
495 void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
496 MachineBasicBlock::iterator I) const {
497 // This pseudo instruction is generated as part of the lowering of
498 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
499 // indirect jump to TargetReg
500 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
501 unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
502 unsigned OR = STI.isABI_N64() ? Mips::OR64 : Mips::OR;
503 unsigned JR = STI.isABI_N64() ? Mips::JR64 : Mips::JR;
504 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
505 unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA;
506 unsigned T9 = STI.isABI_N64() ? Mips::T9_64 : Mips::T9;
507 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
508 unsigned OffsetReg = I->getOperand(0).getReg();
509 unsigned TargetReg = I->getOperand(1).getReg();
511 // or $ra, $v0, $zero
512 // addu $sp, $sp, $v1
514 if (TM.getRelocationModel() == Reloc::PIC_)
515 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(OR), T9)
516 .addReg(TargetReg).addReg(ZERO);
517 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(OR), RA)
518 .addReg(TargetReg).addReg(ZERO);
519 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), SP)
520 .addReg(SP).addReg(OffsetReg);
521 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(JR)).addReg(RA);
524 const MipsInstrInfo *llvm::createMipsSEInstrInfo(MipsTargetMachine &TM) {
525 return new MipsSEInstrInfo(TM);