1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsSEInstrInfo.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsTargetMachine.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/TargetRegistry.h"
26 MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm)
28 tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J),
29 RI(*tm.getSubtargetImpl(), *this),
30 IsN64(tm.getSubtarget<MipsSubtarget>().isABI_N64()) {}
32 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
36 /// isLoadFromStackSlot - If the specified machine instruction is a direct
37 /// load from a stack slot, return the virtual or physical register number of
38 /// the destination along with the FrameIndex of the loaded stack slot. If
39 /// not, return 0. This predicate must return 0 if the instruction has
40 /// any side effects other than loading from the stack slot.
41 unsigned MipsSEInstrInfo::
42 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
44 unsigned Opc = MI->getOpcode();
46 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) ||
47 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) ||
48 (Opc == Mips::LDC1) || (Opc == Mips::LDC164) ||
49 (Opc == Mips::LDC164_P8)) {
50 if ((MI->getOperand(1).isFI()) && // is a stack slot
51 (MI->getOperand(2).isImm()) && // the imm is zero
52 (isZeroImm(MI->getOperand(2)))) {
53 FrameIndex = MI->getOperand(1).getIndex();
54 return MI->getOperand(0).getReg();
61 /// isStoreToStackSlot - If the specified machine instruction is a direct
62 /// store to a stack slot, return the virtual or physical register number of
63 /// the source reg along with the FrameIndex of the loaded stack slot. If
64 /// not, return 0. This predicate must return 0 if the instruction has
65 /// any side effects other than storing to the stack slot.
66 unsigned MipsSEInstrInfo::
67 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
69 unsigned Opc = MI->getOpcode();
71 if ((Opc == Mips::SW) || (Opc == Mips::SW_P8) || (Opc == Mips::SD) ||
72 (Opc == Mips::SD_P8) || (Opc == Mips::SWC1) || (Opc == Mips::SWC1_P8) ||
73 (Opc == Mips::SDC1) || (Opc == Mips::SDC164) ||
74 (Opc == Mips::SDC164_P8)) {
75 if ((MI->getOperand(1).isFI()) && // is a stack slot
76 (MI->getOperand(2).isImm()) && // the imm is zero
77 (isZeroImm(MI->getOperand(2)))) {
78 FrameIndex = MI->getOperand(1).getIndex();
79 return MI->getOperand(0).getReg();
85 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
86 MachineBasicBlock::iterator I, DebugLoc DL,
87 unsigned DestReg, unsigned SrcReg,
89 unsigned Opc = 0, ZeroReg = 0;
91 if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
92 if (Mips::CPURegsRegClass.contains(SrcReg))
93 Opc = Mips::OR, ZeroReg = Mips::ZERO;
94 else if (Mips::CCRRegClass.contains(SrcReg))
96 else if (Mips::FGR32RegClass.contains(SrcReg))
98 else if (SrcReg == Mips::HI)
99 Opc = Mips::MFHI, SrcReg = 0;
100 else if (SrcReg == Mips::LO)
101 Opc = Mips::MFLO, SrcReg = 0;
103 else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg.
104 if (Mips::CCRRegClass.contains(DestReg))
106 else if (Mips::FGR32RegClass.contains(DestReg))
108 else if (DestReg == Mips::HI)
109 Opc = Mips::MTHI, DestReg = 0;
110 else if (DestReg == Mips::LO)
111 Opc = Mips::MTLO, DestReg = 0;
113 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
115 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
116 Opc = Mips::FMOV_D32;
117 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
118 Opc = Mips::FMOV_D64;
119 else if (Mips::CCRRegClass.contains(DestReg, SrcReg))
120 Opc = Mips::MOVCCRToCCR;
121 else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.
122 if (Mips::CPU64RegsRegClass.contains(SrcReg))
123 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
124 else if (SrcReg == Mips::HI64)
125 Opc = Mips::MFHI64, SrcReg = 0;
126 else if (SrcReg == Mips::LO64)
127 Opc = Mips::MFLO64, SrcReg = 0;
128 else if (Mips::FGR64RegClass.contains(SrcReg))
131 else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
132 if (DestReg == Mips::HI64)
133 Opc = Mips::MTHI64, DestReg = 0;
134 else if (DestReg == Mips::LO64)
135 Opc = Mips::MTLO64, DestReg = 0;
136 else if (Mips::FGR64RegClass.contains(DestReg))
139 else if (Mips::ACRegsRegClass.contains(DestReg, SrcReg))
140 Opc = Mips::COPY_AC64;
141 else if (Mips::ACRegsDSPRegClass.contains(DestReg, SrcReg))
142 Opc = Mips::COPY_AC_DSP;
143 else if (Mips::ACRegs128RegClass.contains(DestReg, SrcReg))
144 Opc = Mips::COPY_AC128;
146 assert(Opc && "Cannot copy registers");
148 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
151 MIB.addReg(DestReg, RegState::Define);
154 MIB.addReg(SrcReg, getKillRegState(KillSrc));
160 void MipsSEInstrInfo::
161 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
162 unsigned SrcReg, bool isKill, int FI,
163 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
164 int64_t Offset) const {
166 if (I != MBB.end()) DL = I->getDebugLoc();
167 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
171 if (Mips::CPURegsRegClass.hasSubClassEq(RC))
172 Opc = IsN64 ? Mips::SW_P8 : Mips::SW;
173 else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
174 Opc = IsN64 ? Mips::SD_P8 : Mips::SD;
175 else if (Mips::ACRegsRegClass.hasSubClassEq(RC))
176 Opc = IsN64 ? Mips::STORE_AC64_P8 : Mips::STORE_AC64;
177 else if (Mips::ACRegsDSPRegClass.hasSubClassEq(RC))
178 Opc = IsN64 ? Mips::STORE_AC_DSP_P8 : Mips::STORE_AC_DSP;
179 else if (Mips::ACRegs128RegClass.hasSubClassEq(RC))
180 Opc = IsN64 ? Mips::STORE_AC128_P8 : Mips::STORE_AC128;
181 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
182 Opc = IsN64 ? Mips::SWC1_P8 : Mips::SWC1;
183 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
185 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
186 Opc = IsN64 ? Mips::SDC164_P8 : Mips::SDC164;
188 assert(Opc && "Register class not handled!");
189 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
190 .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
193 void MipsSEInstrInfo::
194 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
195 unsigned DestReg, int FI, const TargetRegisterClass *RC,
196 const TargetRegisterInfo *TRI, int64_t Offset) const {
198 if (I != MBB.end()) DL = I->getDebugLoc();
199 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
202 if (Mips::CPURegsRegClass.hasSubClassEq(RC))
203 Opc = IsN64 ? Mips::LW_P8 : Mips::LW;
204 else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
205 Opc = IsN64 ? Mips::LD_P8 : Mips::LD;
206 else if (Mips::ACRegsRegClass.hasSubClassEq(RC))
207 Opc = IsN64 ? Mips::LOAD_AC64_P8 : Mips::LOAD_AC64;
208 else if (Mips::ACRegsDSPRegClass.hasSubClassEq(RC))
209 Opc = IsN64 ? Mips::LOAD_AC_DSP_P8 : Mips::LOAD_AC_DSP;
210 else if (Mips::ACRegs128RegClass.hasSubClassEq(RC))
211 Opc = IsN64 ? Mips::LOAD_AC128_P8 : Mips::LOAD_AC128;
212 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
213 Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1;
214 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
216 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
217 Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164;
219 assert(Opc && "Register class not handled!");
220 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
224 bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
225 MachineBasicBlock &MBB = *MI->getParent();
227 switch(MI->getDesc().getOpcode()) {
231 ExpandRetRA(MBB, MI, Mips::RET);
233 case Mips::BuildPairF64:
234 ExpandBuildPairF64(MBB, MI);
236 case Mips::ExtractElementF64:
237 ExpandExtractElementF64(MBB, MI);
239 case Mips::MIPSeh_return32:
240 case Mips::MIPSeh_return64:
241 ExpandEhReturn(MBB, MI);
249 /// GetOppositeBranchOpc - Return the inverse of the specified
250 /// opcode, e.g. turning BEQ to BNE.
251 unsigned MipsSEInstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
253 default: llvm_unreachable("Illegal opcode!");
254 case Mips::BEQ: return Mips::BNE;
255 case Mips::BNE: return Mips::BEQ;
256 case Mips::BGTZ: return Mips::BLEZ;
257 case Mips::BGEZ: return Mips::BLTZ;
258 case Mips::BLTZ: return Mips::BGEZ;
259 case Mips::BLEZ: return Mips::BGTZ;
260 case Mips::BEQ64: return Mips::BNE64;
261 case Mips::BNE64: return Mips::BEQ64;
262 case Mips::BGTZ64: return Mips::BLEZ64;
263 case Mips::BGEZ64: return Mips::BLTZ64;
264 case Mips::BLTZ64: return Mips::BGEZ64;
265 case Mips::BLEZ64: return Mips::BGTZ64;
266 case Mips::BC1T: return Mips::BC1F;
267 case Mips::BC1F: return Mips::BC1T;
271 /// Adjust SP by Amount bytes.
272 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
273 MachineBasicBlock &MBB,
274 MachineBasicBlock::iterator I) const {
275 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
276 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
277 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
278 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
280 if (isInt<16>(Amount))// addi sp, sp, amount
281 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
282 else { // Expand immediate that doesn't fit in 16-bit.
283 unsigned Reg = loadImmediate(Amount, MBB, I, DL, 0);
284 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill);
288 /// This function generates the sequence of instructions needed to get the
289 /// result of adding register REG and immediate IMM.
291 MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
292 MachineBasicBlock::iterator II, DebugLoc DL,
293 unsigned *NewImm) const {
294 MipsAnalyzeImmediate AnalyzeImm;
295 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
296 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
297 unsigned Size = STI.isABI_N64() ? 64 : 32;
298 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
299 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
300 const TargetRegisterClass *RC = STI.isABI_N64() ?
301 &Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass;
302 bool LastInstrIsADDiu = NewImm;
304 const MipsAnalyzeImmediate::InstSeq &Seq =
305 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
306 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
308 assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
310 // The first instruction can be a LUi, which is different from other
311 // instructions (ADDiu, ORI and SLL) in that it does not have a register
313 unsigned Reg = RegInfo.createVirtualRegister(RC);
315 if (Inst->Opc == LUi)
316 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
318 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
319 .addImm(SignExtend64<16>(Inst->ImmOpnd));
321 // Build the remaining instructions in Seq.
322 for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
323 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
324 .addImm(SignExtend64<16>(Inst->ImmOpnd));
326 if (LastInstrIsADDiu)
327 *NewImm = Inst->ImmOpnd;
332 unsigned MipsSEInstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
333 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
334 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ ||
335 Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 ||
336 Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
337 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B ||
342 void MipsSEInstrInfo::ExpandRetRA(MachineBasicBlock &MBB,
343 MachineBasicBlock::iterator I,
344 unsigned Opc) const {
345 BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mips::RA);
348 void MipsSEInstrInfo::ExpandExtractElementF64(MachineBasicBlock &MBB,
349 MachineBasicBlock::iterator I) const {
350 unsigned DstReg = I->getOperand(0).getReg();
351 unsigned SrcReg = I->getOperand(1).getReg();
352 unsigned N = I->getOperand(2).getImm();
353 const MCInstrDesc& Mfc1Tdd = get(Mips::MFC1);
354 DebugLoc dl = I->getDebugLoc();
356 assert(N < 2 && "Invalid immediate");
357 unsigned SubIdx = N ? Mips::sub_fpodd : Mips::sub_fpeven;
358 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
360 BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg);
363 void MipsSEInstrInfo::ExpandBuildPairF64(MachineBasicBlock &MBB,
364 MachineBasicBlock::iterator I) const {
365 unsigned DstReg = I->getOperand(0).getReg();
366 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
367 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
368 DebugLoc dl = I->getDebugLoc();
369 const TargetRegisterInfo &TRI = getRegisterInfo();
373 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpeven))
375 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpodd))
379 void MipsSEInstrInfo::ExpandEhReturn(MachineBasicBlock &MBB,
380 MachineBasicBlock::iterator I) const {
381 // This pseudo instruction is generated as part of the lowering of
382 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
383 // indirect jump to TargetReg
384 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
385 unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
386 unsigned OR = STI.isABI_N64() ? Mips::OR64 : Mips::OR;
387 unsigned JR = STI.isABI_N64() ? Mips::JR64 : Mips::JR;
388 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
389 unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA;
390 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
391 unsigned OffsetReg = I->getOperand(0).getReg();
392 unsigned TargetReg = I->getOperand(1).getReg();
394 // or $ra, $v0, $zero
395 // addu $sp, $sp, $v1
397 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(OR), RA)
398 .addReg(TargetReg).addReg(ZERO);
399 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), SP)
400 .addReg(SP).addReg(OffsetReg);
401 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(JR)).addReg(RA);
404 const MipsInstrInfo *llvm::createMipsSEInstrInfo(MipsTargetMachine &TM) {
405 return new MipsSEInstrInfo(TM);