1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsSEInstrInfo.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsTargetMachine.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/TargetRegistry.h"
27 MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm)
29 tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J),
30 RI(*tm.getSubtargetImpl()),
31 IsN64(tm.getSubtarget<MipsSubtarget>().isABI_N64()) {}
33 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
37 /// isLoadFromStackSlot - If the specified machine instruction is a direct
38 /// load from a stack slot, return the virtual or physical register number of
39 /// the destination along with the FrameIndex of the loaded stack slot. If
40 /// not, return 0. This predicate must return 0 if the instruction has
41 /// any side effects other than loading from the stack slot.
42 unsigned MipsSEInstrInfo::
43 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
45 unsigned Opc = MI->getOpcode();
47 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
48 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
49 if ((MI->getOperand(1).isFI()) && // is a stack slot
50 (MI->getOperand(2).isImm()) && // the imm is zero
51 (isZeroImm(MI->getOperand(2)))) {
52 FrameIndex = MI->getOperand(1).getIndex();
53 return MI->getOperand(0).getReg();
60 /// isStoreToStackSlot - If the specified machine instruction is a direct
61 /// store to a stack slot, return the virtual or physical register number of
62 /// the source reg along with the FrameIndex of the loaded stack slot. If
63 /// not, return 0. This predicate must return 0 if the instruction has
64 /// any side effects other than storing to the stack slot.
65 unsigned MipsSEInstrInfo::
66 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
68 unsigned Opc = MI->getOpcode();
70 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
71 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
72 if ((MI->getOperand(1).isFI()) && // is a stack slot
73 (MI->getOperand(2).isImm()) && // the imm is zero
74 (isZeroImm(MI->getOperand(2)))) {
75 FrameIndex = MI->getOperand(1).getIndex();
76 return MI->getOperand(0).getReg();
82 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
83 MachineBasicBlock::iterator I, DebugLoc DL,
84 unsigned DestReg, unsigned SrcReg,
86 unsigned Opc = 0, ZeroReg = 0;
88 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
89 if (Mips::GPR32RegClass.contains(SrcReg))
90 Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
91 else if (Mips::CCRRegClass.contains(SrcReg))
93 else if (Mips::FGR32RegClass.contains(SrcReg))
95 else if (Mips::HI32RegClass.contains(SrcReg))
96 Opc = Mips::MFHI, SrcReg = 0;
97 else if (Mips::LO32RegClass.contains(SrcReg))
98 Opc = Mips::MFLO, SrcReg = 0;
99 else if (Mips::HI32DSPRegClass.contains(SrcReg))
100 Opc = Mips::MFHI_DSP;
101 else if (Mips::LO32DSPRegClass.contains(SrcReg))
102 Opc = Mips::MFLO_DSP;
103 else if (Mips::DSPCCRegClass.contains(SrcReg)) {
104 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
105 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
108 else if (Mips::MSACtrlRegClass.contains(SrcReg))
111 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
112 if (Mips::CCRRegClass.contains(DestReg))
114 else if (Mips::FGR32RegClass.contains(DestReg))
116 else if (Mips::HI32RegClass.contains(DestReg))
117 Opc = Mips::MTHI, DestReg = 0;
118 else if (Mips::LO32RegClass.contains(DestReg))
119 Opc = Mips::MTLO, DestReg = 0;
120 else if (Mips::HI32DSPRegClass.contains(DestReg))
121 Opc = Mips::MTHI_DSP;
122 else if (Mips::LO32DSPRegClass.contains(DestReg))
123 Opc = Mips::MTLO_DSP;
124 else if (Mips::DSPCCRegClass.contains(DestReg)) {
125 BuildMI(MBB, I, DL, get(Mips::WRDSP))
126 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
127 .addReg(DestReg, RegState::ImplicitDefine);
130 else if (Mips::MSACtrlRegClass.contains(DestReg))
133 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
135 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
136 Opc = Mips::FMOV_D32;
137 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
138 Opc = Mips::FMOV_D64;
139 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
140 if (Mips::GPR64RegClass.contains(SrcReg))
141 Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
142 else if (Mips::HI64RegClass.contains(SrcReg))
143 Opc = Mips::MFHI64, SrcReg = 0;
144 else if (Mips::LO64RegClass.contains(SrcReg))
145 Opc = Mips::MFLO64, SrcReg = 0;
146 else if (Mips::FGR64RegClass.contains(SrcReg))
149 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
150 if (Mips::HI64RegClass.contains(DestReg))
151 Opc = Mips::MTHI64, DestReg = 0;
152 else if (Mips::LO64RegClass.contains(DestReg))
153 Opc = Mips::MTLO64, DestReg = 0;
154 else if (Mips::FGR64RegClass.contains(DestReg))
157 else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
158 if (Mips::MSA128BRegClass.contains(SrcReg))
162 assert(Opc && "Cannot copy registers");
164 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
167 MIB.addReg(DestReg, RegState::Define);
170 MIB.addReg(SrcReg, getKillRegState(KillSrc));
176 void MipsSEInstrInfo::
177 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
178 unsigned SrcReg, bool isKill, int FI,
179 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
180 int64_t Offset) const {
182 if (I != MBB.end()) DL = I->getDebugLoc();
183 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
187 if (Mips::GPR32RegClass.hasSubClassEq(RC))
189 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
191 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
192 Opc = Mips::STORE_ACC64;
193 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
194 Opc = Mips::STORE_ACC64DSP;
195 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
196 Opc = Mips::STORE_ACC128;
197 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
198 Opc = Mips::STORE_CCOND_DSP;
199 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
201 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
203 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
205 else if (RC->hasType(MVT::v16i8))
207 else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16))
209 else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
211 else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
214 assert(Opc && "Register class not handled!");
215 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
216 .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
219 void MipsSEInstrInfo::
220 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
221 unsigned DestReg, int FI, const TargetRegisterClass *RC,
222 const TargetRegisterInfo *TRI, int64_t Offset) const {
224 if (I != MBB.end()) DL = I->getDebugLoc();
225 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
228 if (Mips::GPR32RegClass.hasSubClassEq(RC))
230 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
232 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
233 Opc = Mips::LOAD_ACC64;
234 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
235 Opc = Mips::LOAD_ACC64DSP;
236 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
237 Opc = Mips::LOAD_ACC128;
238 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
239 Opc = Mips::LOAD_CCOND_DSP;
240 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
242 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
244 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
246 else if (RC->hasType(MVT::v16i8))
248 else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16))
250 else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
252 else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
255 assert(Opc && "Register class not handled!");
256 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
260 bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
261 MachineBasicBlock &MBB = *MI->getParent();
263 switch(MI->getDesc().getOpcode()) {
267 expandRetRA(MBB, MI, Mips::RET);
269 case Mips::PseudoMFHI:
270 expandPseudoMFHiLo(MBB, MI, Mips::MFHI);
272 case Mips::PseudoMFLO:
273 expandPseudoMFHiLo(MBB, MI, Mips::MFLO);
275 case Mips::PseudoMFHI64:
276 expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
278 case Mips::PseudoMFLO64:
279 expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
281 case Mips::PseudoMTLOHI:
282 expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);
284 case Mips::PseudoMTLOHI64:
285 expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);
287 case Mips::PseudoMTLOHI_DSP:
288 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
290 case Mips::PseudoCVT_S_W:
291 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
293 case Mips::PseudoCVT_D32_W:
294 expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false);
296 case Mips::PseudoCVT_S_L:
297 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
299 case Mips::PseudoCVT_D64_W:
300 expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true);
302 case Mips::PseudoCVT_D64_L:
303 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
305 case Mips::BuildPairF64:
306 expandBuildPairF64(MBB, MI, false);
308 case Mips::BuildPairF64_64:
309 expandBuildPairF64(MBB, MI, true);
311 case Mips::ExtractElementF64:
312 expandExtractElementF64(MBB, MI, false);
314 case Mips::ExtractElementF64_64:
315 expandExtractElementF64(MBB, MI, true);
317 case Mips::MIPSeh_return32:
318 case Mips::MIPSeh_return64:
319 expandEhReturn(MBB, MI);
327 /// getOppositeBranchOpc - Return the inverse of the specified
328 /// opcode, e.g. turning BEQ to BNE.
329 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
331 default: llvm_unreachable("Illegal opcode!");
332 case Mips::BEQ: return Mips::BNE;
333 case Mips::BNE: return Mips::BEQ;
334 case Mips::BGTZ: return Mips::BLEZ;
335 case Mips::BGEZ: return Mips::BLTZ;
336 case Mips::BLTZ: return Mips::BGEZ;
337 case Mips::BLEZ: return Mips::BGTZ;
338 case Mips::BEQ64: return Mips::BNE64;
339 case Mips::BNE64: return Mips::BEQ64;
340 case Mips::BGTZ64: return Mips::BLEZ64;
341 case Mips::BGEZ64: return Mips::BLTZ64;
342 case Mips::BLTZ64: return Mips::BGEZ64;
343 case Mips::BLEZ64: return Mips::BGTZ64;
344 case Mips::BC1T: return Mips::BC1F;
345 case Mips::BC1F: return Mips::BC1T;
349 /// Adjust SP by Amount bytes.
350 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
351 MachineBasicBlock &MBB,
352 MachineBasicBlock::iterator I) const {
353 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
354 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
355 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
356 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
358 if (isInt<16>(Amount))// addi sp, sp, amount
359 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
360 else { // Expand immediate that doesn't fit in 16-bit.
361 unsigned Reg = loadImmediate(Amount, MBB, I, DL, 0);
362 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill);
366 /// This function generates the sequence of instructions needed to get the
367 /// result of adding register REG and immediate IMM.
369 MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
370 MachineBasicBlock::iterator II, DebugLoc DL,
371 unsigned *NewImm) const {
372 MipsAnalyzeImmediate AnalyzeImm;
373 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
374 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
375 unsigned Size = STI.isABI_N64() ? 64 : 32;
376 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
377 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
378 const TargetRegisterClass *RC = STI.isABI_N64() ?
379 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
380 bool LastInstrIsADDiu = NewImm;
382 const MipsAnalyzeImmediate::InstSeq &Seq =
383 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
384 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
386 assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
388 // The first instruction can be a LUi, which is different from other
389 // instructions (ADDiu, ORI and SLL) in that it does not have a register
391 unsigned Reg = RegInfo.createVirtualRegister(RC);
393 if (Inst->Opc == LUi)
394 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
396 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
397 .addImm(SignExtend64<16>(Inst->ImmOpnd));
399 // Build the remaining instructions in Seq.
400 for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
401 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
402 .addImm(SignExtend64<16>(Inst->ImmOpnd));
404 if (LastInstrIsADDiu)
405 *NewImm = Inst->ImmOpnd;
410 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
411 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
412 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ ||
413 Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 ||
414 Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
415 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B ||
420 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
421 MachineBasicBlock::iterator I,
422 unsigned Opc) const {
423 BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mips::RA);
426 std::pair<bool, bool>
427 MipsSEInstrInfo::compareOpndSize(unsigned Opc,
428 const MachineFunction &MF) const {
429 const MCInstrDesc &Desc = get(Opc);
430 assert(Desc.NumOperands == 2 && "Unary instruction expected.");
431 const MipsRegisterInfo *RI = &getRegisterInfo();
432 unsigned DstRegSize = getRegClass(Desc, 0, RI, MF)->getSize();
433 unsigned SrcRegSize = getRegClass(Desc, 1, RI, MF)->getSize();
435 return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
438 void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB,
439 MachineBasicBlock::iterator I,
440 unsigned NewOpc) const {
441 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
444 void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
445 MachineBasicBlock::iterator I,
448 bool HasExplicitDef) const {
450 // lo_hi pseudomtlohi $gpr0, $gpr1
451 // to these two instructions:
455 DebugLoc DL = I->getDebugLoc();
456 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
457 MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
458 MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
459 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
460 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
462 // Add lo/hi registers if the mtlo/hi instructions created have explicit
464 if (HasExplicitDef) {
465 unsigned DstReg = I->getOperand(0).getReg();
466 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
467 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
468 LoInst.addReg(DstLo, RegState::Define);
469 HiInst.addReg(DstHi, RegState::Define);
473 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
474 MachineBasicBlock::iterator I,
475 unsigned CvtOpc, unsigned MovOpc,
477 const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
478 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
479 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
480 unsigned KillSrc = getKillRegState(Src.isKill());
481 DebugLoc DL = I->getDebugLoc();
482 bool DstIsLarger, SrcIsLarger;
484 std::tie(DstIsLarger, SrcIsLarger) =
485 compareOpndSize(CvtOpc, *MBB.getParent());
488 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
491 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
493 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
494 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
497 void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
498 MachineBasicBlock::iterator I,
500 unsigned DstReg = I->getOperand(0).getReg();
501 unsigned SrcReg = I->getOperand(1).getReg();
502 unsigned N = I->getOperand(2).getImm();
503 DebugLoc dl = I->getDebugLoc();
505 assert(N < 2 && "Invalid immediate");
506 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
507 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
509 if (SubIdx == Mips::sub_hi && FP64) {
510 // FIXME: The .addReg(SrcReg, RegState::Implicit) is a white lie used to
511 // temporarily work around a widespread bug in the -mfp64 support.
512 // The problem is that none of the 32-bit fpu ops mention the fact
513 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
514 // requires a major overhaul of the FPU implementation which can't
515 // be done right now due to time constraints.
516 // MFHC1 is the only instruction that is affected since it is the
517 // only instruction that doesn't read the lower 32-bits. We therefore
518 // pretend that it reads the bottom 32-bits to artificially create a
519 // dependency and prevent the scheduler changing the behaviour of the
521 BuildMI(MBB, I, dl, get(Mips::MFHC1), DstReg).addReg(SubReg).addReg(
522 SrcReg, RegState::Implicit);
524 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
527 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
528 MachineBasicBlock::iterator I,
530 unsigned DstReg = I->getOperand(0).getReg();
531 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
532 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
533 DebugLoc dl = I->getDebugLoc();
534 const TargetRegisterInfo &TRI = getRegisterInfo();
543 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
547 BuildMI(MBB, I, dl, get(Mips::MTHC1), TRI.getSubReg(DstReg, Mips::sub_hi))
550 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
554 void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
555 MachineBasicBlock::iterator I) const {
556 // This pseudo instruction is generated as part of the lowering of
557 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
558 // indirect jump to TargetReg
559 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
560 unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
561 unsigned JR = STI.isABI_N64() ? Mips::JR64 : Mips::JR;
562 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
563 unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA;
564 unsigned T9 = STI.isABI_N64() ? Mips::T9_64 : Mips::T9;
565 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
566 unsigned OffsetReg = I->getOperand(0).getReg();
567 unsigned TargetReg = I->getOperand(1).getReg();
569 // addu $ra, $v0, $zero
570 // addu $sp, $sp, $v1
572 if (TM.getRelocationModel() == Reloc::PIC_)
573 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), T9)
574 .addReg(TargetReg).addReg(ZERO);
575 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), RA)
576 .addReg(TargetReg).addReg(ZERO);
577 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), SP)
578 .addReg(SP).addReg(OffsetReg);
579 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(JR)).addReg(RA);
582 const MipsInstrInfo *llvm::createMipsSEInstrInfo(MipsTargetMachine &TM) {
583 return new MipsSEInstrInfo(TM);