1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsSEInstrInfo.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsTargetMachine.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/TargetRegistry.h"
27 MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm)
29 tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J),
30 RI(*tm.getSubtargetImpl()),
31 IsN64(tm.getSubtarget<MipsSubtarget>().isABI_N64()) {}
33 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
37 /// isLoadFromStackSlot - If the specified machine instruction is a direct
38 /// load from a stack slot, return the virtual or physical register number of
39 /// the destination along with the FrameIndex of the loaded stack slot. If
40 /// not, return 0. This predicate must return 0 if the instruction has
41 /// any side effects other than loading from the stack slot.
42 unsigned MipsSEInstrInfo::
43 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
45 unsigned Opc = MI->getOpcode();
47 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
48 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
49 if ((MI->getOperand(1).isFI()) && // is a stack slot
50 (MI->getOperand(2).isImm()) && // the imm is zero
51 (isZeroImm(MI->getOperand(2)))) {
52 FrameIndex = MI->getOperand(1).getIndex();
53 return MI->getOperand(0).getReg();
60 /// isStoreToStackSlot - If the specified machine instruction is a direct
61 /// store to a stack slot, return the virtual or physical register number of
62 /// the source reg along with the FrameIndex of the loaded stack slot. If
63 /// not, return 0. This predicate must return 0 if the instruction has
64 /// any side effects other than storing to the stack slot.
65 unsigned MipsSEInstrInfo::
66 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
68 unsigned Opc = MI->getOpcode();
70 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
71 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
72 if ((MI->getOperand(1).isFI()) && // is a stack slot
73 (MI->getOperand(2).isImm()) && // the imm is zero
74 (isZeroImm(MI->getOperand(2)))) {
75 FrameIndex = MI->getOperand(1).getIndex();
76 return MI->getOperand(0).getReg();
82 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
83 MachineBasicBlock::iterator I, DebugLoc DL,
84 unsigned DestReg, unsigned SrcReg,
86 unsigned Opc = 0, ZeroReg = 0;
87 bool isMicroMips = TM.getSubtarget<MipsSubtarget>().inMicroMipsMode();
89 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
90 if (Mips::GPR32RegClass.contains(SrcReg)) {
92 Opc = Mips::MOVE16_MM;
94 Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
95 } else if (Mips::CCRRegClass.contains(SrcReg))
97 else if (Mips::FGR32RegClass.contains(SrcReg))
99 else if (Mips::HI32RegClass.contains(SrcReg)) {
100 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
102 } else if (Mips::LO32RegClass.contains(SrcReg)) {
103 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
105 } else if (Mips::HI32DSPRegClass.contains(SrcReg))
106 Opc = Mips::MFHI_DSP;
107 else if (Mips::LO32DSPRegClass.contains(SrcReg))
108 Opc = Mips::MFLO_DSP;
109 else if (Mips::DSPCCRegClass.contains(SrcReg)) {
110 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
111 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
114 else if (Mips::MSACtrlRegClass.contains(SrcReg))
117 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
118 if (Mips::CCRRegClass.contains(DestReg))
120 else if (Mips::FGR32RegClass.contains(DestReg))
122 else if (Mips::HI32RegClass.contains(DestReg))
123 Opc = Mips::MTHI, DestReg = 0;
124 else if (Mips::LO32RegClass.contains(DestReg))
125 Opc = Mips::MTLO, DestReg = 0;
126 else if (Mips::HI32DSPRegClass.contains(DestReg))
127 Opc = Mips::MTHI_DSP;
128 else if (Mips::LO32DSPRegClass.contains(DestReg))
129 Opc = Mips::MTLO_DSP;
130 else if (Mips::DSPCCRegClass.contains(DestReg)) {
131 BuildMI(MBB, I, DL, get(Mips::WRDSP))
132 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
133 .addReg(DestReg, RegState::ImplicitDefine);
136 else if (Mips::MSACtrlRegClass.contains(DestReg))
139 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
141 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
142 Opc = Mips::FMOV_D32;
143 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
144 Opc = Mips::FMOV_D64;
145 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
146 if (Mips::GPR64RegClass.contains(SrcReg))
147 Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
148 else if (Mips::HI64RegClass.contains(SrcReg))
149 Opc = Mips::MFHI64, SrcReg = 0;
150 else if (Mips::LO64RegClass.contains(SrcReg))
151 Opc = Mips::MFLO64, SrcReg = 0;
152 else if (Mips::FGR64RegClass.contains(SrcReg))
155 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
156 if (Mips::HI64RegClass.contains(DestReg))
157 Opc = Mips::MTHI64, DestReg = 0;
158 else if (Mips::LO64RegClass.contains(DestReg))
159 Opc = Mips::MTLO64, DestReg = 0;
160 else if (Mips::FGR64RegClass.contains(DestReg))
163 else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
164 if (Mips::MSA128BRegClass.contains(SrcReg))
168 assert(Opc && "Cannot copy registers");
170 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
173 MIB.addReg(DestReg, RegState::Define);
176 MIB.addReg(SrcReg, getKillRegState(KillSrc));
182 void MipsSEInstrInfo::
183 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
184 unsigned SrcReg, bool isKill, int FI,
185 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
186 int64_t Offset) const {
188 if (I != MBB.end()) DL = I->getDebugLoc();
189 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
193 if (Mips::GPR32RegClass.hasSubClassEq(RC))
195 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
197 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
198 Opc = Mips::STORE_ACC64;
199 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
200 Opc = Mips::STORE_ACC64DSP;
201 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
202 Opc = Mips::STORE_ACC128;
203 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
204 Opc = Mips::STORE_CCOND_DSP;
205 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
207 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
209 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
211 else if (RC->hasType(MVT::v16i8))
213 else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16))
215 else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
217 else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
220 assert(Opc && "Register class not handled!");
221 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
222 .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
225 void MipsSEInstrInfo::
226 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
227 unsigned DestReg, int FI, const TargetRegisterClass *RC,
228 const TargetRegisterInfo *TRI, int64_t Offset) const {
230 if (I != MBB.end()) DL = I->getDebugLoc();
231 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
234 if (Mips::GPR32RegClass.hasSubClassEq(RC))
236 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
238 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
239 Opc = Mips::LOAD_ACC64;
240 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
241 Opc = Mips::LOAD_ACC64DSP;
242 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
243 Opc = Mips::LOAD_ACC128;
244 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
245 Opc = Mips::LOAD_CCOND_DSP;
246 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
248 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
250 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
252 else if (RC->hasType(MVT::v16i8))
254 else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16))
256 else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
258 else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
261 assert(Opc && "Register class not handled!");
262 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
266 bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
267 MachineBasicBlock &MBB = *MI->getParent();
268 bool isMicroMips = TM.getSubtarget<MipsSubtarget>().inMicroMipsMode();
271 switch(MI->getDesc().getOpcode()) {
275 expandRetRA(MBB, MI);
277 case Mips::PseudoMFHI:
278 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
279 expandPseudoMFHiLo(MBB, MI, Opc);
281 case Mips::PseudoMFLO:
282 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
283 expandPseudoMFHiLo(MBB, MI, Opc);
285 case Mips::PseudoMFHI64:
286 expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
288 case Mips::PseudoMFLO64:
289 expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
291 case Mips::PseudoMTLOHI:
292 expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);
294 case Mips::PseudoMTLOHI64:
295 expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);
297 case Mips::PseudoMTLOHI_DSP:
298 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
300 case Mips::PseudoCVT_S_W:
301 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
303 case Mips::PseudoCVT_D32_W:
304 expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false);
306 case Mips::PseudoCVT_S_L:
307 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
309 case Mips::PseudoCVT_D64_W:
310 expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true);
312 case Mips::PseudoCVT_D64_L:
313 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
315 case Mips::BuildPairF64:
316 expandBuildPairF64(MBB, MI, false);
318 case Mips::BuildPairF64_64:
319 expandBuildPairF64(MBB, MI, true);
321 case Mips::ExtractElementF64:
322 expandExtractElementF64(MBB, MI, false);
324 case Mips::ExtractElementF64_64:
325 expandExtractElementF64(MBB, MI, true);
327 case Mips::MIPSeh_return32:
328 case Mips::MIPSeh_return64:
329 expandEhReturn(MBB, MI);
337 /// getOppositeBranchOpc - Return the inverse of the specified
338 /// opcode, e.g. turning BEQ to BNE.
339 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
341 default: llvm_unreachable("Illegal opcode!");
342 case Mips::BEQ: return Mips::BNE;
343 case Mips::BNE: return Mips::BEQ;
344 case Mips::BGTZ: return Mips::BLEZ;
345 case Mips::BGEZ: return Mips::BLTZ;
346 case Mips::BLTZ: return Mips::BGEZ;
347 case Mips::BLEZ: return Mips::BGTZ;
348 case Mips::BEQ64: return Mips::BNE64;
349 case Mips::BNE64: return Mips::BEQ64;
350 case Mips::BGTZ64: return Mips::BLEZ64;
351 case Mips::BGEZ64: return Mips::BLTZ64;
352 case Mips::BLTZ64: return Mips::BGEZ64;
353 case Mips::BLEZ64: return Mips::BGTZ64;
354 case Mips::BC1T: return Mips::BC1F;
355 case Mips::BC1F: return Mips::BC1T;
359 /// Adjust SP by Amount bytes.
360 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
361 MachineBasicBlock &MBB,
362 MachineBasicBlock::iterator I) const {
363 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
364 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
365 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
366 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
368 if (isInt<16>(Amount))// addi sp, sp, amount
369 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
370 else { // Expand immediate that doesn't fit in 16-bit.
371 unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr);
372 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill);
376 /// This function generates the sequence of instructions needed to get the
377 /// result of adding register REG and immediate IMM.
379 MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
380 MachineBasicBlock::iterator II, DebugLoc DL,
381 unsigned *NewImm) const {
382 MipsAnalyzeImmediate AnalyzeImm;
383 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
384 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
385 unsigned Size = STI.isABI_N64() ? 64 : 32;
386 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
387 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
388 const TargetRegisterClass *RC = STI.isABI_N64() ?
389 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
390 bool LastInstrIsADDiu = NewImm;
392 const MipsAnalyzeImmediate::InstSeq &Seq =
393 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
394 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
396 assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
398 // The first instruction can be a LUi, which is different from other
399 // instructions (ADDiu, ORI and SLL) in that it does not have a register
401 unsigned Reg = RegInfo.createVirtualRegister(RC);
403 if (Inst->Opc == LUi)
404 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
406 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
407 .addImm(SignExtend64<16>(Inst->ImmOpnd));
409 // Build the remaining instructions in Seq.
410 for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
411 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
412 .addImm(SignExtend64<16>(Inst->ImmOpnd));
414 if (LastInstrIsADDiu)
415 *NewImm = Inst->ImmOpnd;
420 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
421 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
422 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ ||
423 Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 ||
424 Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
425 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B ||
430 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
431 MachineBasicBlock::iterator I) const {
432 const auto &Subtarget = TM.getSubtarget<MipsSubtarget>();
434 if (Subtarget.isGP64bit())
435 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
436 .addReg(Mips::RA_64);
438 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn)).addReg(Mips::RA);
441 std::pair<bool, bool>
442 MipsSEInstrInfo::compareOpndSize(unsigned Opc,
443 const MachineFunction &MF) const {
444 const MCInstrDesc &Desc = get(Opc);
445 assert(Desc.NumOperands == 2 && "Unary instruction expected.");
446 const MipsRegisterInfo *RI = &getRegisterInfo();
447 unsigned DstRegSize = getRegClass(Desc, 0, RI, MF)->getSize();
448 unsigned SrcRegSize = getRegClass(Desc, 1, RI, MF)->getSize();
450 return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
453 void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB,
454 MachineBasicBlock::iterator I,
455 unsigned NewOpc) const {
456 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
459 void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
460 MachineBasicBlock::iterator I,
463 bool HasExplicitDef) const {
465 // lo_hi pseudomtlohi $gpr0, $gpr1
466 // to these two instructions:
470 DebugLoc DL = I->getDebugLoc();
471 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
472 MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
473 MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
474 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
475 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
477 // Add lo/hi registers if the mtlo/hi instructions created have explicit
479 if (HasExplicitDef) {
480 unsigned DstReg = I->getOperand(0).getReg();
481 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
482 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
483 LoInst.addReg(DstLo, RegState::Define);
484 HiInst.addReg(DstHi, RegState::Define);
488 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
489 MachineBasicBlock::iterator I,
490 unsigned CvtOpc, unsigned MovOpc,
492 const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
493 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
494 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
495 unsigned KillSrc = getKillRegState(Src.isKill());
496 DebugLoc DL = I->getDebugLoc();
497 bool DstIsLarger, SrcIsLarger;
499 std::tie(DstIsLarger, SrcIsLarger) =
500 compareOpndSize(CvtOpc, *MBB.getParent());
503 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
506 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
508 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
509 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
512 void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
513 MachineBasicBlock::iterator I,
515 const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
516 unsigned DstReg = I->getOperand(0).getReg();
517 unsigned SrcReg = I->getOperand(1).getReg();
518 unsigned N = I->getOperand(2).getImm();
519 DebugLoc dl = I->getDebugLoc();
521 assert(N < 2 && "Invalid immediate");
522 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
523 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
525 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
526 // in MipsSEFrameLowering.cpp.
527 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
529 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
530 // in MipsSEFrameLowering.cpp.
531 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
533 if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) {
534 // FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we
535 // claim to read the whole 64-bits as part of a white lie used to
536 // temporarily work around a widespread bug in the -mfp64 support.
537 // The problem is that none of the 32-bit fpu ops mention the fact
538 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
539 // requires a major overhaul of the FPU implementation which can't
540 // be done right now due to time constraints.
541 // MFHC1 is one of two instructions that are affected since they are
542 // the only instructions that don't read the lower 32-bits.
543 // We therefore pretend that it reads the bottom 32-bits to
544 // artificially create a dependency and prevent the scheduler
545 // changing the behaviour of the code.
546 BuildMI(MBB, I, dl, get(FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32), DstReg)
549 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
552 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
553 MachineBasicBlock::iterator I,
555 const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
556 unsigned DstReg = I->getOperand(0).getReg();
557 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
558 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
559 DebugLoc dl = I->getDebugLoc();
560 const TargetRegisterInfo &TRI = getRegisterInfo();
562 // When mthc1 is available, use:
566 // Otherwise, for O32 FPXX ABI:
567 // spill + reload via ldc1
568 // This case is handled by the frame lowering code.
570 // Otherwise, for FP32:
574 // The case where dmtc1 is available doesn't need to be handled here
575 // because it never creates a BuildPairF64 node.
577 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
578 // in MipsSEFrameLowering.cpp.
579 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
581 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
582 // in MipsSEFrameLowering.cpp.
583 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
585 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
588 if (Subtarget.hasMTHC1()) {
589 // FIXME: The .addReg(DstReg) is a white lie used to temporarily work
590 // around a widespread bug in the -mfp64 support.
591 // The problem is that none of the 32-bit fpu ops mention the fact
592 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
593 // requires a major overhaul of the FPU implementation which can't
594 // be done right now due to time constraints.
595 // MTHC1 is one of two instructions that are affected since they are
596 // the only instructions that don't read the lower 32-bits.
597 // We therefore pretend that it reads the bottom 32-bits to
598 // artificially create a dependency and prevent the scheduler
599 // changing the behaviour of the code.
600 BuildMI(MBB, I, dl, get(FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32), DstReg)
603 } else if (Subtarget.isABI_FPXX())
604 llvm_unreachable("BuildPairF64 not expanded in frame lowering code!");
606 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
610 void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
611 MachineBasicBlock::iterator I) const {
612 // This pseudo instruction is generated as part of the lowering of
613 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
614 // indirect jump to TargetReg
615 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
616 unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
617 unsigned SP = STI.isGP64bit() ? Mips::SP_64 : Mips::SP;
618 unsigned RA = STI.isGP64bit() ? Mips::RA_64 : Mips::RA;
619 unsigned T9 = STI.isGP64bit() ? Mips::T9_64 : Mips::T9;
620 unsigned ZERO = STI.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
621 unsigned OffsetReg = I->getOperand(0).getReg();
622 unsigned TargetReg = I->getOperand(1).getReg();
624 // addu $ra, $v0, $zero
625 // addu $sp, $sp, $v1
626 // jr $ra (via RetRA)
627 if (TM.getRelocationModel() == Reloc::PIC_)
628 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), T9)
629 .addReg(TargetReg).addReg(ZERO);
630 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), RA)
631 .addReg(TargetReg).addReg(ZERO);
632 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), SP)
633 .addReg(SP).addReg(OffsetReg);
637 const MipsInstrInfo *llvm::createMipsSEInstrInfo(MipsTargetMachine &TM) {
638 return new MipsSEInstrInfo(TM);