1 //===-- MipsSEInstrInfo.h - Mips32/64 Instruction Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSSEINSTRUCTIONINFO_H
15 #define MIPSSEINSTRUCTIONINFO_H
17 #include "MipsInstrInfo.h"
18 #include "MipsSERegisterInfo.h"
22 class MipsSEInstrInfo : public MipsInstrInfo {
23 const MipsSERegisterInfo RI;
27 explicit MipsSEInstrInfo(MipsTargetMachine &TM);
29 virtual const MipsRegisterInfo &getRegisterInfo() const;
31 /// isLoadFromStackSlot - If the specified machine instruction is a direct
32 /// load from a stack slot, return the virtual or physical register number of
33 /// the destination along with the FrameIndex of the loaded stack slot. If
34 /// not, return 0. This predicate must return 0 if the instruction has
35 /// any side effects other than loading from the stack slot.
36 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
37 int &FrameIndex) const;
39 /// isStoreToStackSlot - If the specified machine instruction is a direct
40 /// store to a stack slot, return the virtual or physical register number of
41 /// the source reg along with the FrameIndex of the loaded stack slot. If
42 /// not, return 0. This predicate must return 0 if the instruction has
43 /// any side effects other than storing to the stack slot.
44 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
45 int &FrameIndex) const;
47 virtual void copyPhysReg(MachineBasicBlock &MBB,
48 MachineBasicBlock::iterator MI, DebugLoc DL,
49 unsigned DestReg, unsigned SrcReg,
52 virtual void storeRegToStack(MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator MI,
54 unsigned SrcReg, bool isKill, int FrameIndex,
55 const TargetRegisterClass *RC,
56 const TargetRegisterInfo *TRI,
57 int64_t Offset) const;
59 virtual void loadRegFromStack(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator MI,
61 unsigned DestReg, int FrameIndex,
62 const TargetRegisterClass *RC,
63 const TargetRegisterInfo *TRI,
64 int64_t Offset) const;
66 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
68 virtual unsigned getOppositeBranchOpc(unsigned Opc) const;
70 /// Adjust SP by Amount bytes.
71 void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
72 MachineBasicBlock::iterator I) const;
74 /// Emit a series of instructions to load an immediate. If NewImm is a
75 /// non-NULL parameter, the last instruction is not emitted, but instead
76 /// its immediate operand is returned in NewImm.
77 unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
78 MachineBasicBlock::iterator II, DebugLoc DL,
79 unsigned *NewImm) const;
82 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const;
84 void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
87 std::pair<bool, bool> compareOpndSize(unsigned Opc) const;
89 /// Expand pseudo Int-to-FP conversion instructions.
91 /// For example, the following pseudo instruction
92 /// PseudoCVT_D32_W D2, A5
93 /// gets expanded into these two instructions:
97 /// We do this expansion post-RA to avoid inserting a floating point copy
98 /// instruction between MTC1 and CVT_D32_W.
99 void expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
100 unsigned CvtOpc, unsigned MovOpc, bool IsI64) const;
102 void expandExtractElementF64(MachineBasicBlock &MBB,
103 MachineBasicBlock::iterator I) const;
104 void expandBuildPairF64(MachineBasicBlock &MBB,
105 MachineBasicBlock::iterator I) const;
106 void expandDPLoadStore(MachineBasicBlock &MBB,
107 MachineBasicBlock::iterator I, unsigned OpcD,
108 unsigned OpcS) const;
109 void expandEhReturn(MachineBasicBlock &MBB,
110 MachineBasicBlock::iterator I) const;