1 //===-- MipsSEInstrInfo.h - Mips32/64 Instruction Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSEINSTRINFO_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSSEINSTRINFO_H
17 #include "MipsInstrInfo.h"
18 #include "MipsSERegisterInfo.h"
22 class MipsSEInstrInfo : public MipsInstrInfo {
23 const MipsSERegisterInfo RI;
26 explicit MipsSEInstrInfo(const MipsSubtarget &STI);
28 const MipsRegisterInfo &getRegisterInfo() const override;
30 /// isLoadFromStackSlot - If the specified machine instruction is a direct
31 /// load from a stack slot, return the virtual or physical register number of
32 /// the destination along with the FrameIndex of the loaded stack slot. If
33 /// not, return 0. This predicate must return 0 if the instruction has
34 /// any side effects other than loading from the stack slot.
35 unsigned isLoadFromStackSlot(const MachineInstr *MI,
36 int &FrameIndex) const override;
38 /// isStoreToStackSlot - If the specified machine instruction is a direct
39 /// store to a stack slot, return the virtual or physical register number of
40 /// the source reg along with the FrameIndex of the loaded stack slot. If
41 /// not, return 0. This predicate must return 0 if the instruction has
42 /// any side effects other than storing to the stack slot.
43 unsigned isStoreToStackSlot(const MachineInstr *MI,
44 int &FrameIndex) const override;
46 void copyPhysReg(MachineBasicBlock &MBB,
47 MachineBasicBlock::iterator MI, DebugLoc DL,
48 unsigned DestReg, unsigned SrcReg,
49 bool KillSrc) const override;
51 void storeRegToStack(MachineBasicBlock &MBB,
52 MachineBasicBlock::iterator MI,
53 unsigned SrcReg, bool isKill, int FrameIndex,
54 const TargetRegisterClass *RC,
55 const TargetRegisterInfo *TRI,
56 int64_t Offset) const override;
58 void loadRegFromStack(MachineBasicBlock &MBB,
59 MachineBasicBlock::iterator MI,
60 unsigned DestReg, int FrameIndex,
61 const TargetRegisterClass *RC,
62 const TargetRegisterInfo *TRI,
63 int64_t Offset) const override;
65 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
67 unsigned getOppositeBranchOpc(unsigned Opc) const override;
69 /// Adjust SP by Amount bytes.
70 void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
71 MachineBasicBlock::iterator I) const;
73 /// Emit a series of instructions to load an immediate. If NewImm is a
74 /// non-NULL parameter, the last instruction is not emitted, but instead
75 /// its immediate operand is returned in NewImm.
76 unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
77 MachineBasicBlock::iterator II, DebugLoc DL,
78 unsigned *NewImm) const;
81 unsigned getAnalyzableBrOpc(unsigned Opc) const override;
83 void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const;
85 std::pair<bool, bool> compareOpndSize(unsigned Opc,
86 const MachineFunction &MF) const;
88 void expandPseudoMFHiLo(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
89 unsigned NewOpc) const;
91 void expandPseudoMTLoHi(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
92 unsigned LoOpc, unsigned HiOpc,
93 bool HasExplicitDef) const;
95 /// Expand pseudo Int-to-FP conversion instructions.
97 /// For example, the following pseudo instruction
98 /// PseudoCVT_D32_W D2, A5
99 /// gets expanded into these two instructions:
103 /// We do this expansion post-RA to avoid inserting a floating point copy
104 /// instruction between MTC1 and CVT_D32_W.
105 void expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
106 unsigned CvtOpc, unsigned MovOpc, bool IsI64) const;
108 void expandExtractElementF64(MachineBasicBlock &MBB,
109 MachineBasicBlock::iterator I, bool FP64) const;
110 void expandBuildPairF64(MachineBasicBlock &MBB,
111 MachineBasicBlock::iterator I, bool FP64) const;
112 void expandEhReturn(MachineBasicBlock &MBB,
113 MachineBasicBlock::iterator I) const;