1 //===-- MipsSERegisterInfo.cpp - MIPS32/64 Register Information -== -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS32/64 implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #include "MipsSERegisterInfo.h"
17 #include "MipsAnalyzeImmediate.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSEInstrInfo.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Constants.h"
28 #include "llvm/IR/DebugInfo.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameLowering.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
42 MipsSERegisterInfo::MipsSERegisterInfo(const MipsSubtarget &ST)
43 : MipsRegisterInfo(ST) {}
45 bool MipsSERegisterInfo::
46 requiresRegisterScavenging(const MachineFunction &MF) const {
50 bool MipsSERegisterInfo::
51 requiresFrameIndexScavenging(const MachineFunction &MF) const {
55 const TargetRegisterClass *
56 MipsSERegisterInfo::intRegClass(unsigned Size) const {
58 return &Mips::GPR32RegClass;
61 return &Mips::GPR64RegClass;
64 /// Get the size of the offset supported by the given load/store.
65 /// The result includes the effects of any scale factors applied to the
66 /// instruction immediate.
67 static inline unsigned getLoadStoreOffsetSizeInBits(const unsigned Opcode) {
74 return 10 + 1 /* scale factor */;
77 return 10 + 2 /* scale factor */;
80 return 10 + 3 /* scale factor */;
86 /// Get the scale factor applied to the immediate in the given load/store.
87 static inline unsigned getLoadStoreOffsetAlign(const unsigned Opcode) {
103 void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
104 unsigned OpNo, int FrameIndex,
106 int64_t SPOffset) const {
107 MachineInstr &MI = *II;
108 MachineFunction &MF = *MI.getParent()->getParent();
109 MachineFrameInfo *MFI = MF.getFrameInfo();
110 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
112 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
117 MinCSFI = CSI[0].getFrameIdx();
118 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
121 bool EhDataRegFI = MipsFI->isEhDataRegFI(FrameIndex);
123 // The following stack frame objects are always referenced relative to $sp:
124 // 1. Outgoing arguments.
125 // 2. Pointer to dynamically allocated stack space.
126 // 3. Locations for callee-saved registers.
127 // 4. Locations for eh data registers.
128 // Everything else is referenced relative to whatever register
129 // getFrameRegister() returns.
132 if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI)
133 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
135 FrameReg = getFrameRegister(MF);
137 // Calculate final offset.
138 // - There is no need to change the offset if the frame object is one of the
139 // following: an outgoing argument, pointer to a dynamically allocated
140 // stack space or a $gp restore location,
141 // - If the frame object is any of the following, its offset must be adjusted
142 // by adding the size of the stack:
143 // incoming argument, callee-saved register location or local variable.
147 Offset = SPOffset + (int64_t)StackSize;
148 Offset += MI.getOperand(OpNo + 1).getImm();
150 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
152 if (!MI.isDebugValue()) {
153 // Make sure Offset fits within the field available.
154 // For MSA instructions, this is a 10-bit signed immediate (scaled by
155 // element size), otherwise it is a 16-bit signed immediate.
156 unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits(MI.getOpcode());
157 unsigned OffsetAlign = getLoadStoreOffsetAlign(MI.getOpcode());
159 if (OffsetBitSize < 16 && isInt<16>(Offset) &&
160 (!isIntN(OffsetBitSize, Offset) ||
161 OffsetToAlignment(Offset, OffsetAlign) != 0)) {
162 // If we have an offset that needs to fit into a signed n-bit immediate
163 // (where n < 16) and doesn't, but does fit into 16-bits then use an ADDiu
164 MachineBasicBlock &MBB = *MI.getParent();
165 DebugLoc DL = II->getDebugLoc();
166 unsigned ADDiu = Subtarget.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
167 const TargetRegisterClass *RC =
168 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
169 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
170 unsigned Reg = RegInfo.createVirtualRegister(RC);
171 const MipsSEInstrInfo &TII =
172 *static_cast<const MipsSEInstrInfo *>(
173 MBB.getParent()->getTarget().getInstrInfo());
174 BuildMI(MBB, II, DL, TII.get(ADDiu), Reg).addReg(FrameReg).addImm(Offset);
179 } else if (!isInt<16>(Offset)) {
180 // Otherwise split the offset into 16-bit pieces and add it in multiple
182 MachineBasicBlock &MBB = *MI.getParent();
183 DebugLoc DL = II->getDebugLoc();
184 unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
186 const MipsSEInstrInfo &TII =
187 *static_cast<const MipsSEInstrInfo *>(
188 MBB.getParent()->getTarget().getInstrInfo());
189 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL,
190 OffsetBitSize == 16 ? &NewImm : NULL);
191 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
192 .addReg(Reg, RegState::Kill);
195 Offset = SignExtend64<16>(NewImm);
200 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
201 MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);